ESDR0502N Ultra Low Capacitance ESD Protection Array for High Speed Data Line Protection The ESDR0502N ultra low capacitance TVS array is designed to protect high speed data lines from ESD. Ultra−low capacitance and high level of ESD protection makes this device well suited for use in USB 2.0 applications. http://onsemi.com 6 Features • • • • Low Capacitance (0.3 pF Typical Between I/O Lines and Ground) IEC 61000−4−2 Level 4 UL Flammability Rating of 94 V−0 These Devices are Pb−Free and are RoHS Compliant 1 4 5 Typical Applications • • • • • High Speed Communication Line Protection USB 2.0 High Speed Data Line and Power Line Protection Monitors and Flat Panel Displays MP3 Gigabit Ethernet UDFN6 MU SUFFIX CASE 517AA MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) MARKING DIAGRAM Rating Symbol Value Unit Operating Junction Temperature Range TJ −40 to +125 °C Peak Power Dissipation 8x20 ms @ TA = 25°C (Note 1) Ppk 100 W Peak Power Current 8x20 ms @ TA = 25°C (Note 1) Ipp 3.0 A Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD 8.0 kV IEC 61000−4−2 Contact (ESD) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Nonrepetitive current pulse (pin 6 to pin 1). DM G D M G = Specific Device Code* (Rotated 90° clockwise) = Date Code & Assembly Location = Pb−Free Device PINOUT GND 1 6 VBUS NC 2 5 D+ NC 3 4 D− (Top View) ORDERING INFORMATION Device Package Shipping† ESDR0502NMUTBG UDFN6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 0 1 Publication Order Number: ESDR0502N/D ESDR0502N ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol I Parameter IF IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR Working Peak Reverse Voltage Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C VC VBR VRWM Maximum Reverse Leakage Current @ VRWM IPP Uni−Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Symbol VRWM VBR Conditions Min Typ (Note 2) IT = 1 mA, (Note 3) Max Unit 5.5 V 6.0 Reverse Leakage Current IR VRWM = 5.5 V ESD Clamping Voltage VC Per IEC61000−4−2 (Note 4) Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins V 1.0 mA 0.3 0.6 pF 0.3 0.6 pF See Figures 1 & 2 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 ESDR0502N IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 3 80 ESDR0502N APPLICATION INFORMATION Protecting USB 2.0 Interfaces voltage (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away from the protected controller chip. The TVS diode suppresses ESD strikes directly on the voltage bus and directs the surge to ground, protecting both the power and data pins. The USB interface consists of Data (D− and D+) lines and a 5.5 V bus, which are all vulnerable to ESD and cable discharge events. Each ESDR0502N device will protect the four USB connections (VCC, D+, D−, and GND) of one USB port. When the voltage on the data lines exceed the bus USB Controller USB Connector 1 6 VBUS D+ 2 5 D+ D− 3 4 D− ESDR0502N GND Figure 6. http://onsemi.com 4 ESDR0502N PACKAGE DIMENSIONS UDFN6, 1.2x1.0, 0.4P CASE 517AA−01 ISSUE C EDGE OF PACKAGE PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ ÉÉ L1 E DETAIL A Bottom View (Optional) TOP VIEW 2X EXPOSED Cu 0.10 C (A3) 0.10 C A1 A 10X 0.08 C ÉÉÉ ÉÉÉ A3 DETAIL B Side View (Optional) 5X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.30 0.40 0.00 0.15 0.40 0.50 MOUNTING FOOTPRINT* 6X C A1 DIM A A1 A3 b D E e L L1 L2 MOLD CMPD SEATING PLANE SIDE VIEW 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D 6X 0.42 0.22 L 3 L2 6X b 0.10 C A B 0.05 C 6 4 0.40 PITCH e NOTE 3 1.07 DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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