High Frequency Divider/PLL Synthesizer ADF4007 FEATURES GENERAL DESCRIPTION 7.5 GHz bandwidth Maximum PFD frequency of 120 MHz Divide ratios of 8, 16, 32, or 64 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems RSET contol of charge pump current Hardware power-down mode The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider/prescaler. The divider/ prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz. APPLICATIONS A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. Satellite communications Broadband wireless access CATV Instrumentation Wireless LANs FUNCTIONAL BLOCK DIAGRAM VP VDD CPGND REFERENCE ADF4007 REFIN R COUNTER ÷2 RFINA N COUNTER ÷ 8, ÷ 16, ÷ 32, ÷ 64 PHASE FREQUENCY DETECTOR CHARGE PUMP CP MUXOUT MUX 04537-0-001 RFINB RSET N2 N1 GND M2 M1 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADF4007 TABLE OF CONTENTS Specifications..................................................................................... 3 R Counter .......................................................................................9 Absolute Maximum Ratings............................................................ 4 Phase Frequency Detector (PFD) and Charge Pump...............9 ESD Caution.................................................................................. 4 MUXOUT ................................................................................... 10 Pin Configuration and Function Descriptions............................. 5 Applications..................................................................................... 11 Typical Performance Characteristics ............................................. 7 Fixed High Frequency Local Oscillator................................... 11 Theory of Operation ........................................................................ 9 Using the ADF4007 as a Divider .............................................. 12 Reference Input Section............................................................... 9 PCB Design Guidelines for Chip Scale Package......................... 13 RF Input Stage............................................................................... 9 Outline Dimensions ....................................................................... 14 Prescaler P ..................................................................................... 9 Ordering Guide .......................................................................... 14 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADF4007 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Frequency REFIN CHARACTERISTICS REFIN Input Sensitivity REFIN Input Frequency REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency3 MUXOUT MUXOUT Frequency3 CHARGE PUMP ICP Sink/Source Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD4 (AIDD + DIDD) IP NOISE CHARACTERISTICS Normalized Phase Noise Floor5 B Version1 Unit Test Conditions/Comments 1.0/7.0 0.5/7.5 GHz min/max GHz min/max RF input level: +5 dBm to −10 dBm RF input level: +5 dBm to −5 dBm For lower frequencies, ensure that slew rate (SR) > 560 V/µs 0.8/VDD 20/240 10 ±100 V p-p min/max MHz min/max pF max µA max Biased at AVDD/22 For f < 20 MHz, use square wave (slew rate > 50 V/µs) 120 MHz max 200 MHz max CL = 15 pF 5.0 2.5 3.0/11 10 2 1.5 2 mA typ % typ kΩ typ nA max % typ % typ % typ With RSET = 5.1 kΩ With RSET = 5.1 kΩ 1.4 0.6 ±1 10 V min V max µA max pF max VDD − 0.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 17 2.0 V min/max V min/max mA max mA max −219 dBc/Hz typ 1 TA = 85°C 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 TA = 25°C IOH = 100 µA IOL = 500 µA AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C Operating temperature range (B version) is −40°C to +85°C. AC coupling ensures AVDD/2 bias. See Figure 13 for typical circuit. 3 Guaranteed by design. Characterized to ensure compliance. 4 TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN TOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent. 2 Rev. 0 | Page 3 of 16 ADF4007 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Transistor Count CMOS Bipolar 1 Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 122°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 215°C 220°C 6425 303 GND = AGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 16 ADF4007 20 CP 19 RSET 18 VP 17 DVDD 16 DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADF4007 TOPVIEW 15 MUXOUT 14 M1 13 M2 12 N1 11 N2 04537-0-002 PIN1 INDICATOR AVDD 6 AVDD 7 REF IN 8 DGND 9 DGND 10 CPGND 1 AGND 2 AGND 3 RFIN B 4 RFIN A 5 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2, 3 4 Mnemonic CPGND AGND RFINB 5 6, 7 RFINA AVDD 8 REFIN 9, 10 11, 12 13, 14 15 16, 17 DGND N2, N1 M2, M1 MUXOUT DVDD 18 VP 19 RSET 20 CP Function Charge Pump Ground. The ground return path of the charge pump. Analog Ground. The ground return path of the prescaler. Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. A CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. These two bits set the N value. See Table 4. These two bits set the status of MUXOUT and PFD polarity. See Table 5. This multiplexer output allows either the N divider output or the R divider output to be accessed externally. Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This pin should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V. Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is 25.5 I CP MAX = R SET Therefore, if RSET = 5.1 kΩ, then ICP = 5 mA. Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO. Rev. 0 | Page 5 of 16 ADF4007 Table 4. N Truth Table N2 0 0 1 1 N1 0 1 0 1 Table 5. M Truth Table N Value 8 16 32 64 M2 0 M1 0 0 1 1 0 1 1 Rev. 0 | Page 6 of 16 Operation CP: MUXOUT: PFD polarity: CP: MUXOUT: PFD polarity: CP: MUXOUT: PFD polarity: CP: MUXOUT: PFD polarity: Active VDD +ve Three-state R divider output +ve Active N divider output +ve Active GND −ve ADF4007 TYPICAL PERFORMANCE CHARACTERISTICS Table 6. S-Parameter Data for the RF Input Frequency1 0.60000 0.70000 0.80000 0.90000 1.00000 1.10000 1.20000 1.30000 1.40000 1.50000 1.60000 1.70000 1.80000 1.90000 2.00000 2.10000 2.20000 2.30000 2.40000 2.50000 2.60000 2.70000 2.80000 2.90000 3.00000 3.10000 3.20000 3.30000 3.40000 3.50000 3.60000 3.70000 3.80000 3.90000 4.00000 4.10000 MagS11 0.87693 0.85834 0.85044 0.83494 0.81718 0.80229 0.78917 0.77598 0.75578 0.74437 0.73821 0.72530 0.71365 0.70699 0.70380 0.69284 0.67717 0.67107 0.66556 0.65640 0.63330 0.61406 0.59770 0.56550 0.54280 0.51733 0.49909 0.47309 0.45694 0.44698 0.43589 0.42472 0.41175 0.41055 0.40983 0.40182 AngS11 −19.9279 −23.5610 −26.9578 −30.8201 −34.9499 −39.0436 −42.3623 −46.3220 −50.3484 −54.3545 −57.3785 −60.6950 −63.9152 −66.4365 −68.4453 −70.7986 −73.7038 −75.8206 −77.6851 −80.3101 −82.5082 −85.5623 −87.3513 −89.7605 −93.0239 −95.9754 −99.1291 −102.208 −106.794 −111.659 −117.986 −125.620 −133.291 −140.585 −147.970 −155.978 Frequency1 4.20000 4.30000 4.40000 4.50000 4.60000 4.70000 4.80000 4.90000 5.00000 5.10000 5.20000 5.30000 5.40000 5.50000 5.60000 5.70000 5.80000 5.90000 6.00000 6.10000 6.20000 6.30000 6.40000 6.50000 6.60000 6.70000 6.80000 6.90000 7.00000 7.10000 7.20000 7.30000 7.40000 7.50000 1 Frequency unit: GHz; parameter type: s; data format: MA; keyword: R; impedance: 50. Rev. 0 | Page 7 of 16 MagS11 0.41036 0.41731 0.43126 0.42959 0.42687 0.43450 0.42275 0.40662 0.39103 0.37761 0.34263 0.30124 0.27073 0.23590 0.17550 0.12739 0.09058 0.06824 0.04465 0.04376 0.06621 0.08498 0.10862 0.12161 0.12917 0.12716 0.11678 0.10533 0.09643 0.08919 0.08774 0.09289 0.10803 0.13956 AngS11 −162.939 −168.232 −174.663 −179.797 174.379 171.537 167.201 163.534 159.829 157.633 152.815 147.632 144.304 138.324 131.087 124.568 119.823 114.960 84.4391 34.2210 4.70571 −12.6228 −26.6069 −38.5860 −47.1990 −55.8515 −63.0234 −66.9967 −75.4961 −89.2055 −103.786 −127.153 −150.582 −170.971 ADF4007 0 0 VDD = 3V VP = 3V –5 REF LEVEL = –14.0dBm –10 –15 –20 TA = +85°C –25 TA = +25°C –30 –30 OUTPUT POWER (dB) RF INPUT POWER (dBm) –20 –10 TA = –40°C –40 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 106MHz LOOP BANDWIDTH = 1MHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5s AVERAGES = 30 –50 –60 –70 –91.0dBc/Hz 04537-0-007 –80 –35 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 RF INPUT FREQUENCY (GHz) 04537-0-003 –90 –40 –100 –212 –106 6780 106 FREQUENCY (MHz) 212 Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop Bandwidth) Figure 3. Input Sensitivity –120 0 VDD = 3V VP = 5V REF LEVEL = –14.3dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 106kHz LOOP BANDWIDTH = 1MHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9s AVERAGES = 10 –30 –40 –130 –50 –60 –70 –99dBc/Hz –90 –100 –2k –1k 6780M FREQUENCY (Hz) 1k –150 –160 –170 04537-0-005 –80 –140 –180 10k 2k 100k 1M 10M PHASE DETECTOR FREQUENCY (Hz) –40 –6 10dB/DIV RL = –40dBc/Hz RMS NOISE = 4.2° –5 VP = 5V ICP = 5mA –4 –60 –3 –70 –2 ICP (mA) –80 –90 –100 –1 0 1 2 –110 3 –120 100k 1M 10M FREQUENCY OFFSET FROM CARRIER (Hz) 04537-0-014 –130 –140 10k 4 04537-0-006 PHASE NOISE (dBc/Hz) 120M Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop Bandwidth) –50 04537-0-013 OUTPUT POWER (dB) –20 PHASE NOISE (dBc/Hz) –10 5 6 0 100M 0.5 1.0 1.5 2.0 2.5 3.0 VCP (V) 3.5 4.0 Figure 8. Charge Pump Output Characteristics Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop Bandwidth) Rev. 0 | Page 8 of 16 4.5 5.0 ADF4007 THEORY OF OPERATION REFERENCE INPUT SECTION PRESCALER P The reference input stage is shown in Figure 9. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the PFD. The prescaler can be selected to be either 8, 16, 32, or 64, and is effectively the N value in the PLL synthesizer. The terms N and P are used interchangeably in this data sheet. N1 and N2 set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 120 MHz, the maximum specified PFD frequency. Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is valid, but a value of 32 or less is not valid. POWER-DOWN CONTROL NC 100kΩ SW2 TO R COUNTER NC SW1 NO SW3 Figure 9. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 10 . It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. BIAS GENERATOR 500Ω 1.6V AVDD 500Ω f REFIN 2 f VCO = [N ] × BUFFER 04537-0-015 REFIN R COUNTER The R counter is permanently set to 2. It allows the input reference frequency to be divided down by 2 to produce the reference clock to the phase frequency detector (PFD). PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and the N counter (prescaler, P) and produces an output proportional to the phase and frequency difference between them. Figure 11 is a simplified schematic. The PFD includes a fixed, 3 ns delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. RFINA VP CHARGE PUMP RFINB 04537-0-016 LOGIC HI D1 Q1 UP U1 R DIVIDER CLR1 AGND 3ns DELAY Figure 10. RF Input Stage CP CLR2 DOWN D2 Q2 U2 N DIVIDER CPGND Figure 11. PFD Simplified Schematic and Timing (In Lock) Rev. 0 | Page 9 of 16 04537-0-017 LOGIC HI U3 ADF4007 MUXOUT PFD Polarity The output multiplexer on the ADF4007 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by the M2 and M1 pins. Figure 12 shows the MUXOUT section in block diagram form. The PFD polarity is set by the state of M2 and M1 pins as given in the Table 5. The ability to set the polarity allows the use of VCOs with either positive or negative tuning characteristics. For standard VCOs with positive characteristics (output frequency increases with increasing tuning voltage), the polarity should be set to positive. This is accomplished by tying M2 and M1 to a logic low state. DVDD DVDD R COUNTER OUTPUT CP Output MUX CONTROL MUXOUT N COUNTER OUTPUT DGND 04537-0-018 DGND The CP output state is also controlled by the state of M2 and M1. It can be set either to active (so that the loop can be locked) or to three-state (open the loop). The normal state is CP output active. Figure 12. MUXOUT Circuit Rev. 0 | Page 10 of 16 ADF4007 APPLICATIONS FIXED HIGH FREQUENCY LOCAL OSCILLATOR Figure 13 shows the ADF4007 being used with the HMC358MS8G VCO from Hittite Microwave Corporation to produce a fixed-frequency LO (local oscillator), which could be used in satellite or CATV applications. In this case, the desired LO is 6.7 GHz. Other PLL system specifications are as follows: KD = 5 mA KV = 100 MHz/V Loop Bandwidth = 300 kHz FPFD = 106 MHz N = 64 The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω. Many systems would have either a TCXO or an OCXO driving the reference input without any 50 Ω termination. To bias the REFIN pin at AVDD/2, ac coupling is used. The value of the coupling capacitor used depends on the input frequency. The equivalent impedance at the input frequency should be less than 10 Ω. Given that the dc input impedance at the REFIN pin is 100 kΩ, less than 0.1% of the signal is lost. All these specifications are needed and used with the ADIsimPLL to derive the loop filter component values shown in Figure 13. The circuit in Figure 13 gives a typical phase noise performance of −100 dBc/Hz at 10 kHz offset from the carrier. Spurs are heavily attenuated by the loop filter and are below −90 dBc. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer and also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer. The charge pump output of the ADF4007 drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system is 45°. VCC = 3.3V AVDD = 3.3V 18kΩ 7 6 16 18 17 5 4 RFINA 1kΩ AD820 CP 20 10pF 22Ω 100pF 18Ω 18Ω 100pF RFOUT VCO 100MHz/V 47nF ADF4007 100pF FREFIN 8 REFIN LOGIC HI 11 N2 LOGIC HI 12 N1 LOGIC LO 13 M2 LOGIC LO 14 M1 19 RSET MUXOUT 15 GND 2 3 9 100pF NOTE DECOUPLING CAPACITORS (0.1mF/10pF) ON AVDD, DVDD, AND VP OF THE ADF4007 AND ON VCC OF THE AD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 13. 6.78 GHz Local Oscillator Using the ADF4007 Rev. 0 | Page 11 of 16 04537-0-019 GND GND 10 RSET 5.1kΩ GND 51Ω HMC358MS8G RFINB 5.6nF 100pF 18Ω VCC = 12V 1kΩ VP AVDD AVDD DVDD DVDD ADF4007 USING THE ADF4007 AS A DIVIDER In addition to its use as a standard PLL synthesizer, the ADF4007 can also be used as a high frequency counter/divider with a value of 8, 16, 32, or 64.This can prove useful in a wide variety of applications where a higher frequency signal is readily available. Figure 14 shows the ADF4007 used in this manner with the ADF4360-7. This part is an integrated synthesizer and VCO, in this case operating over a range of 1200 MHz to 1500 MHz. With divideby-8 chosen in the ADF4007 (N2 = 0, N1 = 0), the output range is 150 MHz to 187.50 MHz. VDD VDD VVCO LOCK DETECT 4.7kΩ 10µF 6 2 21 RSET 20 23 VVCO DVDD AVDD 14 CN 13kΩ CHARGE PUMP CP 24 1nF 1nF FREFIN VP CP M2 AVDD DVDD M1 MUXOUT VTUNE 7 CE 16 REF IN 6.8nF 470pF 51Ω PHASE FREQUENCY DETECTOR MUXOUT CMOS OUTPUT MUX 220pF 6.2kΩ 17 CLK ADF4360-7 18 DATA VVCO 12 C C 51Ω 13 RSET 1nF RFOUTA 4 4.7kΩ CPGND 1 AGND 3 8 DGND 11 22 15 L1 L2 9 10 RFOUTB 5 51Ω REFIN R COUNTER ÷2 RFINA 100pF RFINB 100pF CPGND GND 2.2nH N COUNTER ÷8, ÷16 ÷32, ÷64 N1 N2 ADF4007 2.2nH 04537-0-020 SPI COMPATIBLE SERIAL BUS 19 LE Figure 14. Using the ADF4007 to Divide-Down the Output of the ADF4360-7 Rev. 0 | Page 12 of 16 ADF4007 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad to ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. The printed circuit board should have a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.30 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. 0 | Page 13 of 16 ADF4007 OUTLINE DIMENSIONS 0.60 MAX 4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR 3.75 BSC SQ TOP VIEW 11 10 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 0.20 REF 2.25 2.10 SQ 1.95 6 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC 20 1 BOTTOM VIEW 0.75 0.55 0.35 SEATING PLANE 16 15 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 15. 20-Lead Frame Chip Scale Package [LFCSP] (CP-20) Dimensions shown in millimeters ORDERING GUIDE Model ADF4007BCP ADF4007BCP–REEL ADF4007BCP–REEL7 Temperature Range −40°C to + 85°C −40°C to + 85°C −40°C to + 85°C Package Description 20-lead frame chip scale package (LFCSP) 20-lead frame chip scale package (LFCSP) 20-lead frame chip scale package (LFCSP) CP = chip scale package. Rev. 0 | Page 14 of 16 Package Option CP-20 CP-20 CP-20 ADF4007 NOTES Rev. 0 | Page 15 of 16 ADF4007 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04537–0–2/04(0) Rev. 0 | Page 16 of 16