AGILENT HDMP-0480

Agilent HDMP-0480
Octal Cell Port Bypass Circuit
without Clock and Data Recovery
Data Sheet
Features
• Supports 1.0625 GBd fibre channel
operation
Description
The HDMP-0480 is an Octal Cell
Port Bypass Circuit (PBC). This
device minimizes part count, cost
and jitter accumulation. Port
Bypass Circuits are used in hard
disk arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. By using Port
Bypass Circuits, hard disks may
be pulled out or swapped while
other disks in the array are
available to the system.
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplexers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk by-passed”. When the “disk
in loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data
goes from the HDMP-0480’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx± differential outputs goes to
the HDMP- 0480’s FM_NODE[n]±
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the “disk in
loop” mode. HDMP-0480’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
TO_NODE pins to accommodate
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0480 may also be used
as eight 1:1 buffers. In addition,
an HDMP-0480 may be configured as four 2:1 multiplexers or
as four 1:2 buffers.
• Supports 1.25 GBd gigabit Ethernet
(GE) operation
• Octal cell PBC in one package
• Valid amplitude detection on
FM_NODE[7] input
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 0.76 W typical power at Vcc=3.3V
• 64 Pin, 10 mm, low cost plastic QFP
package
Applications
• RAID, JBOD, BTS cabinets
• Four 2:1 muxes
• Four 1:2 buffers
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux
HDMP-0480
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and
assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
2
3
4
5
6
7
0
BYPASS2
BYPASS3
BYPASS4
BYPASS5
BYPASS6
BYPASS7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
BYPASS0
BYPASS1
AV
FM_NODE(7)_AV
1
Figure 1. Block Diagram of HDMP-0480.
HDMP-0480 Block Diagram
AV Output
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[7]± is valid by examining the differential amplitude
of that input. The incoming data
is considered valid, and
FM_NODE[7]_AV is driven high,
as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[7]_AV
is driven low as long as the
amplitude of the input signal is
less than 100 mV (differential
peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential
peak-to-peak), FM_NODE[7]_AV
is unpredictable.
2
BLL Output
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0480 are of
equal strength and can drive in
excess of 120 inches of FR-4 PCB
trace. Unused outputs should not
be left unconnected. Ideally,
unused outputs should have their
differential pins shorted together
with a short PCB trace. If transmission lines are connected to
the output pins, the lines should
be differentially terminated with
an appropriate resistor. The value
of the termination resistor should
match the PCB trace differential
impedance.
EQU Input
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs.
BYPASS[N]- Input
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0480. All BYPASS pins are
LVTTL and contain internal pullup circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1kΩ resistor. Otherwise, the BYPASS[n]- inputs
should be left to float. In this
case, the internal pull-up circuitry will force them high.
GND
GND
GND
VCC
GND
GND
VCC
GND
GND
GND
GND
BYPASS[0]FM_NODE[7]_AV
FM_NODE[0]FM_NODE[0]+
BYPASS[5]-
FM_NODE[5]-
FM_NODE[5]+
GND
FM_NODE[6]-
FM_NODE[6]+
BYPASS[6]-
TO_NODE[6]-
TO_NODE[6]+
VCCHS
TO_NODE[7]-
TO_NODE[7]+
GND
FM_NODE[7]-
FM_NODE[7]+
VCC
BYPASS[7]-
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
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5
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6
42
7
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Agilent
HDMP-0480
nnnn-nnn Rz.zz
S YYWW
VCCHS
TO_NODE[5]+
TO_NODE[5]VCCHS
TO_NODE[4]+
TO_NODE[4]BYPASS[4]FM_NODE[4]+
FM_NODE[4]GND
FM_NODE[3]+
FM_NODE[3]BYPASS[3]TO_NODE[3]+
TO_NODE[3]VCCHS
TO_NODE[2]+
TO_NODE[2]-
BYPASS[2]-
FM_NODE[2]+
FM_NODE[2]-
VCC
FM_NODE[1]+
FM_NODE[1]-
BYPASS[1]-
TO_NODE[1]+
TO_NODE[1]-
VCCHS
TO_NODE[0]+
TO_NODE[0]-
GND
VCC
Figure 2. HDMP-0480 Package Layout and Marking, Top View.
nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code (YY = year, WW = work week);
COUNTRY = country of manufacture (on back side).
I/O Type Definitions
I/O Type
Definition
I-LVTTL
LVTTL Input
O-LVTTL
LVTTL Output
HS_OUT
High Speed Output, LVPECL Compatible
HS_IN
High Speed Input
C
External circuit node
S
Power supply or ground
3
Table 1. Pin Definitions for HDMP-0480.
Pin Name
Pin
Pin Type
Pin Description
TO_NODE[0]+
TO_NODE[0]TO_NODE[1]+
TO_NODE[1]TO_NODE[2]+
TO_NODE[2]TO_NODE[3]+
TO_NODE[3]TO_NODE[4]+
TO_NODE[4]TO_NODE[5]+
TO_NODE[5]TO_NODE[6]+
TO_NODE[6]TO_NODE[7]+
TO_NODE[7]-
20
19
23
22
32
31
35
34
44
43
47
46
57
56
60
59
HS_OUT
Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
FM_NODE[0]+
FM_NODE[0]FM_NODE[1]+
FM_NODE[1]FM_NODE[2]+
FM_NODE[2]FM_NODE[3]+
FM_NODE[3]FM_NODE[4]+
FM_NODE[4]FM_NODE[5]+
FM_NODE[5]FM_NODE[6]+
FM_NODE[6]FM_NODE[7]+
FM_NODE[7]-
16
15
26
25
29
28
38
37
41
40
51
50
54
53
63
62
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
BYPASS[0]BYPASS[1]BYPASS[2]BYPASS[3]BYPASS[4]BYPASS[5]BYPASS[6]BYPASS[7]-
13
24
30
36
42
49
55
1
I-LVTTL
Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]- to GND through a1k resistor.
For “disk in loop” mode, float HIGH.
FM_NODE[7]_AV
14
O-LVTTL
Amplitude Valid: Indicates acceptable signal amplitude on the FM_NODE[7]± inputs.
If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1
If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable
If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-), FM_NODE[7]_AV = 0
Table 1 is continued on next page.
4
Table 1. Pin Definitions for HDMP-0480, continued
Pin Name
Pin
Pin Type
Pin Description
GND
2
3
4
6
7
9
10
11
12
18
39
52
61
S
Ground: Normally 0 volts. See Figure 7 for Recommended Power Supply Filtering.
VCCHS[0,1]
VCCHS[2,3]
VCCHS[4]
VCCHS[5]
VCCHS[6,7]
21
33
45
48
58
S
High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs (TO_NODE[n]).
See Figure 7 for Recommended Power Supply Filtering.
VCC
5
8
17
27
64
S
Logic Power Supply: Normally 3.3 volts. Used for internal logic.
See Figure 7 for Recommended Power Supply Filtering.
HDMP-0480 Absolute Maximum Ratings
Ta=25° C, except as specified. Operation in excess of any of these conditions may result in permanent
damage to this device. Ta refers to the ambient temperature for the board upon which the parametric
measurements were taken.
Symbol
Parameters
Units
Min.
Max.
VCC
Supply Voltage
V
-0.7
4.0
VIN, LVTTL
LVTTL Input Voltage
V
-0.7
4.0
VIN, HS_IN
HS_IN Input Voltage
V
1.3
VCC
IO, LVTTL
LVTTL Output Voltage
mA
Tstg
Storage Temperature
°C
-65
+150
Tj
Junction Temperature
°C
0
+125
±13
HDMP-0480 Guaranteed Operating Rates, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Serial Clock Rate
FC (MBd)
Min.
Max.
Serial Clock Rate
GE (MBd)
Min.
Max.
1,040
1,240
5
1,080
1,260
HDMP-0480 DC Electrical Specifications, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameters
Min.
VIH,LVTTL
LVTTL Input High Voltage Range
VIL,LVTTL
Typ.
Max.
Units
2.0
4.0
V
LVTTL Input Low Voltage Range
0
0.8
V
VOH,LVTTL
LVTTL Output High Voltage Range, IOH = -400 µA
2.2
3.45
V
VOL,LVTTL
LVTTL Output Low Voltage Level, IOL = 1 mA
0
0.6
V
IIH,LVTTL
Input High Current (Magnitude), VIN = 2.4V, VCC = 3.45V
.003
40
µA
IIL,LVTTL
Input Low Current (Magnitude), VIN = 0.4V, VCC = 3.45V
300
600
µA
ICC
Total Supply Current, Ta = 25°C
230
280
mA
Typ.
Max.
Units
HDMP-0480 AC Electrical Specifications, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameters
Min.
tloop
Total Loop Latency from FM_NODE[0] to TO_NODE[0]
0.9
2.0
ns
tcell
Per Cell Latency from FM_NODE[7] to TO_NODE[0]
0.5
0.8
ns
tr,LVTTLin
Input LVTTL Rise Time Requirement, 0.8V to 2.0V
2
ns
tf,LVTTLin
Input LVTTL Fall Time Requirement, 2.0V to 0.8V
2
ns
trs,HS_OUT
HS_OUT Single-Ended Rise Time, 20%-80%
200
tfs,HS_OUT
HS_OUT Single-Ended Rise Time, 20%-80%
200
350
ps
trd,HS_OUT
HS_OUT Differential Rise Time, 20%-80%
200
350
ps
tfd,HS_OUT
HS_OUT Differential Rise Time, 20%-80%
200
350
ps
VIP,HS_IN
HS_IN Input Peak to Peak Required Differential Voltage Range
200
1200
2000
mV
VOP,HS_OUT
HS_OUT Output Pk-Pk Diff. Voltage Range (Z0 = 75Ω, Fig. 5)
1100
1400
2000
mV
350
HDMP-0480 Power Dissipation, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameters
Unit
Typ.
Max.
PD
Power Dissipation
mW
760
970
6
ps
Figure 3. Eye Diagram of TO_NODE[1]± High Speed Differential Output.
Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0]±.
7
O-LVTTL
I-LVTTL
Vcc
Vcc
Vcc
Vbb
1.4V
GND
ESD
Protection
ESD
Protection
GND
GND
Figure 4. O-LVTTL and I-LVTTL Simplified Circuit Schematic.
HS_OUT
HS_IN
VCCHS
VCC
+
–
VCC
VCC
+
–
75 Ohms
ZO = 75Ω
TO_NODE[n]+
FM_NODE[n]+
0.01 µF
2 * ZO = 150Ω
ZO = 75Ω
FM_NODE[n]-
TO_NODE[n]-
ESD
Protection
0.01 µF
GND
GND
GND
ESD
Protection
GND
Figure 5. HS_OUT and HS_IN Simplified Circuit Schematic.
Note: FM_NODE[n] inputs should never be connected to ground as permanent damage to the device may result.
8
Package Information
HDMP-0480 Thermal Characteristics, TC = 0°C to +85°C, VCC = 3.15V to 3.45V
Symbol
Parameter
Unit
Typ.
Max.
θ jc
Thermal Resistance, Junction to Case
°C/W
10
—
Note: Based on independent testing by Agilent. θja for these devices is 56°C/W for the HDMP-0480.
θja is measured on a standard 3x3” FR4 PCB in a still air environment. To determine the actual
junction temperature in a given application, use the following equation: Tj = TC + (θjc x PD), where TC
is the case temperature measured on the top center of the package, and PD is the power being
dissipated.
Item
Details
Package Material
Plastic
Lead Finish Material
85% Tin, 15% Lead
Lead Finish Thickness
300 – 800 micro-inches
Lead Skew
0.08 mm max.
Lead Coplanarity
(Seating Plane Method)
0.08 mm max.
Pin #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
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40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
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10.00 ± 0.10
13.20 ± 0.25
10.00 ± 0.10
13.20 ± 0.25
Top View
2.00 + 0.10,
- 0.05
2.45 MAX.
0.17 MAX.
0.25 MIN.
All dimensions shown in mm
Figure 6. HDMP-0480 Package Drawing.
9
Seating
Plane
0.22 ± 0.05
0.50
BASIC
0.88
+ 0.15, - 0.10
0.25
Gauge
Plane
GND
GND
VCC
GND
GND
VCC
GND
GND
GND
VCC
VCC
VCC
Figure 7. Recommended Power Supply Filtering. Capacitors = 0.1 µF.
10
VCC
VCC
HDMP-0480
GND
GND
GND
VCC
GND
VCC
GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
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GND
VCC
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
October 24, 2001
5988-4186EN