a 5 V, Rail-to-Rail, High-Output Current, xDSL Line Drive Amplifier AD8018 FEATURES Ideal xDSL Line Drive Amplifier for USB, PCMCIA, or PCI-Based Customer Premise Equipment (CPE). The AD8018 provides maximum reach on 5 V supply, driving 16 dBm of power into a back-terminated, transformer-coupled 100 ⍀ while maintaining –82 dBc of out-of-band SFDR. Rail-to-Rail Output Voltage and High Output Current Drive 400 mA Output Current into Differential Load of 10 ⍀ @ 8 V p-p Low Single-Tone Distortion –86 dBc Worst Harmonic, 6 V p-p into Differential 10 ⍀ @ 100 kHz Low Noise 4.5 nV/√Hz Voltage Noise Density, 100 kHz Out-of-Band SFDR = –82 dBc, 144 kHz to 500 kHz, R LOAD = 12.5 ⍀, PLINE = 13 dBm Low-Power Operation 3.3 V to 8 V Power Supply Range Two Logic Bits for Standby and Shutdown Low Supply Current of 9 mA/Amplifier (Typ) Current Feedback Amplifiers High Speed 130 MHz Bandwidth (–3 dB) 300 V/s Slew Rate APPLICATIONS xDSL USB, PCI, PCMCIA Cards Consumer DSL Modems Twisted Pair Line Driver –30 N = 4.0 –40 VS = 5V SFDR – dBc –50 VS = 3.3V PIN CONFIGURATIONS 8-Lead SOIC (Thermal Coastline) OUT1 1 8 ⴙVS –IN1 2 7 OUT2 ⴙIN1 3 6 –IN2 –VS 4 5 ⴙIN2 12 ⴙIN2 PWDN1 6 13 PWDN0 14 DGND Fabricated with ADI’s high-speed XFCB (eXtra Fast Complementary Bipolar) process, the high bandwidth and fast slew rate of the AD8018 keep distortion to a minimum, while dissipating a minimum of power. The quiescent current of the AD8018 is a low 9 mA/amplifier. The AD8018 drive capability comes in compact 8-lead Thermal Coastline SOIC and 14-lead TSSOP packages. Low-distortion, rail-to-rail output voltage, and highcurrent drive in small packages make the AD8018 ideal for use in low-cost USB, PCMCIA, and PCI Customer Premise Equipment for ADSL, SDSL, VDSL, and proprietary xDSL systems. Both models will operate over the temperature range –40°C to +85°C. 100⍀ 1nF VREF 0.01F 10k⍀ 750⍀ 750⍀ 750⍀ Figure 1. Out-of-Band SFDR vs. ADSL Upstream Line Power; VS = 5 V, N = 4 Turns, 144 kHz to 500 kHz. See Evaluation Board Schematics in Figure 11. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 100⍀ RL = 100⍀ LINEPOWER 13dBm R2 3.1⍀ 18 0.01F R1 3.1⍀ POUT 16dBm 10k⍀ 16 11 –IN2 –VS 5 10⍀ –80 14 ⴙIN1 4 The AD8018 is intended for use in single-supply (5 V) xDSL modems where high-output current and low distortion are essential to achieve maximum reach. The dual high-speed amplifiers are capable of driving low distortion signals to within 0.5 V of the power supply rail. Each amplifier can drive 400 mA of current into 10 Ω (differential) while maintaining –82 dBc out-of-band SFDR. The AD8018 is available with flexible standby and shutdown modes. Two digital logic bits (PWDN1 and PWDN0) may be used to put the AD8018 into one of three modes: full power, standby (outputs low impedance), and shutdown (outputs high impedance). VIN 10 12 PLINE – dBm 10 OUT2 NC = NO CONNECT 10k⍀ 8 9 ⴙVS –IN1 3 PRODUCT DESCRIPTION –70 6 8 NC OUT1 2 NC 7 0.01F VS = 8V AD8018ARU NC 1 5V –60 –90 4 AD8018AR 14-Lead TSSOP 10⍀ 1nF 10k⍀ 1:4 TRANSFORMER Figure 2. Single-Supply Voltage Differential Drive Circuit for xDSL Applications One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD8018–SPECIFICATIONS (@ 25ⴗC, V = 5 V, R = 100 ⍀, R = R = 750 ⍀ unless otherwise noted.) S Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/HARMONIC PERFORMANCE Distortion, Second Harmonic Third Harmonic MTPR (In-Band) SFDR (Out-of-Band) Input Noise Voltage Input Noise Current Crosstalk L F G Conditions Min Typ G = 1, VOUT < 0.4 V p-p, RL = 5 Ω G = 1, VOUT < 0.4 V p-p, RL = 100 Ω G = 2, VOUT < 0.4 V p-p, RL = 5 Ω G = 2, VOUT < 0.4 V p-p, RL = 100 Ω VOUT < 0.4 V p-p, RL = 100 Ω VOUT = 4 V p-p, G = +2 Noninverting, VOUT = 4 V p-p Noninverting, VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p, RL = 100 Ω 40 100 35 80 50 130 40 100 10 80 300 5.5 25 MHz MHz MHz MHz MHz MHz V/s ns ns –89 –61 –86 –74 –94 –63 –89 –77 –70 –82 4.5 1 10 –74 dBc dBc dBc dBc dBc dBc nV√Hz pA√Hz pA√Hz dB VOUT = 6 V p-p (Differential) 100 kHz, RL = 10 Ω 500 kHz, RL = 10 Ω 100 kHz, RL = 10 Ω 500 kHz, RL = 10 Ω 25 kHz to 138 kHz, RL = 12.5 Ω, PLINE = +13 dBm 144 kHz to 500 kHz, RL = 12.5 Ω, PLINE = +13 dBm f = 100 kHz f = 100 kHz (+Inputs) f = 100 kHz (–Inputs) f = 1 MHz, G = +2 DC PERFORMANCE Input Offset Voltage 1 TMIN to TMAX Input Offset Voltage Match Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Bias Current (–) VOUT = 2 V p-p, RL = 5 Ω TMIN to TMAX 830 700 +Input –Input +Input 0.1 2000 10 125 1 0.3 TMIN to TMAX Input Bias Current (–) Match 0.1 TMIN to TMAX Input Bias Current (+) 1 TMIN to TMAX Input Bias Current (+) Match CMRR Input CM Voltage Range OUTPUT CHARACTERISTICS Cap Load Output Resistance Output Voltage Swing Linear Output Current Short-Circuit Current POWER SUPPLY Supply Current/Amp STBY Supply Current/Amp SHUTDOWN Supply Current/Amp Operating Range +Power Supply Rejection Ratio –Power Supply Rejection Ratio 0.1 TMIN to TMAX VIN 2 V to 4 V 51 1.2 30% Overshoot Frequency = 100 kHz, PWDN1, PWDN0 = 1 RL = 100 Ω RL = 5 Ω SFDR < –85 dBc, f = 100 kHz, RL = 10 Ω PWDN1 = 1, PWDN0 = 1 TMIN to TMAX PWDN1 = 0, PWDN0 = 1 or PWDN1 = 1, PWDN0 = 0 PWDN1 = 0, PWDN0 = 0 Single Supply ⌬VS = ⫾1 V TMIN to TMAX ⌬VS = ⫾1 V TMIN to TMAX –2– 350 5 15 17 2.6 8 14 5.5 8 1.5 2.5 0.5 1 54 3.8 1000 0.2 0.16 to 4.87 0.5 to 4.5 400 1000 9 4.5 4.5 0.3 3.3 60 56 52 50 Max 66 55 Unit mV mV mV kΩ kΩ M⍀ Ω pF A A A A A A A A dB V pF Ω V V mA mA 10 11.4 5.1 5.1 0.55 8 mA mA mA mA mA V dB dB dB dB REV. 0 AD8018 Parameter Conditions LOGIC INPUTS (PWDN1, 0) Logic “1” Voltage Logic “0” Voltage Logic Input Bias Current Standby Recovery Time Min Typ Max Unit 2.0 V V A ns 0.8 240 500 RL = 10 Ω, G = +2, IS = 90% of Typical Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 650 mW TSSOP Package (RU) . . . . . . . . . . . . . . . . . . . . . . 565 mW Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ± VS Logic Voltage, PWDN0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 1.6 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range RU, R . . . . . . . –65°C to +125°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C The maximum power that can be safely dissipated by the AD8018 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. 2.0 TJ = 150ⴗC MAXIMUM POWER DISSIPATION – Watts NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air: 8-Lead SOIC Package: θJA = 100°C/W. 8-Lead TSSOP Package: θJA = 115°C/W. While the AD8018 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. ORDERING GUIDE Model AD8018AR Temperature Range Package Description –40°C to +85°C 8-Lead Plastic SOIC AD8018AR–REEL –40°C to +85°C 8-Lead SOIC AD8018ARU –40°C to +85°C 14-Lead Plastic TSSOP AD8018ARU–REEL –40°C to +85°C 14-Lead Plastic TSSOP AD8018ARU–EVAL Evaluation Board Package Option SO-8 SO-8 RU-14 1.5 8-LEAD SOIC PACKAGE 1.0 14-LEAD TSSOP PACKAGE 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – ⴗC RU-14 Figure 3. Plot of Maximum Power Dissipation vs. Temperature RU-14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8018 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 80 90 –3– WARNING! ESD SENSITIVE DEVICE AD8018–Typical Performance Characteristics 1000 100 VS = ⴞ2.5V RL = 100⍀ 10FTANT 0.1F VOUT AD8018 0.1F VSIGNAL RLOAD 50⍀ –VS 100 INOISE – pA/ Hz ⴙVS 10 10 10FTANT ⴙINOISE 1 10 TPC 1. Single-Ended Test Circuit 100 1k 10k FREQUENCY – Hz 0.1 1M 100k TPC 4. INOISE and VNOISE vs. Frequency 3k 150 G=2 VS = ⴞ2.5V RL = 5⍀ VS=ⴞ2.5V 2.5k OUTPUT IMPEDANCE – ⍀ 100 OUTPUT VOLTAGE – mV 1 ⴚINOISE VNOISE – nV/ Hz (RTI) VNOISE 750⍀ 750⍀ 50 0 –50 2k (0,0) 1.5k 1k (1,0) –150 (1,1) 500 –100 0 50 100 150 200 250 300 350 400 450 0 0.01 500 0.1 1 10 FREQUENCY – MHz TIME – ns TPC 2. Small Signal Step Response TPC 5. Output Impedance vs. Frequency, for Full Power, Standby, and Shutdown Modes 3 3 G=2 VS = ⴞ2.5V RL = 5⍀ 2 (+0.1%) 2 1 1 mV OUTPUT VOLTAGE – V 1k 100 0 0 VOUT – (VINⴛ2) –1 –1 –2 (–0.1%) –2 –3 0 50 100 150 200 250 300 350 400 450 –3 500 TIME – ns TPC 3. Large Signal Step Response G=2 VS = ⴞ2.5 VIN = 2V p-p RL = 100⍀ 0 10 20 30 40 50 60 TIME – ns 70 80 90 100 TPC 6. 0.1% Settling Time –4– REV. 0 AD8018 5 5 G=2 VS = ⴞ2.5V RL = 100⍀ 2 –4 –7 –10 –13 –16 –4 –7 –10 –13 –16 –19 –19 –22 –22 –25 10k 100k 1M 10M FREQUENCY – Hz 100M G=2 VS = ⴞ2.5 RL = 5⍀ 2 –1 OUTPUT VOLTAGE – dBv OUTPUT VOLTAGE – dBv –1 –25 10k 1G TPC 7. Output Voltage vs. Frequency 100k 1M 10M FREQUENCY – Hz 100M 1G TPC 10. Output Voltage vs. Frequency 2.5 12 750⍀ 750⍀ 2.4 ⴙSWING –SWING 9 VS = ⴞ2.5V 6 NORMALIZED GAIN – dB OUTPUT SWING – Volts 2.3 2.2 2.1 2.0 1.9 1.8 3 –9 –15 100 1000 LOAD RESISTANCE – ⍀ –18 100k 10k FULL POWER –6 1.6 10 G=2 VS = ⴞ2.5V RL = 100⍀ (1,1) –3 –12 1 RL 50⍀ STANDBY (1,0) or (0,1) 0 1.7 1.5 VOUT VIN 1M 10M FREQUENCY – Hz 100M 1G TPC 11. Small Signal Frequency Response TPC 8. Output Swing vs. RLOAD 0 –10 –10 –20 –20 CMRR – dB PSRR – dB –40 –50 ⴚPSRR –60 –40 –50 –70 ⴙPSRR –80 –90 100k 1M 10M FREQUENCY – Hz (1,1) FULL POWER G=2 VS = ⴞ2.5V ⌬VS = ⴞ1V RL = 100⍀ G=2 VS = ⴞ2.5V RL = 100⍀ –60 –70 100k 100M 1M 10M FREQUENCY – Hz 100M 1G TPC 12. CMRR vs. Frequency, Full Power, and Standby Mode TPC 9. PSRR vs. Frequency REV. 0 STANDBY (1,0) or (0,1) –30 –30 –5– AD8018 –60 ⴙVS 10F VS = ⴞ2.5V G=4 fO = 100kHz VOUT = 6V p–p 0.1F 100⍀ 1/2 DIFFERENTIAL DISTORTION – dBc 7.96k⍀ 402⍀ 0.1F 500⍀ VSIGIN 50⍀ AD8018 500⍀ AD8138 500⍀ 0.1F 220F RL AD9632 0.1F 500⍀ 50⍀ OUT 0.1F ⴚ6V 25⍀ ⴙ6V 750⍀ ⴙ6V 750⍀ ⴚ6V AD8018 500⍀ 100⍀ 7.96k⍀ 1/2 –70 –80 2ND HARMONIC –90 3RD HARMONIC –100 402⍀ 10F ⴚVS 0.1F –110 5 100 10 LOAD RESISTANCE – ⍀ TPC 13. Differential Test Circuit TPC 16. Differential Distortion vs. RLOAD –60 VOUT = 6V p–p RL = 10⍀ VS = ⴞ 2.5V PWDN 1,0 = 1,1 –70 DIFFERENTIAL DISTORTION – dBc DIFFERENTIAL DISTORTION – dBc –60 –80 3RD HARMONIC –90 2ND HARMONIC –100 0.1 FREQUENCY – MHz 2ND HARMONIC –90 3RD HARMONIC –100 3 –60 DIFFERENTIAL DISTORTION – dBc VS = ⴞ2.5V RL = 3⍀ G=4 fO = 100kHz PWDN 1,0 = 1,1 4 5 6 OUTPUT VOLTAGE – Volts 7 8 TPC 17. Differential Distortion vs. Peak-to-Peak Output Voltage –50 DIFFERENTIAL DISTORTION – dBc –80 1.0 TPC 14. Differential Distortion vs. Frequency 3RD HARMONIC –70 –80 2ND HARMONIC –90 –100 –110 200 –70 –110 –110 0.01 –60 VS = ⴞ2.5V RL = 10⍀ G=4 fO = 100kHz PWDN 1,0 = 1,1 VS = ⴞ2.5V RL = 10⍀ G=4 fO = 100kHz PWDN 1,0 = 1,0 or 0,1 –70 –80 2ND HARMONIC –90 3RD HARMONIC –100 –110 300 400 500 600 PEAK OUTPUT CURRENT – mA 700 3 800 TPC 15. Differential Distortion vs. Peak Output Current 4 5 6 OUTPUT VOLTAGE – Volts 7 8 TPC 18. Differential Distortion vs. Peak-to-Peak Output Voltage –6– REV. 0 AD8018 16 18 VS = 8.00 15 16 VS = 5.25 VS = 5.00 14 PLINE – dBm PLINE – dBm 14 13 VS = 5.00 VS = 4.75 12 VS = 4.75 VS = 4.50 12 10 11 8 VS = 3.33 3.2 3.4 3.8 4.0 4.2 4.4 3.6 TRANSFORMER TURNS RATIO 4.6 6 3.0 4.8 –20 VS = 5V RLINE = 100⍀ f = 93kHz TRANSIMPEDANCE – ⍀ MTPR – dBc P = 13dBm P = 13.5dBm P = 14dBm P = 12.5dBm P = 12dBm –60 3.6 3.8 4.0 4.2 4.4 TRANSFORMER TURNS RATIO 4.6 4.8 10M 200 1M 150 100k –40 –50 3.4 TPC 22. Line Power vs. Turns Ratio; –75 dBc Out-of-Band SFDR, f = 361 kHz TPC 19. Line Power vs. Turns Ratio; MTPR = –65 dBc, f = 43 kHz –30 3.2 100 PHASE 10k 50 1k 0 100 –50 TRANSIMPEDANCE 10 –100 1 –150 0.1 –200 –70 –80 3 4 TRANSFORMER TURNS RATIO – N 0.01 1k 5 –30 100M 1G 20 VS = 5V RLINE = 100⍀ f = 361kHz –50 LOGIC 1 TO 0 TOTAL SUPPLY CURRENT – mA –40 SFDR – dBc 100k 1M 10M FREQUENCY – Hz TPC 23. Open Loop Transimpedance and Phase TPC 20. MTPR vs. Turns Ratio P = 12.5dBm P = 13dBm P = 13.5dBm P = 14dBm –60 –70 –80 18 DECREASING 16 14 INCREASING 12 10 LOGIC 0 TO 1 8 P = 12dBm –90 3 4 TRANSFORMER TURNS RATIO – N 6 0.86 5 0.88 0.90 0.92 0.94 0.96 0.98 POWER-DOWN VOLTAGE – Volts 1.00 1.02 TPC 24. Power-Up/-Down Threshold Voltage TPC 21. Out-of-Band SFDR vs. Turns Ratio for Various Line Power REV. 0 10k –7– PHASE – Degrees 10 3.0 AD8018 –10 –20 VIN = 2V p-p G=2 VS = ⴞ2.5 CROSSTALK – dB –30 –40 –50 RL = 5⍀ SIDE A DRIVEN RL = 5⍀ SIDE B DRIVEN –60 RL = 100⍀ SIDE B DRIVEN –70 –80 –90 RL = 100⍀ SIDE A DRIVEN –100 –110 100k 1G 100M 1M 10M FREQUENCY – Hz TPC 25. Crosstalk vs. Frequency THEORY OF OPERATION The AD8018 is composed of two current feedback amplifiers capable of delivering 400 mA of output current while swinging to within 0.5 V of either power supply, and maintaining low distortion. A differential line driver using the AD8018 can provide CPE performance on a single 5 V supply. This performance is enabled by Analog Device’s XFCB process and a novel, twostage current feedback architecture featuring a patent-pending rail-to-rail output stage. VO VP A simplified schematic is shown in Figure 4. Emitter followers buffer the positive input, VP, to provide low input current and current noise. The low impedance current feedback summing junction is at the negative input, VN. The output stage is another high-gain amplifier used as an integrator to provide frequency compensation. The complementary common-emitter output provides the extended output swing. A current feedback amplifier’s dynamic and distortion performance is relatively insensitive to its closed-loop signal gain, which is a distinct advantage over a voltage-feedback architecture. Figure 5 shows a simplified model of a current feedback amplifier. The feedback signal is a current into the inverting node. RIN is inversely proportional to the transconductance of the amplifier’s input stage, gmi. Circuit analysis of the pictured follower with gain yields: VOUT /VIN BIAS VN Figure 4. Simplified Schematic G=1 + VO VIN RIN IIN IT = IIN CT RT + – VOUT TZ ( S ) =G× TZ ( S ) + RF + G × RIN – where: RF G = 1 + RF /RG RT TZ ( S ) = 1 + SCT (RT ) RIN = 1/ g mi ≅ 125 Ω RG Figure 5. Model of Current Feedback Amplifier FEEDBACK RESISTOR SELECTION Recognizing that G ⫻ RIN < RF, and that the –3 dB point is set when TZ(S) = RF, one can see that the amplifier’s bandwidth depends primarily on the feedback resistor. There is a value of RF below which the amplifier will be unstable, as an actual amplifier will have additional poles that will contribute excess phase shift. The optimum value for RF depends on the gain and the amount of peaking tolerable in the application. In current feedback amplifiers, selection of the feedback and gain resistors will impact on the MTPR performance, bandwidth, noise, and gain flatness. Care should be exercised in the selection of these resistors so that the optimum performance is achieved. Table I shows the recommended resistor values for use in a variety of gain settings for the test circuit in TPC 1. These values are intended to be a starting point when designing for any application. –8– REV. 0 AD8018 Table I. Resistor Selection Guide ERR Gain RF (⍀) RG (⍀) –1 +1 +2 +3 +4 +5 681 1k 750 511 340 230 681 ∞ 750 256 113 59 ADP3331 OUT IN VIN C1 0.47F FB GND SD EOUT R3 330k⍀ R1 953k⍀ VOUT C2 0.47F R2 301k⍀ ON OFF Figure 6. ADP3331 LDO POWER-DOWN FEATURES Two digitally programmable logic pins, PWDN1 and PWDN0, are available on the TSSOP-14 package to select among three different modes of operation, full power, standby and shutdown. The DGND pin is the logic ground reference. The logic threshold voltage is established 1 V above DGND. In a typical 5 V single-supply application, the DGND pin is connected to analog ground. If PWDN1, PWDN0, and DGND are left unconnected, the AD8018 will operate at full power. Table II. Power-Down Features and Truth Table PWDN0 PWDN1 State Supply Current Output Impedance High Low High Low High High Low Low Full Power Standby Standby Disabled 18 mA 9 mA 9 mA 300 µA Low Low Low High METHOD FOR GENERATING A MIDSUPPLY VOLTAGE To operate an amplifier on a single voltage supply, a voltage midway between the supply and ground must be generated to properly bias the inputs and the outputs. A voltage divider can be created with two equal value resistors (Figure 7). There is a trade-off between the power consumed by the divider and the voltage drop across these resistors due to the positive input bias currents. Selecting 2.5 kΩ for R1 and R2 will create a voltage divider that draws only 1 mA from a 5 V supply. The voltage generated with this topology can vary due to the temperature coefficient (TC) of resistance. Resistors that are closely matched and have a low TC will minimize variations in the voltage reference due to temperature. One should also be sure to use a decoupling capacitor (0.1 µF) at the node where VREF is generated. 5V R1 2.5k⍀ POWER SUPPLY AND DECOUPLING The AD8018 can be powered with a good quality (i.e., low-noise) supply anywhere in the range from 3.3 V to 8 V. However, in order to optimize the ADSL upstream drive capability to +13 dBm and maintain the best Spurious Free Dynamic Range (SFDR), the AD8018 circuit should be supplied with a well regulated 5 V supply. The 5 V supplied at the USB port may be poorly regulated. Improving the quality of the 5 V supply will optimize the performance of the AD8018 in a USB-supplied CPE ADSL modem. This can be accomplished through the use of a step-up dc-to-dc converter or switching power supply followed by a low dropout (LDO) regulator such as the ADP3331 (see Figure 6). Setting R1 to be 953 kΩ and R2 to be 301 kΩ will result in a V OUT of 5 V. Careful attention must be paid to decoupling the power supply pins at the output of the dc-to-dc converter, the output of the LDO regulator and the supply pins of the AD8018. High-quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCCs) should be used to minimize supply voltage ripple and power dissipation. A large, usually tantalum, 10 µF to 47 µF capacitor located in proximity to the AD8018 is required to provide good decoupling for lower frequency signals. In addition, 0.1 µF MLCC decoupling capacitors should be located as close to each of the power supply pins as is physically possible, no more than 1/8 inch away. An additional large (4.7 µF to 10 µF) tantalum capacitor should be placed on the board near the supply terminals to supply current for fast, largesignal changes at the AD8018 outputs. REV. 0 R2 2.5k⍀ VREF 0.1F Figure 7. Midsupply Reference DIFFERENTIAL TESTING The test circuit shown in TPC 13 is used for measuring the differential distortion of the AD8018. A single-ended test signal is applied to the inverting input of the AD8138 differential driver with the noninverting input grounded. Applying the differential output of the AD8138 through 100 Ω resistors serves to isolate the inputs of the AD8018 differential driver and provide a wellbalanced low-distortion input signal. The differential load (RL) of the AD8018 can be set to the equivalent of the line impedance reflected through a transformer. The AD9632 converts the differential output voltage back to a single-ended signal. The differential-to- single-ended converter using the AD9632 has an attenuation of –26 dB and is wired with precision resistors to optimize the balance of differential input signal. The resulting smaller output signal can be easily measured using a 50 Ω spectrum analyzer. –9– AD8018 This circuit requires significant power supply bypassing. The AD8018 operates on a split supply in this circuit. The bypassing technique shown in TPC 13 utilizes a 220 µF tantalum capacitor and a 0.1 µF ceramic chip capacitor in parallel, connected from the positive to negative supply, and a 10 µF tantalum and 0.1 µF ceramic chip capacitor in parallel, connected from each supply to ground. The capacitors connected between the power supplies serve to minimize any voltage ripples that might appear at the supplies while sourcing or sinking any large differential current. The large capacitor has a pool of charge instantly available for the AD8018 to draw from, thus preventing any erroneous distortion results. POWER DISSIPATION It is important to consider the total power dissipation of the AD8018 in order to properly size the heat sink area of an application. Figure 8 is a simple representation of a differential driver. With some simplifying assumptions we can estimate the total power dissipated in this circuit. If the output current is large compared to the quiescent current, computing the dissipation in the output devices and adding it to the quiescent power dissipation will give a close approximation of the total power dissipation in the package. A factor α (~0.6-1) corrects for the slight error due to the Class A/B operation of the output stage. It can be estimated by subtracting the quiescent current in the output stage from the total quiescent current and ratioing that to the total quiescent current. For the AD8018, α = 0.833. +VS PTOT = 4 (0.8 VO rmsVS – VO rms2 ) × For the AD8018, operating on a single 5 V supply and delivering a total of 16 dBm (13 dBm to the line and 3 dBm to the matching network) into 12.5 Ω (100 Ω reflected back through a 1:4.0 transformer plus back termination), the power is: = 261 mW + 40 mW = 301 mW Using these calculations, and a θJA of 115°C/W for the TSSOP package and 100°C/W for the SOIC, Tables III and IV show junction temperature versus power delivered to the line for several supply voltages. Table III. Junction Temperature vs. Line Power and Operating Voltage for TSSOP, T AMB = 85ⴗC VSUPPLY PLINE 5 6 7 8 13 14 15 16 17 18 115 117 119 121 123 125 122 125 127 130 133 136 129 132 136 139 143 147 136 140 144 148 153 158 +VS +VO Table IV. Junction Temperature vs. Line Power and Operating Voltage for SOIC, T AMB = 85ⴗC –VO RL –VS –VS Figure 8. Simplified Differential Driver Remembering that each output device dissipates for only half the time gives a simple integral that computes the power for each device: 1 2 ∫ (V S – VO ) × 1 + 2 α IQ VS + POUT RL PLINE, dBm 5 VSUPPLY 6 7 8 13 14 15 16 17 18 111 113 115 116 118 120 117 119 122 124 127 130 123 126 129 132 136 139 129 133 136 140 144 149 Running the AD8018 at voltages near 8 V can produce junction temperatures that exceed the thermal rating of the TSSOP packages and should be avoided. The shaded areas indicate junction temperatures greater than 150°C. 2VO RL LAYOUT CONSIDERATIONS The total supply power can then be computed as: 2 1 + 2 α IQ VS + POUT PTOT = 4 VS ∫|VO | − ∫VO × RL In this differential driver, VO is the voltage at the output of one amplifier, so 2 VO is the voltage across RL, which is the total impedance seen by the differential driver, including back termination. Now, with two observations, the integrals are easily evaluated. First, the integral of VO2 is simply the square of the rms value of VO. Second, the integral of |VO| is equal to the average rectified value of VO, sometimes called the Mean Average Deviation, or MAD. It can be shown that for a DMT signal, the MAD value is equal to 0.8 times the rms value. As is the case with all high-speed applications, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. Removing the ground plane on all layers from the area near the input and output pins will reduce stray capacitance, particularly in the area of the inverting inputs. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. –10– REV. 0 AD8018 Following these generic guidelines will improve the performance of the AD8018 in all applications. Stability Enhancements The CPE bridge hybrid circuit presents a complex impedance to the drive amplifiers, particularly when transformer parasitics are factored in. To ensure stable operation under the full range of load conditions, a series R-C network (Zoebel Network) should be connected between each amplifier’s output and ground. The recommended values are 10 Ω for the resistor and 1 nF for the capacitor to create a low impedance path to ground at frequencies above 16 MHz (see Figure 2). R33 and R34 are added to improve common-mode stability. To optimize the AD8018’s performance as an ADSL differential line driver, locate the transformer hybrid near the AD8018 drivers and as close to the RJ11 jack as possible. Maintain differential circuit symmetry into the differential driver and from the output of the drivers through the transformer-coupled output of the bridge circuit as much as possible. CPE ADSL Application The low-cost, high-output current dual AD8018 xDSL driver amplifiers have been specifically designed to drive high fidelity xDSL signals to within 0.5 V of the power rails, the performance needed to provide CPE ADSL on a single 5 V supply. The AD8018 may be used in transformer-coupled bridge hybrid circuits to drive modulated signals including Discrete MultiTone (DMT) upstream to the central office. Receive Channel Considerations A transformer used at the output of the differential line driver to step up the differential output voltage to the line has the inverse effect on signals received from the line. A voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid. The turns ratio of the transformer may also be dictated by the ability of the receive circuitry to resolve low-level signals in the noisy twisted pair telephone plant. Higher turns ratio transformers effectively reduce the received signal-to-noise ratio due to the reduction in the received signal strength. Evaluation Board The AD8018ARU-EVAL evaluation board circuit in Figure 12 offers the ability to evaluate the AD8018 in a typical xDSL bridge hybrid circuit. The receiver circuit on these boards is typically unpopulated. Requesting samples of the AD8022AR with the AD8018ARUEVAL board will provide the capability to evaluate the AD8018ARU along with other Analog Devices products in a typical transceiver circuit. The evaluation circuits have been designed to replicate the CPE side analog transceiver hybrid circuits. The AD8022, a dual amplifier with typical RTI voltage noise of only 2.5 nV/√Hz and a low supply current of 4 mA/amplifier, is recommended for the receive channel. DMT Modulation, MultiTone Power Ratio (MTPR), and Out-of-Band SFDR ADSL systems rely on DMT modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. A uniquely encoded, Quadrature Amplitude Modulation (QAM)-like signal occurs at the center frequency of each subband or tone. See Figure 9 for an example of a DMT waveform in the frequency domain, and Figure 10 for a time domain waveform. Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. The circuit mentioned above is designed using a one-transformer transceiver topology including a line receiver, line driver, line matching network, an RJ11 jack for interfacing to line simulators, and transformer-coupled inputs for single-ended-to-differential input conversion. AC-coupling capacitors of 0.01 µF, C8, and C10, in combination with 10 kΩ resistors R24 and R25, will form a zero frequency at 1.6 kHz. Transformer Selection Customer premise ADSL requires the transmission of a +13 dBm (20 mW) DMT signal. The DMT signal can have a crest factor as high as 5.3, requiring the line driver to provide peak line power of 27.5 dBm (560 mW). 27.5 dBm peak line power translates into a 7.5 V peak voltage on the 100 Ω telephone line. Assuming that the maximum low-distortion output swing available from the AD8018 line driver on a 5 V supply is 4 V and, taking into account the power lost due to the termination resistance, a step-up transformer with turns ratio of 4.0 or greater is needed. In the simplified differential drive circuit shown in Figure 2, the AD8018 is coupled to the phone line through a step-up transformer with a 1:4 turns ratio. R1 and R2 are back-termination or line-matching resistors, each 3.1 Ω (100 Ω/(2 × 42)), where 100 Ω is the approximate phone line impedance. The total differential load for the AD8018, including the termination resistors, is 12.5 Ω. Even under these conditions the AD8018 provides low distortion signals to within 0.5 V of the power rails. REV. 0 Conventional methods of expressing the output signal integrity of line drivers, such as single-tone harmonic distortion or THD, two-tone InterModulation Distortion (IMD), and third order intercept (IP3), become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms. A typical ADSL upstream DMT signal can contain as many as 27 carriers (subbands or tones) of QAM signals. MultiTone Power Ratio (MTPR) is the relative difference between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal), yielding an empty frequency bin. MTPR, sometimes referred to as the “empty bin test,” is typically expressed in dBc, similar to expressing the relative difference between single-tone fundamentals and second or third harmonic distortion components. Measurements of MTPR are typically made on the line side or secondary side of the transformer. –11– AD8018 4 20 3 0 –20 VOLTS POWER – dBm 2 –40 1 0 –1 –60 –2 –3 –0.25 –80 0 50 100 FREQUENCY – kHz 150 Figure 9. DMT Waveform in the Frequency Domain –0.2 –1.5 –1.0 –0.05 0 TIME – ms 0.05 1.0 1.5 0.2 Figure 10. DMT Signal in the Time Domain MTPR versus transformer turns ratio is depicted in TPC 21 and covers a variety of line power ranging from +12 dBm to +14 dBm. As the turns ratio increases, the driver hybrid can deliver more undistorted power due to higher output current capability. Significant degradation of MTPR will occur if the output of the driver swings to the rails, causing clipping at the DMT voltage peaks. Driving DMT signals to such extremes not only compromises “in-band” MTPR, but will also produce spurs that exist outside of the frequency spectrum containing the desired DMT power. “Out-of-band” spurious free dynamic range (SFDR) can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins. Compromising out-of-band SFDR is equivalent to increasing near end crosstalk (NEXT). Regardless of terminology, maintaining out-of-band SFDR while reducing NEXT will improve the overall performance of the modems connected at either end of the twisted pair. TPC 21 shows how SFDR varies versus transformer turns ratio for line power ranging from +12 dBm to +14 dBm. As line power increases, or turns ratio decreases, SFDR degrades. The power contained in the spurs can be measured relative to the power contained in a typical upstream carrier and is expressed in dBc as SFDR, similar to MTPR. Generating DMT Signals At this time, DMT-modulated waveforms are not typically menu-selectable items contained within AWGs. Even using AWG software to generate DMT signals, AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D/A converters and output drivers used by AWG manufacturers. Similar to evaluating single-tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with Option 4, (12-/24-bit, TTL Digital Data Out), digitally coupled to Analog Devices’ AD9754, a 14-bit TxDAC®, buffered by an AD8002 amplifier configured as a differential driver. Note that the DMT waveforms (available on the Analog Devices website, http://www.analog.com), or similar .WFM files are needed to produce the digital data required to drive the TxDAC from the optional TTL Digital Data output of the TEK AWG2021. The supply voltage of the driver can also affect SFDR. As the supply voltage is increased, voltage swing is increased as well, resulting in the ability to deliver more power to the line without sacrificing performance. This can be seen in TPC 22. Less undistorted power is available when lower turns ratio transformers are used due to voltage clipping of the signal. TxDAC is a trademark of Analog Devices, Inc. –12– REV. 0 AD8018 TP10 R30 0⍀ VCC-T 55 C8 0.1F VCC R8 100⍀ AD8018 R24 10k⍀ 2 JP4 A 1 P4 2 P4 3 B A CAPPOLY R18 750⍀ R33 10k⍀ R19 750⍀ R34 10k⍀ 10⍀ 2 1WATT 10 CAPPOLY C6 DNI C27 1000pF 1 R4 10⍀ U1 R14 100⍀ VCC-T TP4 C1 DNI AD8022 53 R17 2.49k⍀ C20 0.1F P3 3 P3 2 P3 R6 DNI VCC R5 DNI R7 DNI AD8022 DNI C16 DNI C3 DNI TP5 Figure 11. EVAL Board Schematic VCC R28 DNI 100⍀ R26 PDN0 JP2 U1 AD8018 100⍀ R25 JP1 0.1F C24 C23 DNI C19 DNI 25V U2 DECOUPLING R13 DNI R27 DNI C17 10F 25V VCC-R VCC;8 AGND;4 DNI: DO NOT INSTALL C15 0.01F TB1 2 U2 54 VCC-T C26 0.1F C18 DNI R10 DNI VCC-R TP18 TP19 TB1 1 C14 10F 2 1 L5 BEAD C2 DNI R9 DNI TP17 2 TP23 TP24 TP25 TP26 VCC-R AGND;4 DNI VCC TP9 R12 DNI U2 VCC 6 7 8 TP8 R31 0⍀ TP11 5 TP2 R21 DNI +V 56 4 C12 DNI 1 C10 0.1F 2 3 PR2 JP3 AD8018 R32 DNI 8 3 C7 DNI 1 R1 R29 10k⍀ VCC 0.1F C25 PDN1 DGND NC1 NC2 NC3 Figure 12. Input Control Circuit REV. 0 9 TP1 3 2 R15 50⍀ R16 2.49k⍀ C22 1000pF C9 DNI 7 CAPPOLY 2 1 R2 750⍀ C5 0.1F T1 NC = 5,6 4 CAPPOLY R3 10⍀ 2 C28 DNI C4 DNI R20 DNI VCC B 1 TP7 PR1 C11 DNI U1 R11 50⍀ 3 P4 TP6 +V –13– AD8018 Figure 13. Assembly—Primary Side Figure 14. Silk Screen—Primary Side –14– REV. 0 AD8018 Figure 15. Layer 1—Primary Side Figure 16. Layer 2—Ground Plane REV. 0 –15– AD8018 Figure 17. Layer 3—Power Plane Figure 18. Layer 4—Secondary Side –16– REV. 0 AD8018 Figure 19. Assembly—Secondary Side REV. 0 –17– AD8018 EVALUATION BOARD—BILL OF MATERIALS Qty. Description Vendor Ref Desc. 2 2 5 2 4 3 1 1 6 2 2 5 2 3 2 2 4 2 3 4 1 2 2 1 1 4 2 4 1 2 2 1 1 4 4 1,000 pF 50 V. 1206 ceramic chip capacitor 0.01 µF 50 V. 1206 ceramic chip capacitor 0.1 µF 50 V. 1206 size ceramic chip capacitor 1.0 µF 16 V. 1206 size ceramic chip capacitor # 26 red (solid) wire jumper 10 µF 16 V. ‘C’ size Tantalum chip capacitor Ferrite bead (with # 22 wire) 10 Ω 5% 3.0 W. metal oxide power resistor 0 Ω 5% 1/8 W. 1206 size chip resistor 10.0 Ω 1% 1/8 W. 1206 size chip resistor 49.9 Ω 1% 1/8 W. 1206 size chip resistor 100 Ω 1% 1/8 W. 1206 size chip resistor 2.49 kΩ 1% 1/8 W. 1206 size chip resistor 750 Ω 1% 1/8 W. 1206 size chip resistor 10.0 kΩ 0.1% 0805 size chip resistor 10.0 kΩ 1% 1/8 W. 1206 size chip resistor Test Point (Black) [GND] Test Point (Brown) Test Point (Red) Test Point (Orange) Test Point (Yellow) Test Point (Blue) Test Point (Green) 2 × 5-pin strips (1/4 of a 20-pin Samtek ‘SIP’ strip socket) 2 Pos. GRAY term. blk. # 25.161.0253 (Newark # 51F4106) 0.1 inch ctr. shunt Berg # 65474 -001 2 pin gold male header 0.1 inch ctr. Berg # 69157 -102 50 Ω BNC pc mount Telegartner # J01001A1944 AMP# 555154 -1 MOD. JACK (SHIELDED) 6 –6 3-pin gold male header Waldom D-K # WM 2723 -ND 3-pin gold male locking header Waldom # WM 2701 -ND AD8018ARU ADSL Driver hybrid AD8018 TSSOP1T Non-Inverting REV. A Evaluation PC board # 4 –40 × 1/4" panhead ss machine screw # 4 –40 × 1/2" threaded alum. standoffs ADS # 4-5-20 ADS # 4-5-19 ADS # 4-5-18 Newark # 83F6841 ADS # 10-14-3 ADS # 4-7-6 ADS # 48-1-1 D-K # P10W-3BK-ND ADS # 3-18-88 ADS # 3-18-120 ADS # 3-14-26 ADS # 3-18-40 ADS # 3-18-71 ADS # 3-18-8 ADS # 3-36-5 ADS # 3-18-119 ADS # 12-18-44 ADS # 12-18-59 ADS # 12-18-43 ADS # 12-18-60 ADS # 12-18-32 ADS # 12-18-62 ADS # 12-18-61 ADS # 11-2-14 ADS# 12-19-10 ADS # 11-2-38 ADS # 11-2-37 ADS # 12-6-22 ADS # 12-20-5 ADS # 12-3-80 ADS # 12-3-79 ADS # AD8018ARU DCS ADS # 30-1-1 ADS # 30-16-2 C22, 27 C15, 23 C5, 20, 24 -26 C8, 10 C4, 6, 7, 9 C14, 17, 19 L5 R1 C11, 12, R20, 21, 30, 31 R3, 4 R11, 15 R 8, 14, 25, 26, 32 R16, 17 R2, 18, 19 R33, 34 R24 and 29 TP23–26 (GND.) TP4, 5 TP17–19 TP1, 2, 10, 11 TP3 TP6, 8 TP7, 9 (T1) TB1, 2 JP1–4 JP1, 2 S3–6 P1 JP3, 4 P3, 4 U1 (D.U.T.) Eval. PC Board –18– REV. 0 AD8018 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14 Lead TSSOP (RU-14) 0.201 (5.10) 0.197 (5.00) 0.193 (4.90) 0.1968 (5.00) 0.1890 (4.80) 8 0.1574 (4.00) 0.1497 (3.80) 5 1 0.2440 (6.20) 0.2284 (5.80) 14 0.0196 (0.50) ⴛ 45ⴗ 0.0099 (0.25) 0.0500 (1.27) BSC 0.020 (0.51) 0.013 (0.33) 8ⴗ 0.0098 (0.25) 0ⴗ 0.0075 (0.19) 0.252 (6.40) BSC 1 0.0688 (1.75) 0.0532 (1.35) SEATING PLANE 8 0.177 (4.50) 0.173 (4.40) 0.169 (4.30) PIN 1 0.0098 (0.25) 0.0040 (0.10) C01519–4.5–7/00 (rev. 0) 8 Lead SOIC (SO-8) 7 PIN 1 0.050 (1.27) 0.016 (0.40) CONTROLLING DIMENSIONS ARE IN MILLIMETERS ALL DIMENSIONS PER JEDEC STANDARDS MS-012 AA 0.059 (1.50) 0.093 (1.00) 0.031 (0.80) 0.0256 (0.65) BSC 0.006 (0.15) 0.002 (0.05) 0.047 (1.2) MAX 8ⴗ 0ⴗ 0.0118 (0.30) SEATING 0.008 (0.20) 0.0075 (0.19) PLANE 0.004 (0.09) 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) PRINTED IN U.S.A. CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV. 0 –19–