AD ADSP-BF533SKBCE10B

Blackfin®
Embedded Processor
ADSP-BF533(M)
a
Preliminary Technical Data
FEATURES
External memory controller with glueless support for
SDRAM, SRAM, FLASH, and ROM
Flexible memory booting options from SPI and external
memory
Up to 627 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
1.39 V to 1.45 V core VDD
3.3 V and 2.5 V tolerant I/O
160-ball mini-BGA package
PERIPHERALS
Parallel peripheral interface (PPI)/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels
12-channel DMA controller
SPI-compatible port
Three timer/counters with PWM support
UART with support for IrDA®
Event handler
Real-time clock
Watchdog timer
Debug/JTAG interface
On-chip PLL capable of 1x to 63x frequency multiplication
Core timer
MEMORY
Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
64K bytes of instruction SRAM
32K bytes of data SRAM/Cache
32K bytes of data SRAM
4K bytes of scratchpad SRAM
Two dual-channel memory DMA controllers
Memory management unit providing memory protection
JTAG TEST AND
EMULATION
VOLTAGE
REGULATOR
EVENT
CONTROLLER/
CORE TIMER
WATCHDOG TIMER
B
L1
INSTRUCTION
MEMORY
MMU
REAL-TIME CLOCK
UART PORT
IRDA®
L1
DATA
MEMORY
TIMER0, TIMER1,
TIMER2
CORE/SYSTEM BUS INTERFACE
PPI / GPIO
DMA
CONTROLLER
SERIAL PORTS (2)
SPI PORT
BOOT ROM
EXTERNAL PORT
FLASH, SDRAM
CONTROL
Figure 1. Functional Block Diagram
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Rev. PrA
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© 2004 Analog Devices, Inc. All rights reserved.
ADSP-BF533(M)
Preliminary Technical Data
TABLE OF CONTENTS
General Description ................................................. 3
ESD Sensitivity ................................................... 19
Portable Low Power Architecture ............................. 3
Timing Specifications ........................................... 20
System Integration ................................................ 3
Clock and Reset Timing ..................................... 21
ADSP-BF533(M) Processor Peripherals ...................... 3
Asynchronous Memory Read Cycle Timing ............ 22
Blackfin Processor Core .......................................... 3
Asynchronous Memory Write Cycle Timing ........... 23
Memory Architecture ............................................ 4
SDRAM Interface Timing .................................. 24
DMA Controllers .................................................. 7
External Port Bus Request and Grant Cycle Timing .. 25
Real-Time Clock ................................................... 8
Parallel Peripheral Interface Timing ...................... 26
Watchdog Timer .................................................. 8
Serial Ports ..................................................... 27
Timers ............................................................... 8
Serial Peripheral Interface (SPI) Port
—Master Timing ........................................... 31
Serial Ports (SPORTs) ............................................ 8
Serial Peripheral Interface (SPI) Port ......................... 9
UART Port .......................................................... 9
Serial Peripheral Interface (SPI) Port
—Slave Timing ............................................. 32
Programmable Flags (PFx) ...................................... 9
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing ...... 33
Parallel Peripheral Interface ................................... 10
Programmable Flags Cycle Timing ....................... 34
Dynamic Power Management ................................ 10
Timer Cycle Timing .......................................... 35
Clock Signals ..................................................... 11
JTAG Test and Emulation Port Timing .................. 36
Booting Modes ................................................... 12
Output Drive Currents ......................................... 37
Instruction Set Description ................................... 12
Power Dissipation ............................................... 39
Development Tools ............................................. 13
Test Conditions .................................................. 40
Designing an Emulator-Compatible Processor Board .. 14
Environmental Conditions .................................... 43
Pin Descriptions .................................................... 15
160-Lead BGA Pinout ............................................. 44
Specifications ........................................................ 18
Outline Dimensions ................................................ 47
Recommended Operating Conditions ...................... 18
Ordering Guide ..................................................... 47
Electrical Characteristics ....................................... 18
Absolute Maximum Ratings .................................. 19
REVISION HISTORY
11/04—Revision PrA: Initial Version
Rev. PrA |
Page 2 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
GENERAL DESCRIPTION
The ADSP-BF533(M) processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction set architecture.
The ADSP-BF533(M) processors are completely code and pin
compatible, differing only with respect to their performance and
on-chip memory. Specific performance and memory configurations are shown in Table 1.
Table 1. Processor Comparison
Maximum
Performance
Instruction
SRAM/Cache
Instruction
SRAM
Data
SRAM/Cache
Data SRAM
Scratchpad
ADSP-BF533
627 MHz
1254 MMACs
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
Dynamic Power Management, the ability to vary both the voltage and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF533(M) processors are highly integrated systemon-a-chip solutions for the next generation of digital communication and consumer multimedia applications. By combining
industry-standard interfaces with a high performance signal
processing core, users can develop cost-effective solutions
quickly without the need for costly external components. The
system peripherals include a UART port, an SPI port, two serial
ports (SPORTs), four general-purpose timers (three with PWM
capability), a real-time clock, a watchdog timer, and a parallel
peripheral interface.
Rev. PrA |
ADSP-BF533(M) PROCESSOR PERIPHERALS
The ADSP-BF533(M) processor contains a rich set of peripherals connected to the core via several high bandwidth buses,
providing flexibility in system configuration as well as excellent
overall system performance (see the functional block diagram in
Figure 1 on Page 1). The general-purpose peripherals include
functions such as UART, timers with PWM (pulse width modulation) and pulse measurement capability, general-purpose flag
I/O pins, a real-time clock, and a watchdog timer. This set of
functions satisfies a wide variety of typical system support needs
and is augmented by the system expansion capabilities of the
part. In addition to these general-purpose peripherals, the
ADSP-BF533(M) processor contains high speed serial and parallel ports for interfacing to a variety of audio, video, and
modem codec functions; an interrupt controller for flexible
management of interrupts from the on-chip peripherals or
external sources; and power management control functions to
tailor the performance and power characteristics of the processor and system to many application scenarios.
All of the peripherals, except for general-purpose I/O, real-time
clock, and timers, are supported by a flexible DMA structure.
There is also a separate memory DMA channel dedicated to
data transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
The ADSP-BF533(M) processor includes an on-chip voltage
regulator in support of the ADSP-BF533(M) processor
Dynamic Power Management capability. The voltage regulator
provides a range of core voltage levels from a single 2.25 V to
3.6 V input. The voltage regulator can be bypassed at the user’s
discretion.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives,
Page 3 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
saturation and rounding, and sign/exponent detection. The set
of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
MEMORY ARCHITECTURE
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
Rev. PrA |
The ADSP-BF533(M) processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency on-chip memory as cache
or SRAM, and larger, lower cost and performance off-chip
memory systems. See Figure 3 on Page 5.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of physical
memory.
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or
data between the internal memory and the external memory
spaces.
Internal (On-Chip) Memory
The ADSP-BF533(M) processor has three blocks of on-chip
memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of 80K bytes
SRAM, of which 16K bytes can be configured as a four way setassociative cache. This memory is accessed at full processor
speed.
The second on-chip memory block is the L1 data memory, consisting of two banks of 32K bytes each. Each memory bank is
configurable, offering both cache and SRAM functionality. This
memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
The external bus interface can be used with both asynchronous
devices such as SRAM, FLASH, EEPROM, ROM, and I/O
devices, and synchronous devices such as SDRAMs. The bus
width is always 16 bits. A1 is the least significant address of a 16bit word. 8-bit peripherals should be addressed as if they were
16-bit devices, where only the lower 8 bits of data should be
used.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
Page 4 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
ADDRE SS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG0
DAG 1
S EQUENCER
ALIG N
DECO DE
LD0 32 BITS
LD1 32 BITS
SD 32 BI TS
R7
R6
R5
R7. H
R6. H
R5. H
R7. L
R6. L
R5. L
R4
R3
R4. H
R3. H
R4. L
R3. L
R2
R1
R2. H
R1. H
R2. L
R1. L
R0
R0. H
R0. L
LOO P BUF FE R
16
16
8
8
BARREL
SHIFTER
8
40
8
CONTRO L
UNIT
40
A0
A1
DATA ARITHME TIC UNI T
Figure 2. Blackfin Processor Core
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully populated with 1M byte of memory.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTE)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
INTERNAL MEMORY MAP
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
0xFF80 0000
RESERVED
0xEF00 0000
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
Booting
The ADSP-BF533(M) processor contains a small boot kernel,
which configures the appropriate peripheral for booting. If the
ADSP-BF533(M) processor is configured to boot from boot
ROM memory space, the processor starts executing from the
on-chip boot ROM. For more information, see Booting Modes
on Page 12.
0x0000 0000
Figure 3. ADSP-BF533 Internal/External Memory Map
Rev. PrA |
Page 5 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
Event Handling
Table 2. Core Event Controller (CEC)
The event controller on the ADSP-BF533(M) processor handles
all asynchronous and synchronous events to the processor. The
ADSP-BF533(M) processor provides event handling that supports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller
provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF533(M) processor event controller consists of two
stages, the core event controller (CEC) and the system interrupt
controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system
events. Conceptually, interrupts from the peripherals enter into
the SIC, and are then routed directly into the general-purpose
interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF533(M) processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF533(M) processor provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 3 describes the inputs
into the SIC and the default mappings into the CEC.
Rev. PrA |
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
EVT Entry
Emulation/Test Control
Reset
Non-Maskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
PLL Wakeup
DMA Error
PPI Error
SPORT 0 Error
SPORT 1 Error
SPI Error
UART Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 RX)
DMA Channel 2 (SPORT 0 TX)
DMA Channel 3 (SPORT 1 RX)
DMA Channel 4 (SPORT 1 TX)
DMA Channel 5 (SPI)
DMA Channel 6 (UART RX)
DMA Channel 7 (UART TX)
Timer 0
Timer 1
Timer 2
PF Interrupt A
PF Interrupt B
DMA Channels 8 and 9
(Memory DMA Stream 1)
DMA Channels 10 and 11
(Memory DMA Stream 0)
Software Watchdog Timer
Page 6 of 48 | November 2004
Default Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
IVG13
IVG13
Preliminary Technical Data
ADSP-BF533(M)
Event Control
The ADSP-BF533(M) processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 6.
• SIC interrupt mask register (SIC_IMASK) – This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servicing the event.
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.
• SIC interrupt wakeup enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 10.)
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
Rev. PrA |
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF533(M) processor has multiple, independent
DMA controllers that support automated data transfers with
minimal overhead for the processor core. DMA transfers can
occur between the ADSP-BF533(M) processor’s internal memories and any of its DMA-capable peripherals. Additionally,
DMA transfers can be accomplished between any of the DMAcapable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and
the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
The ADSP-BF533(M) processor DMA controller supports both
1-dimensional (1D) and 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from registers
or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Examples of DMA types supported by the ADSP-BF533(M)
processor DMA controller include:
• A single, linear buffer that stops upon completion
• A circular, autorefreshing buffer that interrupts on each
full or fractionally full buffer
• 1D or 2D DMA using a linked list of descriptors
• 2D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF533(M) processor system.
This enables transfers of blocks of data between any of the
memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer
mechanism.
Page 7 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
REAL-TIME CLOCK
The ADSP-BF533(M) processor real-time clock (RTC) provides
a robust set of digital watch features, including current time,
stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF533(M) processor. The RTC
peripheral has dedicated power supply pins so that it can remain
powered up and clocked even when the rest of the processor is
in a low power state. The RTC provides several programmable
interrupt options, including interrupt per second, minute, hour,
or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a 24
hour counter, and a 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered-down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
RTXI
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF533(M) processor peripherals. After a reset, software can determine if the watchdog was
the source of the hardware reset by interrogating a status bit in
the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF533(M) processor. Three timers have an external
pin that can be configured either as a Pulse Width Modulator
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulsewidths and periods of external
events. These timers can be synchronized to an external clock
input to the PF1 pin, an external clock input to the PPI_CLK
pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
autobaud detect function for a serial channel.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
RTXO
R1
SERIAL PORTS (SPORTS)
X1
C1
the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remaining in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
The ADSP-BF533(M) processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the following features:
C2
SUGGESTED COMPONENTS:
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C1 = 22 PF
C2 = 22 PF
R1 = 10 M OHM
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
Figure 4. External Components for RTC
WATCHDOG TIMER
The ADSP-BF533(M) processor includes a 32-bit timer that can
be used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset,
nonmaskable interrupt (NMI), or general-purpose interrupt, if
Rev. PrA |
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
Page 8 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF533(M) processor has an SPI-compatible port
that enables the processor to communicate with multiple SPIcompatible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSI, and master input-slave
output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI port
provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.
The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
UART PORT
The ADSP-BF533(M) processor provides a full-duplex universal asynchronous receiver/transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART port includes support for 5 to
8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = ----------------------------------------------16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFX)
f SCLK
SPI Clock Rate = -------------------------------2 × SPI_Baud
The ADSP-BF533(M) processor has 16 bidirectional, generalpurpose programmable flag (PF15–0) pins. Each programmable
flag can be individually controlled by manipulation of the flag
control, status and interrupt registers:
Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
Rev. PrA |
• Flag direction control register – Specifies the direction of
each individual PFx pin as input or output.
• Flag control and status registers – The ADSP-BF533(M)
processor employs a “write one to modify” mechanism that
allows any combination of individual flags to be modified
in a single instruction, without affecting the level of any
other flags. Four control registers are provided. One register is written in order to set flag values, one register is
written in order to clear flag values, one register is written
Page 9 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
in order to toggle flag values, and one register is written in
order to specify a flag value. Reading the flag status register
allows software to interrogate the sense of the flags.
• Flag interrupt mask registers – The two flag interrupt mask
registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
• Flag interrupt sensitivity registers – The two flag interrupt
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters, ITU-R
601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock
pin, up to 3 frame synchronization pins, and up to 16 data pins.
The input clock supports parallel data rates up to half the system
clock rate.
In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R 656 modes are supported:
• Active video only – The PPI does not read in any data
between the end of active video (EAV) and start of active
video (SAV) preamble symbols, or any data present during
the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.
• Vertical blanking only – The PPI only transfers vertical
blanking interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.
• Entire field – The entire incoming bitstream is read in
through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
Rev. PrA |
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF533(M) processor provides five operating modes,
each with a different performance/power profile. In addition,
dynamic power management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. Control of clocking to each of the
ADSP-BF533(M) processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for
each mode.
Full-on Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 4. Power Settings
Mode
PLL
PLL
Core
Bypassed Clock
(CCLK)
Full-on
Enabled No
Enabled
Active
Enabled/ Yes
Enabled
Disabled
Sleep
Enabled
Disabled
Deep Sleep Disabled
Disabled
Hibernate Disabled
Disabled
Page 10 of 48 | November 2004
System Core
Clock
Power
(SCLK)
Enabled On
Enabled On
Enabled On
Disabled On
Disabled Off
Preliminary Technical Data
ADSP-BF533(M)
Hibernate Operating Mode—Maximum Static Power
Savings
The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a nonvolatile
storage device prior to removing power if the processor state is
to be preserved. Since VDDEXT is still supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up either by a realtime clock wakeup or by asserting the RESET pin.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled,
the processor will transition to the active mode.
Alternatively, because the ADSP-BF533(M) processor includes
an on-chip oscillator circuit, an external crystal may be used.
The crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in Figure 5.
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
CLKIN
XTAL
CLKOUT
Figure 5. External Crystal Connections
As shown in Figure 6 on Page 11, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1x to 63x multiplication factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10x, but it can be
modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the
PLL_DIV register.
When in the sleep mode, system DMA access to L1 memory is
not supported.
“FI NE” ADJUSTMENT
REQUI RES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode.
assertion of RESET while in deep sleep mode causes the processor to transition to the full-on mode.
CLOCK SIGNALS
PLL
0. 5×−64×
CLKIN
CCLK
÷ 1:15
SCLK
VCO
SCLK< = CCLK
SCLK < = 133 MHZ
Figure 6. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
The ADSP-BF533(M) processor can be clocked by an external
crystal, a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator.
If an external clock is used, it must not be halted, changed, or
operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin.
When an external clock is used, the XTAL pin must be left
unconnected.
Rev. PrA |
÷ 1, 2, 4, 8
Page 11 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 5 illustrates typical system clock ratios.
Table 5. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0011
1010
Divider Ratio Example Frequency Ratios
VCO/SCLK
(MHz)
VCO
SCLK
1:1
100
100
3:1
400
133
10:1
500
50
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 6. This programmable core clock capability is useful for
fast core frequency modifications.
Table 6. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Divider Ratio Example Frequency Ratios
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
500
125
8:1
200
25
BOOTING MODES
The ADSP-BF533(M) processor has two mechanisms (listed in
Table 7) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute from
external memory, bypassing the boot sequence.
Table 7. Booting Modes
BMODE1–0
00
01
10
11
Description
Execute from 16-bit External Memory (Bypass
Boot ROM)
Boot from 8-bit or 16-bit FLASH
Boot from SPI Host (Slave mode)
Boot from SPI Serial EEPROM (8-, 16-, or 24-bit
address range)
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, implement the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous memory bank 0. All configuration settings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM (8, 16, or 24-bit
addressable) – The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read commands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8-, 16-, or 24-bit addressable EEPROM is detected,
and begins clocking data into the beginning of L1 instruction memory.
For each of the boot modes, a ten-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
Rev. PrA |
Page 12 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Set conditional breakpoints on registers, memory,
and stacks.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Perform linear or statistical profiling of program execution.
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
• Create custom debugger windows.
DEVELOPMENT TOOLS
The ADSP-BF533(M) processor is supported with a complete
set of CROSSCORE®* software and hardware development
tools, including Analog Devices emulators and VisualDSP++®†
development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF533(M) processor.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information).
• Insert breakpoints.
*
CROSSCORE is a registered trademark of Analog Devices, Inc.
†
VisualDSP++ is a registered trademark of Analog Devices, Inc.
Rev. PrA |
• Trace instruction execution.
• Fill, dump, and graphically plot the contents of memory.
• Perform source level debugging.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software
applications. Components can be downloaded from the Web
and dropped into the application. Component archives can be
published from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphical and textual environments.
Analog Devices emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF533(M) processor to monitor and control
the target board processor during emulation. The emulator pro-
Page 13 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
vides full speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. The emulator uses
the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
Rev. PrA |
Page 14 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
PIN DESCRIPTIONS
ADSP-BF533(M) processor pin definitions are listed in Table 8.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate functionality is shown in italics.
Table 8. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR3
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
I/O Function
Driver Type1
O
I/O
O
I
O
O
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request
Bus Grant
Bus Grant Hang
A2
A2
A2
O
I
O
O
O
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
A2
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
A2
A2
A2
A2
B4
A2
A2
I/O Timer 0
I/O Timer 1/PPI Frame Sync1
I/O Timer 2/PPI Frame Sync2
C5
C5
C5
Rev. PrA |
Page 15 of 48 | November 2004
A2
A2
A2
A2
A2
ADSP-BF533(M)
Preliminary Technical Data
Table 8. Pin Descriptions (Continued)
Pin Name
Parallel Peripheral Interface Port/GPIO
PF0/SPISS
PF1/SPISEL1/TMRCLK
PF2/SPISEL2
PF3/SPISEL3/PPI_FS3
PF4/SPISEL4/PPI15
PF5/SPISEL5/PPI14
PF6/SPISEL6/PPI13
PF7/SPISEL7/PPI12
PF8/PPI11
PF9/PPI10
PF10/PPI9
PF11/PPI8
PF12/PPI7
PF13/PPI6
PF14/PPI5
PF15/PPI4
PPI3–0
PPI_CLK
Serial Ports
RSCLK0
RFS0
DR0PRI
DR0SEC
TSCLK0
TFS0
DT0PRI
DT0SEC
RSCLK1
RFS1
DR1PRI
DR1SEC
TSCLK1
TFS1
DT1PRI
DT1SEC
SPI Port
MOSI
MISO7
SCK
I/O Function
Driver Type1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Programmable Flag 0/SPI Slave Select Input
Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference
Programmable Flag 2/SPI Slave Select Enable 2
Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3
Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15
Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14
Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13
Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12
Programmable Flag 8/PPI 11
Programmable Flag 9/PPI 10
Programmable Flag 10/PPI 9
Programmable Flag 11/PPI 8
Programmable Flag 12/PPI 7
Programmable Flag 13/PPI 6
Programmable Flag 14/PPI 5
Programmable Flag 15/PPI 4
PPI3–0
PPI Clock
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
I/O
I/O
I
I
I/O
I/O
O
O
I/O
I/O
I
I
I/O
I/O
O
O
SPORT0 Receive Serial Clock
SPORT0 Receive Frame Sync
SPORT0 Receive Data Primary
SPORT0 Receive Data Secondary
SPORT0 Transmit Serial Clock
SPORT0 Transmit Frame Sync
SPORT0 Transmit Data Primary
SPORT0 Transmit Data Secondary
SPORT1 Receive Serial Clock
SPORT1 Receive Frame Sync
SPORT1 Receive Data Primary
SPORT1 Receive Data Secondary
SPORT1 Transmit Serial Clock
SPORT1 Transmit Frame Sync
SPORT1 Transmit Data Primary
SPORT1 Transmit Data Secondary
D6
C5
I/O Master Out Slave In
I/O Master In Slave Out
I/O SPI Clock
Rev. PrA |
Page 16 of 48 | November 2004
D6
C5
C5
C5
D6
C5
D6
C5
C5
C5
C5
C5
D6
Preliminary Technical Data
ADSP-BF533(M)
Table 8. Pin Descriptions (Continued)
Pin Name
UART Port
RX
TX
Real-Time Clock
RTXI8
RTXO
JTAG Port
TCK
TDO
TDI
TMS
TRST9
EMU
Clock
CLKIN
XTAL
Mode Controls
RESET
NMI8
BMODE1–0
Voltage Regulator
VROUT1–0
Supplies
VDDEXT
VDDINT
VDDRTC
GND
I/O Function
Driver Type1
I
O
UART Receive
UART Transmit
C5
I
O
RTC Crystal Input
RTC Crystal Output
I
O
I
I
I
O
JTAG Clock
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
Emulation Output
I
O
Clock/Crystal Input
Crystal Output
I
I
I
Reset
Non-Maskable Interrupt
Boot Mode Strap
O
External FET Drive
P
P
P
G
I/O Power Supply
Core Power Supply
Real-Time Clock Power Supply
External Ground
1
Refer to Figure 23 on Page 37 to Figure 27 on Page 38.
See Figure 22 and Figure 23 on Page 37
3
This pin should be pulled HIGH when not used.
4
See Figure 24 and Figure 25 on Page 37
5
See Figure 26 and Figure 27 on Page 38
6
See Figure 28 and Figure 29 on Page 38
7
This pin should always be pulled HIGH through a 4.7 kΩ resistor if booting via the SPI port.
8
This pin should always be pulled LOW when not used.
9
This pin should be pulled LOW if the JTAG port will not be used.
2
Rev. PrA |
Page 17 of 48 | November 2004
C5
C5
ADSP-BF533(M)
Preliminary Technical Data
SPECIFICATIONS
Component specifications are subject to change
without notice.
RECOMMENDED OPERATING CONDITIONS
Parameter
VDDINT
VDDEXT
VDDRTC
VIH
VIHCLKIN
VIL
Internal Supply Voltage
External Supply Voltage
Real-Time Clock Power Supply Voltage
High Level Input Voltage1, 2 @ VDDEXT =maximum
High Level Input Voltage3 @ VDDEXT =maximum
Low Level Input Voltage2, 4 @ VDDEXT =minimum
Minimum
1.39
2.25
2.25
2.0
2.2
–0.3
Nominal
1.42
2.5 or 3.3
Maximum
1.45
3.6
3.6
3.6
3.6
0.6
Unit
V
V
V
V
V
V
1
The ADSP-BF533(M) processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because
VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0, RSCLK1–0, TSCLK1–0,
RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET,
NMI, and BMODE1–0).
2
Parameter value applies to all input and bidirectional pins except CLKIN.
3
Parameter value applies to CLKIN pin only.
4
Parameter value applies to all input and bidirectional pins.
ELECTRICAL CHARACTERISTICS
Parameter
VOH
VOL
IIH
IIHP
IIL
IOZH
IOZL
CIN
1
High Level Output Voltage
Low Level Output Voltage2
High Level Input Current2
High Level Input Current JTAG3
Low Level Input Current4
Three-State Leakage Current4
Three-State Leakage Current5
Input Capacitance5, 6
Test Conditions
@ VDDEXT = 3.0V, IOH = –0.5 mA
@ VDDEXT = 3.0V, IOL = 2.0 mA
@ VDDEXT = maximum, VIN = VDD maximum
@ VDDEXT = maximum, VIN = VDD maximum
@ VDDEXT = maximum, VIN = 0 V
@ VDDEXT = maximum, VIN = VDD maximum
@ VDDEXT = maximum, VIN = 0 V
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
1
Applies to output and bidirectional pins.
Applies to input pins except JTAG inputs.
3
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4
Applies to three-statable pins.
5
Applies to all signal pins.
6
Guaranteed, but not tested.
2
Rev. PrA |
Page 18 of 48 | November 2004
Minimum
2.4
Maximum
0.4
10.0
20.0
10.0
10.0
10.0
8.0
Unit
V
V
µA
µA
µA
µA
µA
pF
Preliminary Technical Data
ADSP-BF533(M)
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
For proper SDRAM controller operation, the maximum load
capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for
ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, CLKOUT,
SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Parameter
Internal (Core) Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Load Capacitance
ADSP-BF533 Core Clock (CCLK)
Peripheral Clock (SCLK)
Storage Temperature Range
Junction Temperature Under Bias
Rating
–0.3 V to +1.45 V
–0.3 V to +3.8 V
–0.5 V to 3.6 V
–0.5 V to VDDEXT +0.5 V
200 pF
627 MHz
133 MHz
–65ºC to +150ºC
105ºC
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF533(M) processor features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
Rev. PrA |
Page 19 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 9 through Table 11 describe the timing requirements for
the ADSP-BF533(M) processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock and system clock as described in Absolute Maximum
Ratings on Page 19, and the voltage controlled oscillator (VCO)
operating frequencies described in Table 10. Table 10 describes
phase-locked loop operating conditions.
Table 9. Core and System Clock Requirements—ADSP-BF533SKBCE10
Parameter
tCCLK
Core Cycle Period
System Clock Period
tSCLK
Min
1.594
Maximum of 7.5 or tCCLK
Max
Unit
ns
ns
Min
50
Max
Max CCLK
Unit
MHz
Table 10. Phase-Locked Loop Operating Conditions
Parameter
Voltage Controlled Oscillator (VCO) Frequency
fVCO
Table 11. Maximum SCLK Conditions
Parameter
fSCLK
VDDEXT = 3.3 V
133
VDDEXT = 2.5 V
133
Rev. PrA |
Page 20 of 48 | November 2004
Unit
MHz
Preliminary Technical Data
ADSP-BF533(M)
Clock and Reset Timing
Table 12 and Figure 7 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 19, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 627/133 MHz.
Table 12. Clock and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period
tCKINL
CLKIN Low Pulse1
CLKIN High Pulse1
tCKINH
tWRST
RESET Asserted Pulse Width Low2
1
2
Min
Max
Unit
25.0
10.0
10.0
11 tCKIN
100.0
ns
ns
ns
ns
Applies to bypass mode and non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 7. Clock and Reset Timing
Rev. PrA |
Page 21 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 13. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
tHO
1
Min
Max
Unit
2.1
0.8
4.0
0.0
ns
ns
ns
ns
6.0
ns
ns
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
t DO
tHO
ARE
t SARDY
tHARDY
t HARDY
ARDY
t SARDY
t SDAT
t HDAT
DATA15–0
READ
Figure 8. Asynchronous Memory Read Cycle Timing
Rev. PrA |
Page 22 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
Asynchronous Memory Write Cycle Timing
Table 14. Asynchronous Memory Write Cycle Timing
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
tHO
1
Min
4.0
0.0
1.0
6.0
0.8
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t HARDY
t SARDY
ARDY
tSARDY
t END AT
DATA15–0
WRITE DATA
Figure 9. Asynchronous Memory Write Cycle Timing
Rev. PrA |
Page 23 of 48 | November 2004
t DD AT
Unit
ns
ns
6.0
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
Max
ns
ns
ns
ns
ADSP-BF533(M)
Preliminary Technical Data
SDRAM Interface Timing
Table 15. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
tHSDAT
DATA Hold After CLKOUT
Switching Characteristics
tSCLK
CLKOUT Period
tSCLKH
CLKOUT Width High
tSCLKL
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT2
tDCAD
tHCAD
Command, ADDR, Data Hold After CLKOUT1
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
1
2
Min
Max
2.1
0.8
ns
ns
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
6.0
0.8
6.0
1.0
For VDDINT = 1.2 V.
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
tSCLKH
CLKOUT
t SSDAT
t SCLKL
tHSDAT
DATA (IN)
t DCAD
tENSDAT
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 10. SDRAM Interface Timing
Rev. PrA |
tD SDA T
tHCAD
DATA(OUT)
Page 24 of 48 | November 2004
Unit
Preliminary Technical Data
ADSP-BF533(M)
External Port Bus Request and Grant Cycle Timing
Table 16 and Figure 11 describe external port bus request and
bus grant operations.
Table 16. External Port Bus Request and Grant Cycle Timing
Parameter, 1, 2
Timing Requirements
tBS
BR Asserted to CLKOUT High Setup
tBH
CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
CLKOUT Low to xMS, Address, and RD/WR enable
tSE
tDBG
CLKOUT High to BG High Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH High Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
1
2
Min
Max
4.6
0.0
ns
ns
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
These are preliminary timing parameters that are based on worst-case operating conditions.
The pad loads for these timing parameters are 20 pF.
CLKOUT
tBS
tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 11. External Port Bus Request and Grant Cycle Timing
Rev. PrA |
Page 25 of 48 | November 2004
Unit
TEBH
ADSP-BF533(M)
Preliminary Technical Data
Parallel Peripheral Interface Timing
Table 17 and Figure 12 on Page 26 describe parallel peripheral
interface operations.
Table 17. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width
tPCLK
PPI_CLK Period1
tSFSPE
External Frame Sync Setup Before PPI_CLK
tHFSPE
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
tSDRPE
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
tDDTPE
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
tHDTPE
1
Min
6.0
15.0
3.0
3.0
2.0
4.0
10.0
10.0
0.0
DRIVE
EDGE
SAMPLE
EDGE
tPCLKW
PPI_CLK
tDFSPE
tSFSPE
tHFSPE
tSDRPE
tHDRPE
PPI_FS1
PPI_FS2
tDDTPE
tHDTPE
PPIx
Figure 12. GP Output Mode and Frame Capture Timing
Rev. PrA |
Page 26 of 48 | November 2004
Unit
ns
ns
ns
ns
ns
ns
0.0
PPI_CLK frequency cannot exceed fSCLK/2
tHOFSPE
Max
ns
ns
ns
ns
Preliminary Technical Data
ADSP-BF533(M)
Serial Ports
Table 18 through Table 21 on Page 28 and Figure 13 on Page 28
through Figure 15 on Page 30 describe Serial Port operations.
Table 18. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK1
tHFSE
TFS/RFS Hold After TSCLK/RSCLK1
tSDRE
Receive Data Setup Before RSCLK1
tHDRE
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
tSCLKEW
tSCLKE
TSCLK/RSCLK Period
Switching Characteristics
tDFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
tDDTE
Transmit Data Delay After TSCLK1
Transmit Data Hold After TSCLK1
tHDTE
1
2
Min
Max
3.0
3.0
3.0
3.0
4.5
15.0
Unit
ns
ns
ns
ns
ns
ns
10.0
0.0
10.0
0.0
ns
ns
ns
ns
Referenced to sample edge.
Referenced to drive edge.
Table 19. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK1
tHFSI
TFS/RFS Hold After TSCLK/RSCLK1
tSDRI
Receive Data Setup Before RSCLK1
tHDRI
Receive Data Hold After RSCLK1
TSCLK/RSCLK Width
tSCLKEW
tSCLKE
TSCLK/RSCLK Period
Switching Characteristics
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSI
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
tDDTI
Transmit Data Delay After TSCLK1
Transmit Data Hold After TSCLK1
tHDTI
tSCLKIW
TSCLK/RSCLK Width
1
2
Min
Max
8.0
−2.0
6.0
0.0
4.5
15.0
Unit
ns
ns
ns
ns
ns
ns
3.0
3.0
ns
ns
ns
ns
ns
Max
Unit
−1.0
−2.0
4.5
Referenced to sample edge.
Referenced to drive edge.
Table 20. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLK1
tDDTTE
Data Disable Delay from External TSCLK1
tDTENI
Data Enable Delay from Internal TSCLK1
Data Disable Delay from Internal TSCLK1
tDDTTI
1
Min
0
10.0
−2.0
3.0
Referenced to drive edge.
Rev. PrA |
Page 27 of 48 | November 2004
ns
ns
ns
ns
ADSP-BF533(M)
Preliminary Technical Data
Table 21. External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
Data Enable from Late FS or MCE = 1, MFD = 01,2
tDTENLFS
1
2
Min
Max
Unit
10.0
ns
ns
0
MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE.
If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
RFS
tHOFSE
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
TFS
tHOFSE
tSFSE
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 13. Serial Ports
Rev. PrA |
Page 28 of 48 | November 2004
tHFSE
Preliminary Technical Data
ADSP-BF533(M)
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tHOFSE/I
tSFSE/I
RFS
tDDTE/I
tDDTENFS
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDDTENFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 14. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrA |
Page 29 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I
tDTENLSCK
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLSCK
DT
1ST BIT
tHDTE/I
2ND BIT
tDDTLSCK
Figure 15. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrA |
Page 30 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 22 and Figure 16 describe SPI port master operations.
Table 22. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
tHSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
SPISELx Low to First SCK edge (x=0 or 1)
tSDSCIM
tSPICHM
Serial Clock High period
tSPICLM
Serial Clock Low period
tSPICLK
Serial Clock Period
tHDSM
Last SCK Edge to SPISELx High (x=0 or 1)
Sequential Transfer Delay
tSPITDM
tDDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
Min
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
ns
ns
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA = 1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
MOSI
(OUTPUT)
LSB VALID
tHDSPIDM
MSB
tSSPIDM
MISO
(INPUT)
tHSPIDM
MSB VALID
tDDSPIDM
CPHA = 0
tSSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 16. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrA |
Page 31 of 48 | November 2004
Unit
7.5
–1.5
SPISELx
(OUTPUT)
tSDSCIM
Max
tSPITDM
6
4.0
ADSP-BF533(M)
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 23 and Figure 17 describe SPI port slave operations.
Table 23. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock low Period
Serial Clock Period
tSPICLK
tHDS
Last SCK Edge to SPISS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
SPISS Assertion to Data Out Active
tDSOE
tDSDHI
SPISS Deassertion to Data High Impedance
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
Min
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
0
0
0
0
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tDSDHI
MSB
CPHA = 1
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
MSB VALID
tDSOE
MISO
(OUTPUT)
tDDSPID
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA = 0
tSSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
Figure 17. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrA |
Page 32 of 48 | November 2004
Unit
ns
ns
ns
ns
ns
ns
ns
ns
8
8
10
10
SPISS
(INPUT)
tSPICHS
Max
ns
ns
ns
ns
Preliminary Technical Data
ADSP-BF533(M)
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 18 describes UART port receive and transmit operations.
The maximum baud rate is SCLK/16. As shown in Figure 18
there is some latency between the generation internal UART
interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.
CLKOUT
(SAMPLE CLOCK)
RXD
DATA[8:5]
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
TXD
DATA[8:5]
STOP[2:1]
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 18. UART Port—Receive and Transmit Timing
Rev. PrA |
Page 33 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
Programmable Flags Cycle Timing
Table 24 and Figure 19 describe programmable flag operations.
Table 24. Programmable Flags Cycle Timing
Parameter
Timing Requirements
tWFI
Flag Input Pulse Width
Switching Characteristics
Flag Output Delay from CLKOUT Low
tDFO
Min
tSCLK + 1
tDFO
PF (OUTPUT)
FLAG OUTPUT
tWFI
FLAG INPUT
Figure 19. Programmable Flags Cycle Timing
Rev. PrA |
Page 34 of 48 | November 2004
Unit
ns
6
CLKOUT
PF (INPUT)
Max
ns
Preliminary Technical Data
ADSP-BF533(M)
Timer Cycle Timing
Table 25 and Figure 20 describe timer expired operations. The
input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 25. Timer Cycle Timing
Parameter
Timing Characteristics
tWL
Timer Pulse Width Input Low1 (Measured in SCLK Cycles)
tWH
Timer Pulse Width Input High1 (Measured in SCLK Cycles)
Switching Characteristics
Timer Pulse Width Output2 (Measured in SCLK Cycles)
tHTO
1
2
Min
Max
1
1
1
Unit
SCLK
SCLK
(232–1)
SCLK
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
tWL
tWH
Figure 20. Timer PWM_OUT Cycle Timing
Rev. PrA |
Page 35 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
JTAG Test and Emulation Port Timing
Table 26 and Figure 21 describe JTAG port operations.
Table 26. JTAG Port Timing
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
tHTAP
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (Measured in TCK cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
tDSYS
1
Min
Max
20
4
4
4
5
4
0
Unit
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PP3–0.
2
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 21. JTAG Port Timing
Rev. PrA |
Page 36 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
OUTPUT DRIVE CURRENTS
Figure 22 through Figure 29 show typical current-voltage characteristics for the output drivers of the ADSP-BF533(M)
processor. The curves represent the current drive capability of
the output drivers as a function of output voltage.
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
VDDEXT = 2.75V @ –40°C
50
0
VOH
–50
–100
0
V
–150
OH
VOL
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
–50
V
–100
–150
0
0.5
1.0
1.5
2.0
Figure 24. Drive Current B (Low VDDEXT)
OL
2.5
3.0
150
SOURCE VOLTAGE (V)
150
= 2.95V @ 95°C
DDEXT
V
= 3.30V @ 25°C
DDEXT
VDDEXT = 3.65V @ –40°C
V
100
VDDEXT = 2.95V @ 95°C
VDDEXT = 3.30V @ 25°C
VDDEXT = 3.65V @ –40°C
100
Figure 22. Drive Current A (Low VDDEXT)
SOURCE CURRENT (mA)
50
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
100
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
VDDEXT = 2.75V @ –40°C
100
SOURCE CURRENT (mA)
150
150
50
0
VOH
–50
50
–100
0
–150
VOL
VOH
0
–50
–100
–150
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 23. Drive Current A (High VDDEXT)
Rev. PrA |
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
Figure 25. Drive Current B (High VDDEXT)
VOL
0
0.5
Page 37 of 48 | November 2004
3.0
3.5
ADSP-BF533(M)
Preliminary Technical Data
100
60
40
SOURCE CURRENT (mA)
20
0
V
OH
–20
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
V
= 2.75V @ –40°C
DDEXT
80
60
SOURCE CURRENT (mA)
VDDEXT = 2.25V @ 95°C
VDDEXT = 2.50V @ 25°C
VDDEXT = 2.75V @ –40°C
40
20
0
VOH
–20
–40
–60
V
–40
VOL
–60
0
0.5
1.0
1.5
2.0
OL
–80
2.5
3.0
–100
0
0.5
SOURCE VOLTAGE (V)
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 26. Drive Current C (Low VDDEXT)
Figure 28. Drive Current D (Low VDDEXT)
100
60
40
20
0
VOH
–20
–40
50
0
V
OH
–50
VOL
–100
VOL
–60
VDDEXT = 2.95V @ 95°C
VDDEXT = 3.30V @ 25°C
V
= 3.65V @ –40°C
DDEXT
100
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
150
VDDEXT = 2.95V @ 95°C
V
= 3.30V @ 25°C
DDEXT
V
= 3.65V @ –40°C
DDEXT
80
–80
–150
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
SOURCE VOLTAGE (V)
Figure 27. Drive Current C (High VDDEXT)
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
Figure 29. Drive Current D (High VDDEXT)
Rev. PrA |
Page 38 of 48 | November 2004
3.0
3.5
Preliminary Technical Data
ADSP-BF533(M)
POWER DISSIPATION
Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 29 shows the power dissipation for
internal circuitry (VDDINT). Internal power dissipation is dependent on the instruction execution sequence and the data
operands involved.
Table 27. Internal Power Dissipation1
Parameter
IDDTYP3
IDDSLEEP4
IDDDEEPSLEEP4
IDDRTC5
Test Conditions2
fCCLK =
627 MHz
VDDINT =
1.42 V
300
73
65
30
Unit
mA
mA
mA
µA
1
See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors.
IDD data is specified for typical process parameters. All data at 25ºC.
3
Processor executing 75% dual Mac, 25% ADD with moderate data bus activity.
4
See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for definitions of sleep and deep sleep operating modes.
5
Measured at VDDRTC = 3.3V at 25ºC.
2
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• Number of output pins (O) that switch during each cycle
• Maximum frequency (f) at which they can switch
• Their load capacitance (C)
• Their voltage swing (VDDEXT)
The external component is calculated using:
P EXT = O × C × V
2
DD
×f
The frequency f includes driving the load high and then back
low. For example: DATA15–0 pins can drive high and low at a
maximum rate of 1/(2ⴛ tSCLK) while in SDRAM burst mode.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P TOTAL = P EXT + ( I DD × V DDINT )
Note that the conditions causing a worst-case PEXT differ from
those causing a worst-case PINT . Maximum PINT cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an application to have 100% or even 50% of the outputs switching
simultaneously.
Rev. PrA |
Page 39 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
TEST CONDITIONS
REFERENCE
SIGNAL
All timing parameters appearing in this data sheet were measured under the conditions described in this section.
tDIS_MEASURED
Output Enable Time
tDIS
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from the
point when a reference signal reaches a high or low voltage level
to the point when the output starts driving as shown in the Output Enable/Disable diagram (Figure 30). The time tENA_MEASURED
is the interval from when the reference signal switches to when
the output voltage reaches 2.0 V (output high) or 1.0 V (output
low). Time tTRIP is the interval from when the output starts driving to when the output reaches the 1.0 V or 2.0 V trip voltage.
Time tENA is calculated as shown in the equation:
tENA-MEASURED
tENA
VOH
(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOH
2.0V (MEASURED)
VOL (MEASURED) + ⌬V
1.0V
VOL
(MEASURED)
tDECAY
VOL
(MEASURED)
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 30. Output Enable/Disable
t ENA = t ENA_MEASURED – t TRIP
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
50 OHMS
TO
OUTPUT
PIN
1.5V
30pF
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
equation:
Figure 31. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
INPUT
OR
OUTPUT
1.5V
1.5V
t DECAY = ( C L ∆V ) ⁄ I L
The output disable time tDIS is the difference between tDIS_MEASURED
and tDECAY as shown in Figure 30. The time tDIS_MEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. The time tDECAY is calculated with test loads
CL and IL, and with ∆V equal to 0.5 V.
Figure 32. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
capacitance. The delay and hold specifications given should be
derated by a factor derived from these figures. The graphs in
these figures may not be linear outside the ranges shown.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-BF533(M) processor’s
output voltage and the input threshold for the device requiring
the hold time. A typical ∆V will be 0.4 V. CL is the total bus
capacitance (per data line), and IL is the total leakage or
three-state current (per data line). The hold time will be tDECAY
plus the minimum disable time (for example, tDSDAT for an
SDRAM write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 31). Figure 33 on Page 41 through
Figure 40 on Page 42 show how output rise time varies with
Rev. PrA |
Page 40 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
CLKOUT (CLKOUT DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85°C
12
ABE_B[0] (133 MHz DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85°C
RISE AND FALL TIME ns (10%-90%)
RISE AND FALL TIME ns (10%-90%)
14
12
RISE TIME
10
FALL TIME
8
6
4
10
RISE TIME
8
FALL TIME
6
4
2
2
0
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
50
250
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 35. Typical Output Delay or Hold for Driver B at EVDDMIN
Figure 33. Typical Output Delay or Hold for Driver A at EVDDMIN
CLKOUT (CLKOUT DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85°C
10
ABE0 (133 MHz DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85°C
RISE AND FALL TIME ns (10%-90%)
RISE AND FALL TIME ns (10%-90%)
12
10
RISE TIME
8
FALL TIME
6
4
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
1
2
0
0
0
50
100
150
LOAD CAPACITANCE (p F)
200
0
250
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 36. Typical Output Delay or Hold for Driver B at EVDDMAX
Figure 34. Typical Output Delay or Hold for Driver A at EVDDMAX
Rev. PrA |
Page 41 of 48 | November 2004
250
ADSP-BF533(M)
TMR0 (33 MHz DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85°C
SCK (66 MHz DRIVER), EVDDMIN = 2.25V, TEMPERATURE = 85°C
18
RISE AND FALL TIME ns (10%-90%)
RISE AND FALL TIME ns (10%-90%)
30
Preliminary Technical Data
25
RISE TIME
20
15
FALL TIME
10
16
14
RISE TIME
12
10
FALL TIME
8
6
4
5
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 37. Typical Output Delay or Hold for Driver C at EVDDMIN
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 39. Typical Output Delay or Hold for Driver D at EVDDMIN
TMR0 (33 MHz DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85°C
SCK (66 MHz DRIVER), EVDDMAX = 3.65V, TEMPERATURE = 85°C
14
RISE AND FALL TIME ns (10%-90%)
20
RISE AND FALL TIME ns (10%-90%)
0
250
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
12
RISE TIME
10
8
FALL TIME
6
4
2
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 38. Typical Output Delay or Hold for Driver C at EVDDMAX
Rev. PrA |
250
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 40. Typical Output Delay or Hold for Driver D at EVDDMAX
Page 42 of 48 | November 2004
250
Preliminary Technical Data
ADSP-BF533(M)
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + ( Ψ JT × P D )
where:
TJ = junction temperature (ⴗC)
TCASE = case temperature (ⴗC) measured by customer at top center of package.
ΨJT = from Table 28
PD = power dissipation (see Power Dissipation on Page 39 for
the method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
where:
TA = ambient temperature (ⴗC)
In Table 28, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Thermal resistance θJA in Table 28 is the figure of merit relating
to performance of the package and board in a convective environment. θJMA represents the thermal resistance under two
conditions of airflow. θJB represents the heat extracted from the
periphery of the board. ΨJT represents the correlation between
TJ and TCASE. Values of θJB are provided for package comparison
and printed circuit board design considerations.
Table 28. Thermal Characteristics for BC-160 Package
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
Condition
0 Linear m/s Airflow
1 Linear m/s Airflow
2 Linear m/s Airflow
Not applicable
Not applicable
0 Linear m/s Airflow
Typical
34.1
30.1
28.8
25.55
8.75
0.13
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
Rev. PrA |
Page 43 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
160-LEAD BGA PINOUT
Table 29 lists the BGA pinout by signal. Table 30 on Page 45
lists the BGA pinout by ball number.
Table 29. 160-Ball BGA Pin Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA10
DATA11
Ball No.
H13
H12
J14
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
K14
L14
J13
K13
L13
K12
L12
M12
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
P3
D14
A12
B14
M9
N9
N6
P6
Signal
DATA12
DATA13
DATA14
DATA15
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
M5
N5
P5
P4
P9
M8
N8
P8
M7
N7
P7
M6
K1
J2
G3
F3
H1
H2
F2
E3
M2
A10
A14
B11
C4
C5
C11
D4
D7
D8
D10
D11
F4
F11
G11
H4
H11
K4
K11
L5
Rev. PrA |
Signal
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF10
PF11
PF12
PF13
PF14
PF15
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PPI0
PPI1
PPI2
PPI3
PPI_CLK
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
Ball No.
L6
L8
L10
M4
M10
P14
E2
D3
B10
D2
C1
A4
A5
B5
B6
A6
C6
C2
C3
B1
B2
B3
B4
A2
A3
C8
B8
A7
B7
C9
C10
J3
G2
L1
G1
A9
A8
L3
E12
C14
Page 44 of 48 | November 2004
Signal
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
D1
B13
C13
D13
D12
P2
M3
N3
H3
E1
L2
M1
K2
N2
N1
J1
F1
K3
A1
C7
C12
D5
D9
F12
G4
J4
J12
L7
L11
P1
D6
E4
E11
J11
L4
L9
B9
A13
B12
A11
Preliminary Technical Data
ADSP-BF533(M)
Table 30 lists the BGA pinout by ball number. Table 29 on
Page 44 lists the BGA pinout by signal.
Table 30. 160-Ball BGA Pin Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
Signal
VDDEXT
PF8
PF9
PF10
PF11
PF14
PPI2
RTXO
RTXI
GND
XTAL
CLKIN
VROUT0
GND
PF4
PF5
PF6
PF7
PF12
PF13
PPI3
PPI1
VDDRTC
NMI
GND
VROUT1
SCKE
CLKOUT
PF1
PF2
PF3
GND
GND
PF15
VDDEXT
PPI0
PPI_CLK
RESET
GND
VDDEXT
Ball No.
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
E2
E3
E4
E11
E12
E13
E14
F1
F2
F3
F4
F11
F12
F13
F14
G1
G2
G3
G4
G11
G12
G13
G14
Signal
SMS
SCAS
SCK
PF0
MOSI
GND
VDDEXT
VDDINT
GND
GND
VDDEXT
GND
GND
SWE
SRAS
BR
TFS1
MISO
DT1SEC
VDDINT
VDDINT
SA10
ARDY
AMS0
TSCLK1
DT1PRI
DR1SEC
GND
GND
VDDEXT
AMS2
AMS1
RSCLK1
RFS1
DR1PRI
VDDEXT
GND
AMS3
AOE
ARE
Ball No.
H1
H2
H3
H4
H11
H12
H13
H14
J1
J2
J3
J4
J11
J12
J13
J14
K1
K2
K3
K4
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M1
M2
Signal
DT0PRI
DT0SEC
TFS0
GND
GND
ABE1
ABE0
AWE
TSCLK0
DR0SEC
RFS0
VDDEXT
VDDINT
VDDEXT
ADDR4
ADDR1
DR0PRI
TMR2
TX
GND
GND
ADDR7
ADDR5
ADDR2
RSCLK0
TMR0
RX
VDDINT
GND
GND
VDDEXT
GND
VDDINT
GND
VDDEXT
ADDR8
ADDR6
ADDR3
TMR1
EMU
Figure 41 lists the top view of the BGA ball configuration.
Figure 42 lists the bottom view of the BGA ball configuration.
Rev. PrA |
Page 45 of 48 | November 2004
Ball No.
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Signal
TDI
GND
DATA12
DATA9
DATA6
DATA3
DATA0
GND
ADDR15
ADDR9
ADDR10
ADDR11
TRST
TMS
TDO
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
ADDR19
ADDR18
ADDR17
GND
ADSP-BF533(M)
1
2
3
4
5
6
Preliminary Technical Data
7
8
9
10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
VDDEXT
VDDRTC
GND
VROUT
I/O
Figure 41. 160-Ball BGA Ball Configuration (Top View)
14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
VDDEXT
GND
I/O
VDDRTC
VROUT
Figure 42. 160-Ball BGA Ball Configuration (Bottom View)
Rev. PrA |
Page 46 of 48 | November 2004
Preliminary Technical Data
ADSP-BF533(M)
OUTLINE DIMENSIONS
Dimensions in Figure 43—160-Ball Mini-BGA (BC-160) are
shown in millimeters.
12.00 BSC SQ
14 12 10
8
6
4
2
13 11 9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
BALL A1
INDICATOR
10.40
BSC
SQ
TOP VIEW
1.70
MAX
A1 CORNER
INDEX AREA
0.80 BSC
BALL PITCH
1.31
1.21
1.11
DETAIL A
SEATING
PLANE
0.40 NOM
(NOTE 3)
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MO-205, VARIATION AE WITH EXCEPTION OF
THE BALL DIAMETER.
3. MINIMUM BALL HEIGHT 0.25.
BOTTOM VIEW
0.12
0.50
MAX
0.45
COPLANARITY
0.40
BALL DIAMETER
DETAIL A
Figure 43. 160-Ball Mini-BGA (BC-160)
ORDERING GUIDE
Part Number
ADSP-BF533SKBCE10
Temperature Package Description
Instruction Operating Voltage
Range
Rate (Max)
(Ambient )
0ºC to 70ºC Chip Scale Package Ball Grid Array (Mini-BGA) BC-160 627 MHz
1.42 V internal, 2.5 V or 3.3 V I/O
Rev. PrA |
Page 47 of 48 | November 2004
ADSP-BF533(M)
Preliminary Technical Data
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Rev. PrA |
Page 48 of 48 | November 2004