2.5 MSPS, 20-Bit Σ∆ ADC AD7760 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM VIN- VIN+ Multi-Bit Sigma-Delta Modulator DIFF VREF+ + BUF - Reconstruction AD7760 Programmable Decimation Control Logic, I/O and Registers MCLK SYNC AVDD1 AVDD2 AVDD3 AVDD4 DECAP RBIAS AGND MCLK VDRIVE DVDD DGND FIR Filter Engine DRDY CS RESET RD/WR High performance 20-bit Sigma-Delta ADC 118dB SNR at 78kHz output data rate 100dB SNR at 2.5MHz output data rate 2.5 MHz maximum fully filtered output word rate Programmable over-sampling rate (8x to 256x) Flexible parallel interface Fully differential modulator input On-chip differential amplifier for signal buffering Low pass FIR filter with default or user programmable coefficients Over-range alert bit Digital offset and gain correction registers Filter bypass modes Low power and power down modes Synchronization of multiple devices via SYNC pin DB0 - DB15 Figure 1. APPLICATIONS Data acquisition systems Vibration analysis Instrumentation PRODUCT OVERVIEW The AD7760 high performance 20-bit sigma delta analog to digital converter combines wide input bandwidth and high speed with the benefits of sigma delta conversion with performance of 100dB SNR at 2.5MSPS making it ideal for high speed data acquisition. Wide dynamic range combined with significantly reduced anti-aliasing requirements simplify the design process. An integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an over-range flag, internal gain & offset registers and a low-pass digital FIR filter make the AD7760 a compact highly integrated data acquisition device requiring minimal peripheral component selection. In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application. The AD7760 is ideal for applications demanding high SNR without necessitating design of complex front end signal processing. The differential input is sampled at up to 40MS/s by an analog modulator. The modulator output is processed by a series of low-pass filters, the final one having default or user programmable coefficients. The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760. The reference voltage supplied to the AD7760 determines the analog input range. With a 4V reference, the analog input range is ±3.2V differential biased around a common mode of 2V. This common mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements. The AD7760 is available in an exposed paddle 64-lead TQFP and 48-lead CSP packages and is specified over the industrial temperature range from -40°C to +85°C. Rev. PrN Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD7760 Preliminary Technical Data TABLE OF CONTENTS TABLE OF CONTENTS.................................................................. 2 Clocking the AD7760..................................................................... 14 AD7760—Specifications.................................................................. 3 Driving The AD7760...................................................................... 15 Timing Specifications....................................................................... 5 Using The AD7760..................................................................... 16 Timing Diagrams.............................................................................. 6 Bias Resistor Selection ............................................................... 16 Absolute Maximum Ratings............................................................ 7 Programmable FIR Filter............................................................... 17 ESD Caution.................................................................................. 7 Downloading a User-Defined Filter ............................................ 18 Pin Configuration and Functional Descriptions.......................... 8 Example Filter Download ......................................................... 18 Terminology .................................................................................... 10 AD7760 Registers ........................................................................... 20 Typical Performance Characteristics ........................................... 11 Non Bit-Mapped Registers........................................................ 21 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 22 AD7760 Interface............................................................................ 13 Ordering Guide .......................................................................... 22 REVISION HISTORY Rev. PrN | Page 2 of 22 Preliminary Technical Data AD7760 AD7760—SPECIFICATIONS Table 1. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, TA = +25°C, Full Power Mode, unless otherwise noted Parameter DYNAMIC PERFORMANCE Decimate by 256 Signal to Noise Ratio (SNR) 1 Spurious Free Dynamic Range (SFDR) 1 Total Harmonic Distortion (THD) 1 Intermodulation Distortion (IMD) 1 Decimate by 16 Signal to Noise Ratio (SNR) 1 Spurious Free Dynamic Range (SFDR) 1 Total Harmonic Distortion (THD) 1 Intermodulation Distortion (IMD) 1 Decimate by 8 Signal to Noise Ratio (SNR) 1 Spurious Free Dynamic Range (SFDR) 1 Total Harmonic Distortion (THD) 1 Intermodulation Distortion (IMD) 1 Intermodulation Distortion (IMD) 1 DC ACCURACY Resolution Integral Nonlinearity1 Differential Nonlinearity1 Offset Error1 Gain Error1 Offset Error Drift Gain Error Drift DIGITAL FILTER RESPONSE Decimate by 8 Group Delay Decimate by 16 Group Delay Decimate by 128 Group Delay ANALOG INPUT Differential Input Voltage DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage VREF Input DC Leakage Current VREF Input Capacitance POWER REQUIREMENTS AVDD1 (Modulator Supply) AVDD2 (General Supply) AVDD3 (Diff-Amp Supply) AVDD4 (Ref Buffer Supply) DVDD VDRIVE Test Conditions/Comments Specifcation Unit 118 118 -100 -100 dB typ dBFS typ dB typ dB typ 103 103 -100 -100 dB typ dBFS typ dB typ dB typ 100 100 -100 -100 -100 dB typ dBFS typ dB typ dB typ dB typ 20 1 1 0.03 5 0.0006 0.1 Bits LSB typ LSB typ % typ LSB typ % /°C LSB /°C MCLK = 40MHz 12 µS typ MCLK = 40MHz 24 µS typ MCLK = 24.576MHz 480 µS typ Vin(+) – Vin(-), VREF = 2.5V Vin(+) – Vin(-), VREF = 4.096V ±2 ±3.25 ±2 5 55 V pk-pk V pk-pk µA max pF typ pF typ VDD3 = 3.3V VDD3 = 5V +2.5 +4.096 ±1 5 Volts Volts µA max pF max ±5% ±5% +2.5 +5 +3.0/+5.5 +3.15/+5.25 +2.5 +1.65/+2.7 Volts Volts V min/max V min/max Volts V min/max MCLK = 24.576MHz, ODR = 48kHz, FIN = 1kHz Sine Wave Non-harmonic Input Amplitude = -6dB MCLK = 40MHz, ODR = 1.25MHz, FIN =100kHz Sine Wave Non-harmonic Input Amplitude = -6dB MCLK = 40MHz, ODR = 2.5MHz, FIN = 100kHz Sine Wave Non-harmonic Input Amplitude = -6dB FIN = 100kHz Sine Wave FIN = 1MHz Sine Wave At 18 bits Guaranteed monotonic to 20 bits With internal buffer With external buffer ±5% Rev. PrN | Page 3 of 22 AD7760 Parameter Full Power Mode AIDD1 (Modulator) AIDD2 (General) AIDD4 (Reference Buffer) Low Power Mode AIDD1 (Modulator) AIDD2 (General) AIDD4 (Reference Buffer) AIDD3 (Diff Amp) DIDD Standby Mode AIDD1 (Modulator) AIDD2 (General) AIDD3 (Diff Amp) AIDD4 (Reference Buffer) DIDD POWER DISSIPATION Full Power Mode Modulator (P1) General (P2) Reference Buffer (P4) Low Power Mode Modulator (P1) General (P2) Reference Buffer (P4) Differential Amplifier (P3) Digital Power Standby Mode 1 Preliminary Technical Data Test Conditions/Comments Specifcation Unit AVDD4 = +5V 50 35 35 mA typ mA typ mA typ AVDD4 = +5V 26 20 10 mA typ mA typ mA typ AVDD3 = +5V, Both Modes Both Modes 42 45 mA typ mA typ AVDD3 = +5V AVDD4 = +5V Clock Stopped Clock Running 210 30 30 30 250 690 µA typ nA typ nA typ nA typ µA typ µA typ AVDD4 = +3.3V AVDD4 = +5V 125 175 101 175 mW typ mW typ mW typ mW typ 65 100 27 50 116 210 112.5 1.2 2.3 mW typ mW typ mW typ mW typ mW typ mW typ mW typ mW typ mW typ AVDD4 = +3.3V AVDD4 = +5V AVDD3 = +3.3V AVDD3 = +5V Clock Stopped Clock Running See Terminology Rev. PrN | Page 4 of 22 Preliminary Technical Data AD7760 TIMING SPECIFICATIONS Table 2. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25°C, CLOAD = 25pF, Full Power Mode, unless otherwise noted Parameter fMCLK Unit MHz min MHz max MHz min MHz max typ Description Applied Master Clock Frequency t11 Limit at TMIN, TMAX 12.288 80 12.288 20 0.5 × tICLK t2 10 nS min DRDY Falling Edge to CS falling Edge t3 2 nS min RD/WR Setup Time to CS Falling Edge t4 t5 10 tICLK nS typ min Data Access Time CS Low Pulse Width t6 tICLK min CS High Pulse Width Between Reads t7 2 nS min RD/WR Hold Time to CS Rising Edge t8 t9 10 0.5 × tICLK nS max typ Bus Relinquish Time DRDY High Period t10 0.5 × tICLK typ DRDY Low Period t11 t12 15 TBD nS typ xS min Data Access Time Data Valid Prior to DRDY Rising Edge t13 TBD xS min Data Valid After DRDY Rising Edge t14 t15 10 tICLK nS max xS min Bus Relinquish Time CS Low Pulse Width t16 tICLK xS min CS High Period Between Address and Data t17 t18 10 10 nS min nS min Data Setup Time Data Hold Time fICLK 1 Internal Modulator Clock Derived from MCLK. DRDY Pulse Width tICLK = 1/fICLK Rev. PrN | Page 5 of 22 AD7760 Preliminary Technical Data TIMING DIAGRAMS t5 t1 t6 t2 t7 t3 t4 t8 Figure 2. Parallel Interface Timing Diagram t9 t11 t12 t10 t13 t14 Figure 3. 20MHz Modulator Data Output Mode t15 t17 t16 t18 Figure 4. AD7760 Register Write Rev. PrN | Page 6 of 22 Preliminary Technical Data AD7760 ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. Parameters VDD to GND VIN+ to GND VIN– to GND Digital input voltage to GND Digital output voltage to GND VREF to GND Input current to any pin except supplies1 Operating temperature range Commercial (A, B version) Storage temperature range Junction temperature TQFP Exposed Paddle Package θJA thermal impedance θJC thermal impedance CSP Package θJA thermal impedance θJC thermal impedance Lead temperature, soldering Vapor phase (60 secs) Infrared (15 secs) ESD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating TBD TBD TBD TBD TBD TBD TBD −40°C to +85°C −65°C to +150°C 150°C 92.7 °C/W 5.1 °C/W 26.7 °C/W 30 °C/W 215°C 220°C TBD kV 1 Transient currents of up to TBD mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrN | Page 7 of 22 AD7760 Preliminary Technical Data 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 12 37 RESET 13 36 SYNC 14 35 DGND 34 AGND 33 AV DD1 37 DB11 38 DB10 40 DB8 41 DB7 42 DB6 43 DB5 39 DB9 30 CS 29 RD/WR 28 DRDY 27 RESET 26 SYNC 25 AVDD1 AGND 24 11 38 DRDY 31 DVDD AVDD2 10 AVDD2 11 RBIAS 12 DECAP2 21 39 RD/WR AGND 16 44 DB4 TOP VIEW (Not to Scale) 40 CS 15 45 DB3 AD7760 REFGND 7 VREF+ 8 AVDD4 9 41 DV DD TOP VIEW (Not to Scale) 46 DB2 DECAP1 6 43 DGND VIN- 19 AVDD2 20 DECAP1 8 REFGND 9 VREF+ 10 AGND AVDD4 AGND AVDD2 AVDD2 44 VDRIVE 42 DGND AD7760 33 DB15 32 VDRIVE AGND 23 45 DB15 DECAP3 22 46 DB14 AGND 5 AVDD1 6 AGND 7 35 DB13 34 DB14 MCLK 3 AVDD2 4 AVDD1 5 47 DB13 VOUTA1+ 16 AVDD3 17 VIN+ 18 PIN 1 IDENTIFIER 36 DB12 PIN 1 IDENTIFIER VINA1+ 13 VINA1- 14 VOUTA1- 15 MCLK 2 MCLK 3 AVDD2 4 VDRIVE 1 MCLK 2 48 DB12 DGND 1 47 DB1 48 DB0 DB11 DB10 DB9 DGND DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND DGND VDRIVE PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS AGND AGND DECAP3 DECAP2 AGND AVDD2 VIN+ VIN- AVDD3 AGND VOUTA1VOUTA1+ VINA1+ VINA1- AGND RBIAS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 6. 48-PIN LFCSP Pin Configuration Figure 5. 64-Lead TQFP Pin Configuration Table 4. Pin Function Descriptions TQFP Pin Number 6, 33 CSP Pin Number 5, 25 Pin Mnemonic Description AVDD1 4, 14, 15, 27 24 4, 10, 11, 20 17 AVDD2 12 9 AVDD4 5, 7, 11, 13, 16, 18, 23, 28, 31, 32, 34 9 41 23, 24, Paddle AGND +2.5V power supply for modulator. These pins should be decoupled to AGND with 100nF and 10µF capacitors on each pin. +5V power supply. These pins should be decoupled to AGND with TBD nF and TBD µF capacitors on each pin. +3.3V to +5V power supply for differential amplifier. These pins should be decoupled to AGND with a 100nF capacitor. +3.3V to +5V power supply for reference buffer. This pin should be decoupled to AGND with a 10nF capacitor in series with a 22Ω resistor. Power supply ground for analog circuitry. In the Chip Scale package, most of the internal AGND pads are down-bonded to the exposed paddle. This paddle then become the main analog ground connection for the AD7760. 7 31 REFGND DVDD 44, 63 1, 32 VDRIVE 1, 35, 42, 43, 53, 62, 64 Paddle DGND AVDD3 Reference Ground. Ground connection for the reference voltage. +2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to DGND with a 470nF capacitor. Logic power supply input, +1.8V to +2.5V. The voltage supplied at these pins will determine the operating voltage of the logic interface. Both these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a 470nF capacitor. Ground Reference for digital circuitry. In the Chip Scale package, all the internal DGND pads are down-bonded to the exposed paddle. This paddle then becomes the single ground connection for the AD7760. Rev. PrN | Page 8 of 22 Preliminary Technical Data AD7760 TQFP Pin Number 19 20 21 22 25 26 10 CSP Pin Number 13 14 15 16 18 19 8 Pin Mnemonic Description VINA1+ VINA1VOUTA1VOUTA1+ VIN+ VINVREF+ 8 29 30 17 6 21 22 12 DECAP1 DECAP2 DECAP3 RBIAS 45-52, 54-61 33-48 DB15 – DB0 37 27 RESET 3 3 MCLK 2 36 2 26 MCLK SYNC 39 29 RD/WR 38 28 DRDY 40 30 CS Positive Input to Full-Power Differential Amplifier 1. Negative Input to Full-Power Differential Amplifier 1. Negative Output from Full-Power Differential Amplifier 1. Positive Output from Full-Power Differential Amplifier 1. Positive Input to the Modulator. Negative Input to the Modulator. Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See Reference Section for more details. Decoupling Pin. A 100nF capacitor must be inserted between this pin and AGND. Decoupling Pin. A TBD µF capacitor must be inserted between this pin and AGND. Decoupling Pin. A TBD µF capacitor must be inserted between this pin and AGND. Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more details on this, see the Bias Resistor Section. 16-bit bi-directional data bus. These are three-state pins that are controlled by the CS and RD /WR pins. The operating voltage for these pins is determined by the VDRIVE voltage. See Interfacing Section for more details. A falling edge on this pin resets all internal digital circuitry. Holding this pin lows keeps the AD7760 in a reset state. Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate will depend on the frequency of this clock. See Clocking Section for more details. Master Clock ground sensing pin. Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. Read/Write Input. This pin, in conjunction with the Chip Select pin, is used to read and write data to and from the AD7760. If this pin is low when CS is low, a read will take place. If this pin is high and CS is low, a write will occur. See AD7760 Interface Section for more details. Data Ready Output. Each time that new conversion data is available, an active low pulse, ½ ICLK period wide, is produced on this pin. See AD7760 Interface Section for further details. Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the AD7760. See AD7760 Interface Section for further details. Rev. PrN | Page 9 of 22 AD7760 Preliminary Technical Data TERMINOLOGY Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76 ) dB Thus, for an 18-bit converter, this is 110.12dBs and for a 20-bit converter, 122.16 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7760, it is defined as THD (dB ) = 20 log V22 + V32 + V42 + V52 + V62 V1 products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb). The AD7760 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but, for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Non-Harmonic Spurious Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component excluding harmonics. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion Offset Error The deviation of the first code transition (000...000 to 000...001) from the ideal (that is, AGND + 1 LSB). Gain Error The deviation of the last code transition (111...110 to 111...111) from the ideal (that is, VREF − 1 LSB), after the offset error has been adjusted out. Power Supply Rejection Ratio (PSRR) The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fs. The frequency of this input varies from 1 kHz to 1 MHz. PSRR (dB ) = 10 log (Pf Pfs ) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. Rev. PrN | Page 10 of 22 Preliminary Technical Data AD7760 TYPICAL PERFORMANCE CHARACTERISTICS 000 000 000 000 000 ALL CAPS ( Init ial cap) ALL CAPS ( Init ial cap) Default Conditions: TA = 25°C, TBD, unless otherwise noted. TBD 000 000 000 000 000 TBD 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 000 000 000 000 Figure 7. TBD 000 ALL CAPS ( Init ial cap) ALL CAPS ( Init ial cap) 000 000 000 000 000 TBD 000 000 TBD 000 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 000 000 000 000 Figure 8. TBD 000 000 000 000 TBD 000 000 000 ALL CAPS ( Init ial cap) Figure 11. TBD 000 ALL CAPS ( Init ial cap) ALL CAPS ( Init ial cap) 000 Figure 10. TBD 000 000 000 000 000 000 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 TBD 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 000 Figure 9. TBD 000 000 000 000 000 ALL CAPS ( Init ial cap) Figure 12. TBD Rev. PrN | Page 11 of 22 AD7760 Preliminary Technical Data THEORY OF OPERATION The AD7760 employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to ICLK. Due to the high over-sampling rate, which spreads the quantization noise from 0 to fICLK, the noise energy contained in the band of interest is reduced (Figure 13a). To further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum; so that most of the noise energy is shifted out of the band of interest (Figure 13b). The digital filtering which follows the modulator removes the large out-of-band quantization noise (Figure 13c) while also reducing the data rate from fICLK at the input of the filter to fICLK/8 or less at the output of the filter, depending on the decimation rate used. Digital filtering has certain advantages over analog filtering. It does not introduce significant noise or distortion and can be made perfectly linear phase. The AD7760 employs three Finite Impulse Response (FIR) filters in series. By using different combinations of decimation ratios and filter selection and bypassing, data can be obtained from the AD7760 at a large range of data rates. Multi-bit data from the modulator can be obtained at a rate of 20MHz. The first filter receives data from the modulator at 20MHz where it is decimated by four to output data at 5MHz. This partially filtered data can also be output at this stage. The second filter allows the decimation rate to be chosen from 2x to 32x or to be QUANTIZATION NOISE fICLK/2 BAND OF INTEREST a. NOISE SHAPING fICLK/2 BAND OF INTEREST b. DIGITAL FILTER CUTOFF FREQUENCY fICLK/2 BAND OF INTEREST c. Figure 13. Sigma-Delta ADC completely bypassed. The third filter has a fixed decimation rate of 2x and is user programmable as well as having a default configuration. It is described in detail in the Programmable FIR Filter Section. This filter can also be bypassed. Table X below shows some characteristics of the default filter. The group delay of the filter is defined to be the delay to the centre of the impulse response and is equal to the computation + filter delays. The delay until valid data is available (the DVALID status bit is set) is equal to 2x the filter delay + the computation delay. Table 5. Configuration With Default Filter ICLK Frequency 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 12.288MHz 12.288MHz 12.288MHz 12.288MHz Filter 1 Filter 2 Filter 3 Data State Bypassed 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x Bypassed Bypassed Bypassed 2x 2x 4x 4x 8x 8x 16x 16x 32x 32x 8x 16x 32x 32x Bypassed Bypassed 2x Bypassed 2x Bypassed 2x Bypassed 2x Bypassed 2x Bypassed 2x 2x 2x Bypassed 2x Unfiltered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Fully Filtered Fully Filtered Partially Filtered Fully Filtered Computation Delay 0 0.325 1.075 1.35 1.625 1.725 1.775 2.6 2.25 4.175 3.1 7.325 4.65 3.66 5.05 11.92 7.57 Rev. PrN | Page 12 of 22 Filter Delay 0 1.2µS 10.8µS 3.6µS 22.8µS 6µS 44.4µS 10.8µS 87.6µS 20.4µS 174µS 39.6µS 346.8µS 142.6µS 283.2µS 64.45µS 564.5µS Passband Bandwidth (10 MHz) 1.35 MHz 1 MHz 562.5 kHz 500 kHz 281.25 kHz 250 kHz 140.625 kHz 125 kHz 70.3125 kHz 62.5 kHz 35.156 kHz 31.25 kHz 76.8 kHz 38.4 kHz 21.6 kHz 19.2 kHz Output Data Rate (ODR) 20 MHz 5 MHz 2.5 MHz 2.5 MHz 1.25 MHz 1.25 MHz 625 kHz 625 kHz 312.5 kHz 312.5 kHz 156.25 kHz 156.25 kHz 78.125 kHz 192 kHz 96 kHz 96 kHz 48 kHz Preliminary Technical Data AD7760 AD7760 INTERFACE Reading Data The AD7760 uses a 16-bit bi-directional parallel interface. This interface is controlled by the RD/WR and CS pins. There are two read operating modes depending on the output data rate. When the AD7760 is outputting data at 5MSPS or less, the interface operates in a conventional mode as shown in Figure 2. When a new conversion result is available, an active low pulse is output on the DRDY pin. To read a conversion result from the AD7760, two 16-bit read operations are performed. The DRDY pulse indicates that a new conversion result is available. Both RD/WR and CS go low to perform the first read operation. Shortly after both these lines go low, the databus becomes active and the 16 Most Significant Bits (MSBs) of the conversion result are output. The RD/WR and CS lines must return high for a period of TBD ns before the second read is performed. This second read will contain the 8 Least Significant Bits (LSBs) of the conversion result along with 7 status bits. These status bits are shown in Table 6. The Cal bit is set to a 1 if a calibration has been performed. Table 14 contains descriptions of the other status bits. Table 6. Status Bits During Data Read D7 DValid D0 Ovr UFilt LPwr FiltOk DLOk Cal 0 Shortly after RD/WR and CS return high, the databus will return to a high impedance state. Both read operations must be completed before a new conversion result is available as the new result will overwrite the contents on the output register. If a DRDY pulse occurs during a read operation, the data read will be invalid. When the AD7760 is operating in modulator data output mode, i.e. Output Data Rate at 20MHz, a different interfacing scheme is necessary. To obtain data from the AD7760 in this mode, both RD/WR and CS lines must be held low. This will bring the databus out of its high impedance state. Figure 3 shows the 20MHz Output Data Rate operation. A DRDY pulse is generated for each word and the data is valid on the rising edge of the DRDY pulse. This DRDY pulse could be used to latch the modulator data into a FIFO or as a DMA control signal. Shortly after the RD/WR and CS lines return high, the AD7760 will stop outputting data and the databus will return to high impedance. Sharing The Parallel Bus By its nature, the high accuracy of the AD7760 make it sensitive to external noise sources. These include digital activity on the parallel bus. For this reason it is recommended that the AD7760 data lines are isolated from the system databus by means of a latch or buffer to ensure that there is no digital activity on the D0-D15 pins that is not controlled by the AD7760. If multiple, synchronized, AD7760 parts that share a properly distributed common MCLK signal exist in a system, these parts can share a common bus without being isolated from each other. This bus can then be isolated from the system bus by a single latch or buffer. Writing To The AD7760 After a reset, only a single write operation to power up the AD7760 is necessary to start the part converting on default settings. While the AD7760 is configured to convert analog signals with the default settings on reset, there are many features and parameters on this part that the user can change by writing to the device. As some of the programmable registers are 16 bits wide, to program a register requires two write operations. The first write contains the register address while the second write contains the register data. There is an exception to this when a user filter is being downloaded to the AD7760. This is dealt with in detail in the following section. The AD7760 Registers section contains the register addresses and further details. Figure 4 shows a write operation to the AD7760. The RD/WR line is held high while the CS line is brought low for a minimum of TBD ns. The register address is latched during this period. The CS line is brought high again for a minimum of TBD ns before the register data is put onto the databus. If a read operation occurs between the writing of the register address and the register data, the register address is cleared and the next write must be the register address again. This also provides a method to get back to a known situation if the user somehow loses track whether the next write is an address or data. It is envisaged that the AD7760 will be written to and configured on power-up and very infrequently, if at all, after that. Following any write operation, the full group delay of the filter must pass before valid data will be output from the AD7760. Reading Status and Other Registers The AD7760 features a number of programmable registers. To read back the contents of these registers or the status register, the user must first write to the control register of the device setting a bit corresponding to the register they wish to read. The next read operation will then output the contents of the selected register instead of a conversion result. More information on the relevant bits in the control register is given in the AD7760 Registers section. Rev. PrN | Page 13 of 22 AD7760 Preliminary Technical Data CLOCKING THE AD7760 The AD7760 requires an external low jitter clock source. This signal is applied to the MCLK and MCLK pins. An internal clock signal (ICLK) is derived from the MCLK input signal. This ICLK controls all the internal operation of the AD7760. The maximum ICLK frequency is 20MHz but due to an internal clock divider, a range of MCLK frequencies can be used. There are three possibilities available to generate the ICLK: 1. ICLK = MCLK (CDIV[1:0] = 10) 2. ICLK = MCLK / 2 (CDIV[1:0] = 00) 3. ICLK = MCLK / 4 (CDIV[1:0] = 01) t j ( RMS ) = 256 = 133 ps 2 × π × 19.2 × 103 × 106 The input amplitude also has an effect on these jitter figures. If, for example, the input level was 3dB down from full-scale, the allowable jitter would be increased by a factor of √2 increasing the first example to 2.53ps RMS. This is due to the fact that the maximum slew rate is reduced by a reduction in amplitude. Figure 14 and Figure 15 illustrate this point showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes. These options are selected from the control register (See Register Section for further details). On power-up, the default is ICLK = MCLK / 4 to ensure that the part can handle the maximum MCLK frequency of 80MHz. If the user wishes to get output data rates equal to those used in audio systems, a 12.288 MHz ICLK frequency can be used. As shown in Table 5, output data rates of 192, 96 and 48kHz are achievable with this ICLK frequency. As mentioned previously, this ICLK frequency can be derived from different MCLK frequencies. The MCLK jitter requirements depend on a number of factors and are given by the following equation: Figure 14. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk OSR t j ( RMS ) = 2 × π × f IN × 10 SNR ( dB ) 20 OSR = Over-sampling ratio = f ICLK ODR fIN = Maximum Input Frequency SNR(dB) = Target SNR. Taking an example from Table 5: ODR = 2.5MHz, fICLK = 20MHz, fIN (max) = 1MHz, SNR = 108dB t j ( RMS ) = 8 = 1.79 ps 2 × π × 106 ×105.4 Figure 15. Maximum Slew Rate of Same Frequency Sine Wave with Amplitude of 1V Pk-Pk This is the maximum allowable clock jitter for a full-scale 1MHz input tone with the given ICLK and Output Data Rate. Taking a second example from Table 5: ODR = 48kHz, fICLK = 12.288MHz, fIN (max) = 19.2kHz, SNR = 120dB Rev. PrN | Page 14 of 22 Preliminary Technical Data AD7760 DRIVING THE AD7760 The AD7760 has an on-chip differential amplifier. This amplifier will operate with a supply voltage (AVDD3) from 3V to 5.5V. For a 4.096V reference, the supply voltage must be 5V. To achieve the specified performance in full power mode, the differential amplifier should be configured as a first order antialias filter as shown in Figure 16. Any additional filtering should be carried out in previous stages using low noise, highperformance op-amps such as the AD8021. +2.5V +3.685V 0V +2.048V A 0.410V -2.5V +2.5V VIN+ +3.685V B 0V +2.048V -2.5V 0.410V VIN- Figure 17. Differential Amplifier Signal Conditioning Suitable component values for the first order filter are listed in Table 7. Using the first row as an example would yield a 10dB attenuation at the first alias point of 19MHz. CFB RFB RIN A VINA1 CS B VIN+ RIN To obtain maximum performance from the AD7760, it is advisable to drive the ADC with differential signals. However, it is possible to drive the AD7760 with a single ended signal once the common mode of the signal is within the range of +0.7V to +2.1V with VDD3 = 5V or +0.7 to +1.25V with VDD3 = 3.3V. In this case the on-chip differential amplifier can be used to convert the signal from single-ended to differential before being fed into the modulator inputs. Figure 18 shows how a bipolar single-ended signal biased around ground can be used to drive the AD7760 with the use of an external op-amp such as the AD8021. CFB RFB 2R VIN CFB Figure 16. Differential Amplifier Configuration RFB RFB AD8021 R Table 7. Full Power Component Values RIN 2R RIN CS VIN+ RIN ODR VREF CS 2.5MHz 4.096v 1kΩ 655 Ω 5.6pF 33pF 2.5MHz 2.5v TBD Ω TBD Ω TBD TBD pF 48kHz 4.096v TBD Ω TBD Ω TBD TBD pF 48kHz 2.5v TBD Ω TBD Ω TBD TBD pF VINA1 RFB CFB Figure 17 shows the signal conditioning that occurs using the circuit in Figure 16 with a ±2.5v input signal biased around ground using the component values and conditions in the first row of Table 7. The differential amplifier will always bias the output signal to sit on the optimum common mode of VREF/2, in this case 2.048V. The signal is also scaled to give the maximum allowable voltage swing with this reference value. This is calculated as 80% of VREF, i.e. 0.8 × 4.096V ≈ 3.275V peak to peak on each input. Rev. PrN | Page 15 of 22 CFB Figure 18. Single Ended to Differential Conversion AD7760 Preliminary Technical Data USING THE AD7760 BIAS RESISTOR SELECTION The following is the recommended sequence for powering up and using the AD7760. The AD7760 requires a resistor to be connected between the RBIAS pin and AGND. The value for this resistor is dependant on the reference voltage being applied to the device. The resistor value should be selected to give a current of 25µA through the resistor to ground. For a 2.5V reference voltage, the correct resistor value is 100kΩ and for a 4.096V reference, 160kΩ. 1. Apply Power 2. Start clock oscillator, applying MCLK 3. Take RESET low for a minimum of 1 MCLK cycle 4. Wait a minimum of 2 MCLK cycles after RESET has been released. 5. Write to Control Register 2 to power up the ADC and the differential amplifiers as required. The correct Clock Divider (CDIV[1:0]) ratio should be programmed here also. 6. Write to Control Register 1 to set up the Output Data Rate. 7. Take SYNC low for a minimum of 2 MCLK cycles. Data can now be read from the part using the default filter, offset, gain and over range threshold values. The conversion data read will not be valid however until the group delay of the filter has passed. When this has occurred, the DVALID bit read with the data LSW will be set indicating that the data is indeed valid. The user can now download their own filter if required (see Downloading a User-Defined Filter). Values for gain, offset and over range threshold registers can be written or read at this stage. An internal calibration sequence can also be initiated at this point. Rev. PrN | Page 16 of 22 Preliminary Technical Data AD7760 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7760 is user programmable. The default coefficients that are loaded on reset are given in Table 8. This gives a frequency response shown in Figure 19. The frequencies quoted in Figure 19 scale directly with the Output Data Rate. • The filter must be even, symmetrical FIR. • The coefficients are in sign-and-magnitude format with 26 magnitude bits and sign coded as positive=0. • The filter length must be between 12 and 96 in steps of 12. • As the filter is symmetrical, the number of coefficients that must be downloaded will be half the filter length. The default filter coefficients are an example of this with only 48 coefficients listed for a 96-tap filter. • Coefficients are written from the center of impulse response (adjacent to the point of symmetry) outwards. • The coefficients are scaled so that the in-band gain of the filter is equal to 134217726 with the coefficients rounded to the nearest integer. For a low pass filter this is the equivalent of having the coefficients sum arithmetically (including sign) to +67108863 (0x3FF FFFF) positive value over the half-impulse-response coefficient set (max 48 coefficients). Any deviation from this will result in a gain error being introduced. Table 8. Default Filter Coefficients # Dec. Value Hex Value # 0 53656736 332BCA0 24 Dec. Value 700847 1 25142688 17FA5A0 25 -70922 2 -4497814 444A196 26 -583959 408E917 3 -11935847 4B62067 27 -175934 402AF3E 4 -1313841 4140C31 28 388667 5EE3B Hex Value AB1AF 401150A 6976334 6A734E 29 294000 47C70 6 3268059 31DDDB 30 -183250 402CBD2 7 -3794610 439E6B2 31 -302597 4049E05 8 -3747402 4392E4A 32 16034 3EA2 9 1509849 1709D9 33 238315 3A2EB 10 3428088 344EF8 34 88266 158CA 11 80255 1397F 35 -143205 4022F65 12 -2672124 428C5FC 36 -128919 401F797 13 -1056628 4101F74 37 51794 CA52 14 1741563 1A92FB 38 121875 1DC13 15 1502200 16EBF8 39 16426 402A 16 -835960 40CC178 40 -90524 401619C 17 -1528400 4175250 41 -63899 400F99B 18 93626 16DBA 42 45234 B0B2 19 1269502 135EFE 43 114720 1C020 20 411245 6466D 44 102357 18FD5 21 -864038 40D2F26 45 52669 CDBD 22 -664622 40A242E 46 15559 3CC7 23 434489 6A139 47 1963 7AB 0 Passband Ripple = 0.05 dB -0.1dB Frequency = 1.004MHz -3dB Frequency = 1.06MHz Stopband = 1.25MHz -20 -40 Amplitude (dB) 5 -60 -80 -100 -120 -140 -160 The default filter should be sufficient for almost all applications. It is a standard brick wall filter with a symmetrical impulse response. The default filter has a length of 96, in non-aliasing with 120dB of attenuation at Nyquist. This filter not only performs signal anti-aliasing but also suppresses out-of-band quantization noise produced by the A-D conversion process. Any significant relaxation in the stop-band attenuation or transition band width relative to the default filter may result in a failure to meet the SNR specifications. 0 500 1000 1500 2000 2500 Frequency (kHz) Figure 19. Default Filter Frequency Response (2.5MHz ODR) The procedure for downloading a user-defined filter is detailed in the Downloading a User-Defined Filter section. If a user does wish to create their own filter then the following should be noted: Rev. PrN | Page 17 of 22 AD7760 Preliminary Technical Data As previously mentioned, the filter coefficients are 27 bits in length; one sign and 26 magnitude bits. Since the AD7760 has a 16-bit parallel bus, the coefficients are padded with 5 MSB zeros to generate a 32-bit word and split into two 16-bit words for downloading. The first 16-bit word for each coefficient becomes (00000, Sign bit, Magnitude[25:16]), while the second word becomes (Magnitude [15:0]). To ensure that a filter is downloaded correctly, a checksum must also be generated and downloaded following the final coefficient. The checksum is a 16-bit word generated by splitting each 32-bit word mentioned above into 4 bytes and summing all bytes from all coefficients up to a maximum of 192 bytes (48 coefficients × 4 bytes). The same checksum is generated internally in the AD7760 and compared with the checksum downloaded. The DL_OK bit in the Status Register is set if these two checksums agree. The following is the procedure for downloading a user filter: 1. 2. Write to Control Register 1 setting the DL_Filt bit and also the correct filter length bits corresponding to the length of the filter about to be downloaded (See Table 9). Write the first half of the current coefficient data (00000, Sign bit, Magnitude[25:16]). The first coefficient to be written must be the one adjacent to the point of filter symmetry. 3. Write the second half of the current coefficient data (Magnitude [15:0]). 4. Repeat Steps 2 and 3 for each coefficient. 5. Write the 16-bit checksum. 6. There are two methods to verify that the filter coefficients have been downloaded correctly: a. b. It should be borne in mind that since the user coefficients are stored in RAM, they will be cleared after a RESET operation or a loss of power.. EXAMPLE FILTER DOWNLOAD The following is an example of downloading a short user defined filter with 24-taps. The frequency response is shown in Figure 20. 10 0 -10 Amplitude (dB) DOWNLOADING A USER-DEFINED FILTER -20 -30 -40 -50 -60 -70 -80 0 300 400 500 600 Figure 20. 24-Tap FIR Frequency Response The coefficients for the filter are listed in Table 10. The coefficients are in shown from the center of symmetry outwards. The raw coefficients were generated using a commercially available filter design tool and scaled appropriately so their sum equals +67108863 (0x3FF FFFF). Table 10. 24-Tap FIR Coefficients Read the Status Register checking the DL_OK bit. Coeff Start reading data and observe the status of the DL_OK bit. Num Coeffs Default 6 12 18 24 30 36 42 48 200 Frequency (kHz) Table 9. Filter Length Values FLEN[3:0] 0000 0001 0011 0101 0111 1001 1011 1101 1111 100 Filter Length Default 12 24 36 48 60 72 84 96 Rev. PrN | Page 18 of 22 1 Raw 0.365481974 Scaled 53188232 2 0.201339905 29300796 3 0.009636604 1402406 4 -0.075708848 -11017834 5 -0.042856209 -6236822 6 0.019944246 2902466 7 0.036437914 5302774 8 0.007592007 1104856 9 -0.021556583 -3137108 10 -0.024888355 -3621978 11 -0.012379538 -1801582 12 -0.001905756 -277343 Preliminary Technical Data AD7760 Table 11 shows the Hex values (in sign and magnitude format) that are downloaded to the AD7760 to realize this filter. The table is also split into the bytes which are all summed to produce the checksum. The checksum generated from these coefficients is 0x0E6B. Table 11. Filter Hex Values Coeff 0x0001 Address of Control Register 1 0x8079 Control Reg Data; DL Filter, Set Filter Length = 24, Set Output Data Rate = 1.25MHz 0x032B First Coefficient, Word 1 0x9688 First Coefficient, Word 2 Word 2 Word 1 0x01BF Second Coefficient, Word 1 Byte 1 Byte 2 Byte 3 1 03 2B 96 88 2 01 BF 18 3C 3 00 15 66 26 4 04 A8 1E 6A 0x0404 Twelfth (Final) Coefficient, Word 1 5 04 5F 2A 96 0x3B5F Final Coefficient, Word 2 6 00 2C 49 C2 7 00 50 E9 F6 8 00 10 DB D8 9 04 2F DE 54 Wait TBD xS for AD7760 to fill remaining unused coefficients with zeros. 10 04 37 44 5A 0x0001 Address of Control Register 11 04 1B 7D 6E 12 04 04 3B 5F Byte 4 What follows is a list of 16-bit words that the user would write to the AD7760 to set up the ADC and download this filter assuming an output data rate of 1.25MHz has already been selected. 0x183C Second Coefficient, Word 2 … … 0x0E6B Checksum 0x0879 Control Reg Data; Set Read Status and maintain filter length and decimation settings. Read contents of Status Register. Check Bit 7 (DL_OK) to determine that the filter was downloaded correctly. Rev. PrN | Page 19 of 22 AD7760 Preliminary Technical Data AD7760 REGISTERS The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the clock divider etc. There are also digital gain, offset and over-range threshold registers. Writing to these registers involves writing the register address first, then a 16-bit data word. Register Addresses, details of individual bits and default values are given here. Table 12. Control Register 1 (Address 0x0001, Default Value 0x001A) MSB DL Filt LSB RD Ovr RD Gain Bit 15 Mnemonic DL Filt1 14 RD Ovr1,2 13 12 11 10 9 RD Gain1,2 RD Off1,2 RD Stat1,2 CAL1 SYNC1 8-5 4 3 FLEN3:0 BYP F3 BYP F1 2-0 DEC2:0 1 2 RD Off RD Stat CAL SYNC FLEN3 FLEN2 FLEN1 FLEN0 BYP F3 BYP F1 DEC2 DEC1 DEC0 Comment Download Filter. Before downloading a user defined filter, this bit must be set. The Filter Length bits must also be set at this time. The write operations that follow will be interpreted as the user coefficients for the FIR filter until all the coefficients and the checksum have been written. Read Overrange. If this bit has been set, the next read operation will output the contents of the Overrange Threshold Register instead of a conversion result. Read Gain. If this bit has been set, the next read operation will output the contents of the digital Gain Register. Read Offset. If this bit has been set, the next read operation will output the contents of the digital Offset Register. Read Status. If this bit has been set, the next read operation will output the contents of the Status Register. Calibration. Setting this bit will initiate an internal calibration routine. This routine will take 14mS with a 20MHz ICLK. Synchronize. Setting this bit will initiate in internal synchronisation routine. Setting this bit simultaneously on multiple devices will synchronize all filters. Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user defined filter is downloaded. Bypass Filter 3. If this bit is a 0, Filter 3 (Programmable FIR) will be bypassed. Bypass Filter 1. If this bit is a 0, Filter 1 will be bypassed. This should only occur when the user requires unfiltered modulator data to be output. Decimation Rate. These bits set the decimation rate of Filter 2. All zeros implies that the filter is bypassed. A value of 1 corresponds to 2x decimation, a value of 2 corresponds to 4x and so on up to the maximum value of 5, corresponding to 32x decimation. Bits 15-9 are all self clearing bits. Only one of the bits 14-11 may be set in any write operation as they all determine the contents of the next read operation Table 13. Control Register 2 (Address 0x0002, Default Value 0x009B) MSB 0 LSB 0 0 Bit 5-4 Mnemonic CDIV1:0 3 2 PD LPWR 1 0 D1PD 0 0 0 0 0 0 0 CDIV1 CDIV0 PD LPWR 1 D1PD Comment Clock Divider Bits. These set the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV[1:0] = 00 divides the MCLK by 2, setting CDIV[1:0] = 01 divides MCLK by 4. If CDIV[1:0] = 10 then the MCLK frequency is equal to the ICLK. CDIV[1:0] = 11 is not allowed. Power Down. Setting this bit powers down the AD7760 reducing the power consumption to TBD µW. Low Power. If this bit is set, the AD7760 is operating in a low power mode. The power consumption is reduced for a 6dB reduction in noise performance. Write a ‘1’ to this bit. Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier. Rev. PrN | Page 20 of 22 Preliminary Technical Data AD7760 Table 14. Status Register (Read Only) MSB LSB PART 1 PART 0 DIE 2 Bit 15,14 13-11 10 9 8 7 Mnemonic PART1:0 DIE2:0 DVALID LPWR OVR DL OK 6 Filter OK 5 4 3 2-0 U Filter BYP F3 BYP F1 DEC2:0 DIE 1 DIE 0 DVALID LPWR OVR DL OK Filter OK U Filter BYP F3 BYP F1 DEC2 DEC1 DEC0 Comment Part Number. These bits will be constant for the AD7760. Die Number. These bits will reflect the current AD7760 die number for identification purposes within a system. Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation. Low Power. If the AD7760 is operating in Low Power Mode, this bit is set to a 1. If the current analog input exceeds the current overrange threshold, this bit will be set. When downloading a user filter to the AD7760, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This generated checksum is compared to the one downloaded. If they match, this bit is set. If a user-defined filter is in use, this bit is set. Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. Bypass Filter 1. If Filter 1 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. Decimation Rate. These correspond to the bits set in Control Register 1. . NON BIT-MAPPED REGISTERS Offset Register (Address 0x0003, Default Value 0x0000) The Offset Register uses 2’s Complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum negative value) correspond to an offset of +0.78125% and -0.78125% respectively. Offset correction is applied after any gain correction. Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately ±25mV. Gain Register (Address 0x0004, Default Value 0xA000) The Gain Register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a full scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of ±80% of VREF Pk-Pk. Over Range Register (Address 0x0005, Default Value 0xCCCC) The Over Range register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of VREF (the maximum permitted analog input voltage) Assuming VREF = 4.096V, the bit will then be set when the input voltage exceeds approximately 6.55v pk-pk differential. Note that the over-range bit is also set immediately if the analog input voltage exceeds 100% of VREF for more than 4 consecutive samples at the modulator rate. Rev. PrN | Page 21 of 22 AD7760 Preliminary Technical Data OUTLINE DIMENSIONS 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) 0.60 (0.024) 0.42 (0.017) 37 36 0.24 (0.009) 7.0 (0.276) BSC SQ PIN 1 INDICATOR 0.25 (0.010) MIN 48 1 6.75 (0.266) BSC SQ TOP VIEW 5.25 (0.207) 5.10 (0.201) SQ 4.95 (0.195) BOTTOM VIEW 25 24 0.50 (0.020) 0.40 (0.016) 0.30 (0.012) 12 13 5.5 (0.217) REF 0.70 (0.028) MAX 12°MAX 0.65 (0.026) NOM 0.90 (0.035) MAX 0.05 (0.002) 0.85 (0.033) NOM 0.01 (0.0004) 0.0 (0.0) 0.30 (0.012) 0.50 (0.020) 0.20 (0.008) REF 0.23 (0.009) BSC 0.18 (0.007) Figure 21. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)—Dimensions shown in millimeters 1.60 (0.063) MAX 0.15(0.006) 0.05(0.002) 0.60 ± 0.15 (0.024 ± 0.006) 12o TYP 12.0(0.47) BSC 10.0(0.39) BSC 64 49 48 1 SEATING PLANE 6.0(0.235) BSC TOP VIEW 33 32 16 0o 3.5o ± 3.5o 17 0.50 (0.02) BSC 0.22 ± 0.05 (0.0087 ± 0.002) Figure 22. 64-Lead Thin Quad Flat Pack (Exposed Paddle) [TQFP] (SV-64)—Dimensions shown in millimeters ORDERING GUIDE Model AD7760BCP AD7760BSV Temperature Range –40°C to +85°C –40°C to +85°C Package Description Lead Frame Chip Scale Package Thin Quad Flat Pack, Exposed Paddle © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. PR04975-0-6/04(PrN) Rev. PrN | Page 22 of 22 Package Option CP-48 SV-64