PERICOM PI6C185-01B

PI6C185-01B
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Precision 1-5 Clock Buffer
Features
Description
• High-speed, low-noise non-inverting 1-5 buffer
The PI6C185-01B, a high-speed low-noise 1-5 non-inverting buffer
designed for SDRAM clock buffer applications, is intended to be
used with the PI6C10X clock generator for Intel Architecture-based
Mobile systems.
• Switching speed up to 140 MHz
• Supports up to two SODIMMs
At power up, all SDRAM outputs are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the five output drivers.
• Low skew (<250ps) between any two output clocks
• I2C Serial Configuration interface
• Multiple VDD, VSS pins for noise reduction
Note:
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
• 3.3V power supply voltage
• 16-pin TSSOP (L) and QSOP (Q) packages
Block Diagram
Pin Configuration
SDRAM0
Vdd
SDRAM0
SDRAM1
Vss
BUF_IN
Vdd
SDATA
SCLK
SDRAM1
BUF_IN
SDRAM2
SDRAM3
1
2
3
4
5
6
7
8
16-Pin
L, Q
16
15
14
13
12
11
10
9
Vdd
SDRAM4
Vss
Vdd
SDRAM3
SDRAM2
Vss
Vss
SDRAM4
SDATA
I2C
SCLOCK
I/O
1
PS8466
05/03/00
PI6C185-01B
Precision 1-5 Clock Buffer
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Pin Description
Pin
Signal
Type
Qty
De s cription
2,3,11,12,15
SDRAM [0.4]
I
5
Buffered Clock Outputs
5
BUF_IN
I
1
Clock Buffer Input
7
SDATA
I/O
1
Serial Data for I2C interface, internal pull- up
8
SCLK
I
1
Serial Clock for I2C interface, internal pull- up
1,6,13,16
VDD
Power
4
3.3V Power Supply
4,9,10,14
VSS
Ground
4
Ground
PI6C185-01B I2C Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
PI6C185-01B Serial Configuration Map
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
Bit 7
12
Bit 6
D e s cription
Bit
Pin#
D e s cription
SDRAM3 (Active/Inactive)
Bit 7
-
NC (Initialize to 0)
11
SDRAM2 (Active/Inactive)
Bit 6
-
NC (Initialize to 0)
Bit 5
-
NC (Initialize to 0)
Bit 5
-
NC (Initialize to 0)
Bit 4
-
NC (Initialize to 0)
Bit 4
-
NC (Initialize to 0)
Bit 3
-
NC (Initialize to 0)
Bit 3
-
NC (Initialize to 0)
Bit 2
-
NC (Initialize to 0)
Bit 2
-
NC (Initialize to 0)
Bit 1
3
SDRAM1 (Active/Inactive)
Bit 1
-
NC (Initialize to 0)
Bit 0
2
SDRAM0 (Active/Inactive)
Bit 0
15
SDRAM4 (Active/Inactive)
Note:
Inactive means outputs are held LOW and
are disabled from switching
2
PS8466
05/03/00
PI6C185-01B
Precision 1-5 Clock Buffer
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2-Wire I2C Control
1
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to addressed device). If the device’s
own address is detected, PI6C185-01B generates an acknowledge
by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condition
is detected.
The PI6C185-01B, a slave receiver device, cannot be read back.
Sub addressing is not supported. To change one of the control
bytes, all preceding bytes must be sent
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving
device.
2
3
Following acknowledgement of the address byte (0D2H), two
more bytes must be sent:
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
4
1. “Command Code” byte & 2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
5
Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
6
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Storage Temperature ...................................... –65°C to +150°C
Ambient Temperature with Power Applied ........ –0°C to +70°C
3.3V Supply Voltage to Ground Potential ........... –0.5V to +4.6V
DC Input Voltage .............................................. –0.5V to +4.6V
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol
Parame te r
Te s t Condition
M in.
Typ.
IDD
Supply Current
BUF_IN = 0 MHz
IDD
Supply Current
BUF_IN = 66.66 MHz
70
IDD
Supply Current
BUF_IN = 100.0 MHz
120
IDD
Supply Current
BUF_IN = 133.3 MHz
200
M ax.
7
8
9
Units
3
10
mA
11
12
13
14
15
3
PS8466
05/03/00
PI6C185-01B
Precision 1-5 Clock Buffer
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DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C –70°C)
Symbol
Parame te r
Condition
M in.
M ax.
Units
VDD
2.0
VDD +0.3
VSS –0.3
0.8
0 < VIN < VDD
–5
+5
2.4
Input Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
IIL
Input Leakage Current
V
µA
VDD = 3.3V ±5%
VOH
Output High Voltage
IOH = - 1mA
VOL
Output Low Voltage
IOL = 1mA
CIN
Input Pin Capacitance
5
COUT
Output pins Capacitance
6
LPIN
Pin Inductance
7
nH
70
ºC
TA
Ambient Temperature
V
0.4
No Airflow
0
pF
SDRAM Clock Buffer Operating Specification
Symbol
Parame te r
Condition
IO H M IN
Pull- up current
VO U T = 2.0V
IO H M A X
Pull- up current
VO U T = 3.135V
IO LM IN
Pull- down current
VO U T = 1.0V
IO LM A X
Pull- down current
VO U T = 0.4V
M in.
Typ. M ax. Units
–40
36
mA
40
38
tR H SDRAM O utput rise edge rate SDRAM only 3.3V ±5% @0.4V- 2.4V
1.5
tF H SDRAM O utput fall edge rate SDRAM only
1.5
3.3V ±5% @2.4V- 0.4V
4
V/ns
4
AC Timing
Symbol
Parame te r
66 M Hz
100 M Hz
133 M Hz
M in.
M ax.
M in.
M ax.
M in.
M ax.
15.5
10.0
10.5
7.5
7.8
Units
tSDKP
SDRAM CLK period
15.0
tSDKH
SDRAM CLK high time
5.6
3.3
1.0
tSDKL
SDRAM CLK low time
5.3
3.1
1.0
tSDRISE
SDRAM CLK rise time
1.5
4.0
1.5
4.0
1.5
4.0
tSDFALL
SDRAM CLK fall time
1.5
4.0
1.5
4.0
1.5
4.0
tPLH
SDRAM Buffer LH prop delay
1.0
5.5
1.0
5.5
1.0
5.5
tPHL
SDRAM Buffer HL prop delay
1.0
5.5
1.0
5.5
1.0
5.5
tPZL,tPZH
SDRAM Buffer Enable delay
1.0
8.0
1.0
8.0
1.0
8.0
tPLZ,tPHZ
SDRAM Buffer Disable delay
1.0
8.0
1.0
8.0
1.0
8.0
Duty Cycle
Measured at 1.5V
45
55
45
55
45
55
%
tSDSKW
SDRAM Output to Output Skew
250
ps
250
250
4
ns
V/ns
ns
PS8466
05/03/00
PI6C185-01B
Precision 1-5 Clock Buffer
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1
Test
Output
Point
Buffer
2
Test Load
3
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
4
1.5
0.4
5
tSDKL
tSDRISE
tSDFALL
6
Input
1.5V
1.5V
Waveform
tplh
7
tphl
Output
1.5V
Waveform
8
1.5V
9
Figure 1. Clock Waveforms
10
Minimum and Maximum Expected Capacitive Loads
Clock
SDRAM
M in Load M ax Load
15
20
Units
pF
Note s
SDRAM DIMM Specification
11
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
12
13
Design Guidelines to Reduce EMI
14
1. Place RS series resistors and CI capacitors as close as possible to the respective clock pins. Typical
value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise
and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
15
PS8466
05/03/00
PI6C185-01B
Precision 1-5 Clock Buffer
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PI6C185-01B
100/66 MHz
Clock from
Chipset
SDRAM
RS
5
SDRAM
DIMM
Spec.
CI
Figure 2. Design Guidelines
16-Pin TSSOP (L) Package
16-Pin QSOP (Q) Package
16
16
.150
.157
.169
.177
3.81
3.99
.015 x 45° 0.38
4.3
4.5
1
1
.193
.201
4.9
5.1
.004
.008
.047
max.
1.20
.007
.012
.002
.006
0.41 .016
1.27 .050
.008
0.203 REF
0.45 .018
0.75 .030
SEATING
PLANE
.0256
BSC
0.65
0.09
0.20
0.178
0.254
.007
.010
.189
.197
4.80
5.00
.228
.244
5.79
6.19
.053 1.35
.069 1.75
.252
BSC
6.4
SEATING
PLANE
0.05
0.15
.025
BSC
0.635
0.19
0.30
.008
.012
0.203
0.305
.004 0.101
.010 0.254
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
P/N
De s cription
PI6C185- 01BL
TSSOP Package
PI6C185- 01BQ
QSOP Package
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
6
PS8466
05/03/00