MultiG G E N™ GF9102A Decimating/Interpolating Digital Filter DATA SHEET FEATURES DEVICE DESCRIPTION • improved performance over TMC2242 in applications not requiring 1:1 low pass filtering The GF9102A is a linear phase FIR digital filter that is usable in a variety of video signal processing applications. The device contains three separate fixed coefficient filters and can be operated in three basic modes: 53 tap low pass filter, 9 tap chroma bandpass filter or 21 tap chroma bandpass filter. • low power (60mA typical at ƒ = 20MHz) • 40 MHz maximum clock rate • single device exceeds CCIR 601 lowpass filter requirements • true unity gain (0.0 dB) at DC • reduced output ringing with constant input in interpolation mode • built-in TRS code protection • 12 bit inputs and 16 bit outputs in 2's complement signed or unsigned formats • user-selectable 8 to 16 bit output rounding • can also be operated as a 9 or 21 tap chroma bandpass filter under user control • single +5 V power supply • three state outputs APPLICATIONS • CCIR 601-compliant oversampling video A/D and D/A conversion • 2:1 interpolation and decimation • 4:2:2 to 4:4:4 format conversion • Chroma bandpass filtering ORDERING INFORMATION Part Number Package Type Temperature Range GF9102ACPM 44 Pin PLCC 0° to 70° C GF9102ACTM 44 Pin PLCC Tape 0° to 70° C CLK DEC SYNC INT INPUT PROCESSING UNIT Revision Date: February 1996 When used as a decimating post-filter with a double speed oversampling analog-digital converter, the device greatly reduces the cost and complexity of the associated analog anti-aliasing pre-filter. In a similar fashion, when used as an interpolating pre-filter with a double speed oversampling digitalanalog converter, the GF9102A simplifies the analog reconstruction post-filter. The GF9102A also exceeds the requirements for conversion between 4:2:2 and 4:4:4 signal formats. For chroma filtering applications, the GF9102A can be operated as a 9 or 21 tap bandpass filter by selecting the appropriate operating mode. The GF9102A is packaged in a 44 pin PLCC and is pin compatible with the TMC2242. The device operates with a single +5 V supply. RND2..0 TCO SO3..0 OUTPUT FORMAT TIMING CONTROLS DATA IN SI11..0 In the 53 tap low pass filter mode, the GF9102A can replace the TMC2242 in all applications, except those requiring 1:1 low pass filtering, for improved performance and full CCIR 601 compatibility. Specific improvements include true unity gain at DC, 12.4 dB attenuation at ƒs/4 with a single device, reduced output ringing with constant input in interpolate mode, support for signed and unsigned data formats, rounding to 10 and 8 bit CCIR 601 data formats, masking of serial digital TRS codes in the data stream, and elimination of the non-saturated-type overflow condition. The device can be operated in both TMC2242 compatible modes and in GF9102A enhanced modes. BPF1 BPF2 53 TAP LPF M U X OUTPUT PROCESSING UNIT FUNCTIONAL BLOCK DIAGRAM DATA OUT SO15..0 OE Document No. 521 - 26 - 02 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946 Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839 PIN DESCRIPTION SYMBOL PIN NO. TYPE CLK 42 I SYNC 43 I DESCRIPTION System Clock. TTL input. All timing specifications are referenced to the rising edge of clock. Data Synchronization. TTL input with internal pull-up. This input is used to synchronize the incoming data with the GF9102A by holding SYNC high on clock N and low on clock N+1 when the first data word is presented to the input SI11..0 . SYNC may be held low until resynchronization is desired, or it may be clocked at half the clock rate. SI11..0 40, 37, 36, 35, I Input Data Port. TTL inputs with internal pull-downs. Data is presented to this registered 12-bit 34, 33, 32, 31, data input port. This port can be programmed as two’s complement signed or unsigned binary 30, 27, 26, 25 format. See the following section on input data format. Data is latched internally on every clock in decimate mode, and on every other clock in interpolate mode. SI11 is the MSB. TCO 2 I Two’s Complement Output Format Control. TTL input with internal pull-down. When TCO is high, output data is presented in two’s complement format. When TCO is low, the output is inverted offset binary, obtained by inverting bits SO14 through SO0, leaving SO15 unchanged. INT 44 I Interpolate. Active low TTL input with internal pull-up. When the interpolate control is low, data is input at full clock speed and the chip inserts zeros between samples, padding the input to match the output rate. The GF9102A then interpolates between these alternate input data points to achieve full output data rate. DEC 1 I Decimate. Active low TTL input with internal pull-down. When the decimate control is low, the output register is driven at half system clock speed, decimating the output data stream. When DEC and INT are low, the GF9102A will be programmed as a 21 tap or 9 tap bandpass filter depending on the state of the SYNC input. See Operation Mode Control below for more detail. RND2..0 22, 23, 24 I Output Rounding Control. TTL inputs with internal pull-down. These pins set the position of the effective least significant bit of the output port by adding a rounding bit to the next lower internal bit and zeroing all outputs below the rounding bit. Additional rounding functions are added with the SO 1 control input. See Table 6. SO15..0 4, 5, 6, 7, O Output Data Port. TTL outputs (SO3..0 are bi-directional pins with an internal pull-down). The 8, 9, 10, 11, filtered result is available at this registered 16-bit output port, half LSB rounded as determined by 14, 15, 16, 17, the rounding control word RND 2..0. SO15 is the MSB. The SO3..0 control inputs enable additional 18, 19, 20, 21 formatting and rounding features as described below. SO3..0 18, 19, 20, 21 I/O Output Data Port. TTL bi-directional pins with internal pull-down. The SO0 control input enables the unsigned input and output format. The SO1 control input enables 8-bit rounding or CCIR 601 8-bit and 10-bit modes of operation. SO3..2 are reserved for future functions. OE 3 I Output Enable. Active low TTL input with internal pull-up. When this asynchronous input is high, the output data port is in the high impedance state. VDD 13, 29, 38 GND 12, 28, 39, 41 521 - 26 - 02 +5 V ± 5% power supply. Ground 2 SO13 SO14 6 SO15 OE TCO DEC INT SYNC CLK GND SI11 4 3 2 1 44 43 42 41 40 5 SO12 7 39 GND SO11 8 38 VDD SO10 9 37 SI10 SO9 10 36 SI9 SO8 11 35 SI8 GND 12 34 SI7 VDD 13 33 SI6 SO7 14 32 SI5 SO6 15 31 SI4 SO5 16 30 SI3 SO4 17 29 VDD GF9102A TOP VIEW 18 19 20 21 22 23 SO3 SO2 SO1 SO0 RND2 24 RND1 RND0 25 26 27 28 SI0 SI1 SI2 GND Fig. 1 GF9102A Pin Connections LOWPASS FILTER CHARACTERISTICS at SAMPLING FREQUENCY OF 27MHz PARAMETER VALUE Filter Order 53 < ± 0.02 dB Pass Band Ripple Pass Band Edge 5.75 MHz DC Gain 0.00 dB 6.75 MHz (ƒs/4) Attenuation 12.4 dB Minimum Stop Band Attenuation >58 dB Stop Band Edge 7.4 MHz 3 521 - 26 - 02 0 2 4 6 8 10 12 14 0 0 0 CCIR601 CCIR601 GF9102 GF9102A -10 -10 3 4 5 3 4 5 6 0.025 MAGNITUDE (dB) -20 -30 MAGNITUDE (dB) 2 0.0375 -20 -30 dB 1 0.05 -40 -40 -50 -50 -60 -60 0.0125 0 0 -0.0125 -0.025 CCIR601 GF9102A -0.0375 -70 -70 CCIR601 CCIR601 GF9102 -0.05 -80 -80 0 2 4 6 8 10 12 14 0 1 2 FREQUENCY (MHz) 6 FREQUENCY (MHz) Fig. 2 Frequency Response of the Decimation/Interpolation Filter (Sampling at 27 MHz) Fig. 3 Frequency Response of the Decimation/Interpolation Filter Passband (Sampling at 27 MHz) 0 110 0 6 % FULL SCALE 80 70 60 50 40 30 20 10 -20 -15 -40 -36 -60 -58 -79 -80 21 TAP BPF 21 TAP BPF 9 TAP BPF 9 TAP BPF 0 -10 10 20 30 40 50 60 70 80 0 3 freq enc (MH ) 4 5 6 7 Fig. 4 Step Response of Decimation Filter Fig. 5 Frequency Response of the Bandpass Filter (Sampling at 14.31818 MHz) -1 5 -2 4 -3 3 -4 2 -5 1 -6 0 -7 -1 -8 -2 21 21 TAP BPF TAP BPF 9 TAP BPF 9 TAP BPF -9 0 MAGNITUDE (dB) 21 TAP BPF 6 -3 2.5 3 3.5 4 4.5 5 0 6.02 -0.005 6.015 -0.01 6.01 -0.015 6.005 TAP BPF 2121TAP BPF 9 TAP BPF 9 TAP BPF -0.02 2.579545 -4 2 5.5 3.079545 3.579545 frequency (MHz) 4.079545 4.579545 6.00 FREQUENCY (MHz) FREQUENCY (MHz) Fig. 7 Frequency Response of the Bandpass Filter Passband (Sampling at 14.31818 MHz) Fig. 6 Frequency Response of the Bandpass Filter Transition Band (Sampling at 14.31818 MHz) 521 - 26 - 02 2 FREQUENCY (MHz) 0 -10 1.5 1 SAMPLE NUMBER MAGNITUDE (dB) 9 TAP BPF MAGNITUDE (dB) 21 TAP BPF -100 -100 0 4 MAGNITUDE (dB) 9 TAP BPF MAGNITUDE (dB) 21 TAP BPF 90 MAGNITUDE (dB) 9 TAP BPF 100 Table 1: Input Data Format and Bit Weighting Two’s complement signed binary, data range: -1 ≤ SI < 1 SI 11 SI 10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 SI2 SI1 SI0 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 Unsigned binary, data range: 0 ≤ SI < 256 SI 11 SI 10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 SI2 SI1 SI0 27 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 Table 2: Output Data Format and Bit Weighting Two’s complement signed binary, data range: -1 ≤ SO < 1 SO15 SO 14 SO 13 -20 2-1 2-2 SO12 SO11 2-3 SO 10 SO9 SO8 SO7 SO6 SO5 SO4 SO 3 SO2 SO1 SO0 2-5 2-6 2-7 2-8 2-9 2 -10 2 -11 2-12 2-13 2-14 2-15 SO 10 SO9 SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-4 Unsigned binary, data range: 0 ≤ SO < 256 SO 15 SO 14 SO13 27 26 25 SO12 SO11 24 23 Table 3: Operation Mode Control DEC INT Sync Mode Description Device Latency Notes 0 0 0 Bandpass1 21 Tap Bandpass 18 Clock Cycles 2 0 0 1 Bandpass2 9 Tap Bandpass Gain=2 18 Clock Cycles 2 0 1 Sync Decimating Gain=1 33 Clock Cycles 1 1 0 Sync Interpolating Gain=0.5 33 Clock Cycles 1 1 0 Sync Interpolating Gain=1 for unsigned input3 33 Clock Cycles 2 1 1 Sync Pass through Top 12 bit pass through 33 Clock Cycles 2 Notes: 1. This operating mode is compatible with TMC2242. 2. This is an enhanced operating mode of the GF9102A. 3. This mode is invoked using the SO0 pin. See I/O Format control below. Table 4: I/O Format Control RND2..0 RND = 000 SO03 TCO Input5 Output5 Output 0 Signed I_Unsigned 1 Signed Signed Signed I_Unsigned Notes 1 RND ≠ 000 0 0 1 Signed Signed RND ≠ 000 1 0 Unsigned4 Unsigned 2 1 Unsigned Signed Limit output up to 15 bits Notes: 1 1. This operating mode is compatible with TMC2242. 2. This is an enhanced operating mode of the GF9102A. 3. SO 0, the LSB of the output is a bi-directional pad with a large pull-down resistor. This pin does not have to be connected. 4. Application notes for the TMC2242 suggest grounding the MSB of the input if the input data is unsigned as When this pin is not connected the GF9102A defaults to a mode compatible with the TMC2242. in most A/D converters. This method limits the input to 11 bits and leads to potential output non-saturated type overflow since the MSB of the output is ignored. 5. Signed: two’s complement binary data. I_unsigned: invert all bits in signed data except for the MSB; also called inverted offset binary. Unsigned: invert MSB of signed data; also called offset binary. 5 521 - 26 - 02 Table 5: Output Rounding Control RND2..0 SO13 No. of Output Bits 000 Output 16 Rounding to 16 bit 1 001 Output 15 Rounding to 15 bit 1 010 0 14 Rounding to 14 bit 1 011 0 13 Rounding to 13 bit 1 100 0 12 Rounding to 12 bit 1 101 0 11 Rounding to 11 bit 1 110 0 10 Rounding to 10 bit 1 111 0 9 Rounding to 9 bit 1 100 1 8 Rounding to 8 bit 2 110 1 10 CCIR 601 10 bit data format4 2 8 CCIR 601 8 bit data format5 2 101 Notes: 1 Description Notes 1. This operating mode is compatible with TMC2242. 2. This is an enhanced operating mode of the GF9102A. 3. SO1, the second LSB of the output is a bi-directional pad with a large pull-down resistor. This pin does not have to be connected. When this pin is not connected the GF9102A defaults to a mode compatible with the TMC2242. . 4. CCIR 601 10 bit data format range from Hex 004 to 3FB. 5. CCIR 601 8 bit data format range from Hex 01 to FE. Table 6: Extra Control Input Pins using the Four Least Significant Bi-directional Output Pads SO3..0 Conditions to allow Output Pad1 Function Notes Control Inputs RND ≠ 000 SO0 = 1 Unsigned input 2 RND = 100 SO1 = 1 8 bit output rounding 2 RND = 110 SO1 = 1 CCIR 601 10 bit data format 2 RND = 101 SO1 = 1 CCIR 601 8 bit data format 2 RND = 1XX SO2 Reserved RND = 1XX SO3 Reserved Notes: 1. SO3..0 pins are bi-directional with a large pull-down resistor. These pins do not have to be connected. When these pins are not connected the GF9102A defaults to a mode compatible with the TMC2242. 2. This is an enhanced operating mode of the GF9102A. 521 - 26 - 02 6 Table 7: Input Step Response INPUT OUTPUT DECIMATION 55 cycles INTERPOLATION INT = 1, DEC = 0 SYNC INT = 0, DEC = 1 SYNC XXX XXX 1 XXX 1 400 XX 0 XX 0 400 XX 0 XX 0 • • • • • • • • • • • • • • • 400 4000 0 2000 0 400 4000 0 2000 0 000 4000 0 2000 0 • • • • • • • • • • • • • • • 000 44E2 0 244A 0 000 44E2 0 1F6A 0 000 2F6A 0 1000 0 000 2F6A 0 0096 0 000 FC4C 0 FBB6 0 000 FC4C 0 FF68 0 • • • • • • • • • • • • • • • 000 0000 0 0000 0 Maximum Ringing Minimum Ringing Steady State NOTE: TCO = 1 7 521 - 26 - 02 ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage CAUTION ELECTROSTATIC -0.3 to +7.0V Input Voltage Range SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION 0.5 to (VDD + 0.5)V 0°C ≤ TA ≤ 70°C Operating Temperature Range -65°C ≤ TS ≤ 150°C Storage Temperature Range Lead Temperature (soldering, 10 sec) 260°C ELECTRICAL CHARACTERISTICS Conditions: V DD = 5 V, T A = 0˚ to 70 ˚C, RL = 150 Ω to GND and 144 Ω AC coupled unless otherwise shown. PARAMETER SYMBOL Supply Voltage VDD Supply Current Quiescent IDDQ Supply Current Unloaded I DDU Input Voltage, Logic Low CONDITIONS MIN TYP MAX UNITS volts 4.75 5 5.25 VDD = Max, VIN = 0V - 5 10 mA VDD = Max, OE = VDD , ƒ = 20 MHz - 60 1 95 mA V IL - - 0.8 volts Input Voltage, Logic High V IH 2.0 - - volts Switching Threshold VT TTL - 1.5 - volts Input Current: (TTL Inputs) IIN VIN = VDD OR VSS -10 ±1 10 µA Inputs with Pulldown Resistors VIN = VDD 35 115 222 µA Inputs with Pullup Resistors VIN = VSS -35 -115 -214 µA Ouput Voltage, Logic Low VOL VDD = Min, I OL = 6mA - 0.2 0.4 volts Ouput Voltage, Logic High VOH VDD = Min, I OH = -6mA 2.4 4.5 - volts Hi-Z Output Leakage Current I OZ VDD = Max, OE = 1 -10 ±1 10 µA Short Circuit Output Current I OS VDD = Max, output high one pin to - - 210 mA ground, one second duration max CIN TA = 25°C, ƒ = 1MHz - - 10 pF COUT TA = 25°C, ƒ = 1MHz - - 10 pF 0 - 70 °C Input Capacitance Output Capacitance Ambient Temperature, Still Air TA NOTE 1: Supply current may fluctuate with changes in data pattern. VDD VDD n SUBSTRATE n SUBSTRATE p D1 D1 p p+ p+ CONTROL INPUT n+ n+ D2 n n D2 p WELL p WELL GND GND Fig. 8a Equivalent Input Circuit 521 - 26 - 02 Fig. 8b Equivalent Output Circuit 8 SWITCHING CHARACTERISTICS, TA from 0°C NAME to 70°C unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS tD Output delay VDD=Min, CL=25 pF - - 15 ns tOH Output hold VDD=Max, CL=25 pF 3 - - ns tEN Output enable VDD=Min, CL=25 pF - - 15 ns tDIS Output disable VDD=Min, CL=25 pF - - 15 ns tCY Cycle time 25 - - ns tPWL Clock pulse width low 10 - - ns tPWH Clock pulse width high 10 - - ns tS Input setup time 6 - - ns tH Input hold time 0 - - ns 0 1 2 3 4 5 6 CLK tPWH 1 SI11..0 2 tPWL tCY 3 4 5 6 tH tS SYNC 34 35 36 37 38 39 40 CLK tOH tD SO15..0 1 3 5 7 tDIS 7 tEN OE Fig. 9 Timing Diagram - Decimation INT = 1, DEC = 0, SYNC = SYNC 9 521 - 26 - 02 0 1 2 3 4 5 6 CLK tPWH tPWL 1 3 5 SI11..0 tS tH SYNC 34 35 36 37 38 39 CLK tD tOH 1 SO15..0 2 3 4 5 6 tDIS tEN OE Fig. 10 Timing Diagram - Interpolation INT = 0, DEC = 1, SYNC = SYNC 0 1 2 3 4 5 6 CLK SI11..0 19 tPWH tH tS tPWL tCY 1 2 3 4 5 20 21 22 23 24 6 25 CLK tOH tD SO15..0 1 2 3 4 5 6 7 tDIS OE Fig. 11 Timing Diagram - Decimation INT = 0, DEC = 0, SYNC = 0 or SYNC = 1 521 - 26 - 02 10 7 tEN 0 1 2 3 4 5 6 CLK tPWH 1 SI11..0 tS tPWL tCY 2 3 4 5 6 tH SYNC 34 35 36 37 38 39 40 CLK tOH tD SO15..0 1 2 3 4 5 6 7 tDIS 7 tEN OE Fig. 12 Timing Diagram - Decimation INT = 1, DEC = 1, SYNC = SYNC tEN OE tDIS 0.5V THREE STATE OUTPUTS HIGH IMPEDANCE 2.0V 0.8V 0.5V Fig. 13 Threshold Levels for Three State Measurement Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright January 1995 Gennum Corporation. All rights reserved. Printed in Canada. 11 521 - 26 - 02