SN74LS251 8-Input Multiplexer with 3-State Outputs The TTL/MSI SN74LS251 is a high speed 8-Input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS251 can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. • • • • • http://onsemi.com LOW POWER SCHOTTKY Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Inverting and Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 2.6 mA IOL Output Current – Low 24 mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS251N 16 Pin DIP 2000 Units/Box SN74LS251D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS251/D SN74LS251 CONNECTION DIAGRAM DIP (TOP VIEW) VCC I4 I5 I6 I7 S0 S1 S2 16 15 14 13 12 11 10 9 1 I3 2 I2 3 I1 4 I0 5 Z 6 Z 7 E0 8 GND LOADING (Note a) PIN NAMES S0 – S2 E0 I0 – I7 Z Z Select Inputs Output Enable (Active LOW) Inputs Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 65 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 15 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC DIAGRAM I0 S2 S1 S0 E1 9 I1 4 I2 3 I3 2 I4 1 I5 15 10 11 7 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 5 Z http://onsemi.com 2 I6 14 6 Z I7 13 12 SN74LS251 FUNCTIONAL DESCRIPTION The LS251 is a logical implementation of a single pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input (EO) is active LOW. When it is activated, the logic function provided at the output is: When the Output Enable is HIGH, both outputs are in the high impedance (high Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltage. Z = EO ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ Z = E O ⋅ S 2 + I 3 ⋅ S 0 ⋅ S 1 ⋅ S 2 + I4 ⋅ S 0 ⋅ S 1 ⋅ S 2 + I5 ⋅ S 0 ⋅ Z = EO ⋅ S1 ⋅ S2 + I6 ⋅ S0 ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2). TRUTH TABLE E0 S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Z Z H L L L L L L L L L L L L L L L L X L L L L L L L L H H H H H H H H X L L L L H H H H L L L L H H H H X L L H H L L H H L L H H L L H H X L H X X X X X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X L H (Z) H L H L H L H L H L H L H L H L (Z) L H L H L H L H L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High impedance (Off) http://onsemi.com 3 SN74LS251 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage Min Typ Max 2.0 0.8 – 0.65 2.4 – 1.5 3.1 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 12 mA 0.35 0.5 V IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current LOW – 20 µA VCC = MAX, VOUT = 0.4 V 20 IIH Input HIGH Current µA VCC = MAX, VIN = 2.7 V IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current – 30 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 130 mA VCC = MAX 10 mA VCC = MAX, VE = 0 V 12 mA VCC = MAX, VE = 4.5 V Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH tPHL Propagation Delay, Select to Z Output 20 21 33 33 ns Figure 1 tPLH tPHL Propagation Delay, Select to Z Output 29 28 45 45 ns Figure 2 tPLH tPHL Propagation Delay, Data to Z Output 10 9.0 15 15 ns Figure 1 tPLH tPHL Propagation Delay, Data to Z Output 17 18 28 28 ns Figures 2 tPZH tPZL Output Enable Time to Z Output 17 24 27 40 ns Figures 4, 5 tPZH tPZL Output Enable Time to Z Output 30 26 45 40 ns Figures 3, 5 tPHZ tPLZ Output Disable Time to Z Output 37 15 55 25 ns Figures 3, 5 tPHZ tPLZ Output Disable Time to Z Output 30 15 45 25 ns http://onsemi.com 4 Figures 4, 5 CL = 15 pF, RL = 2.0 kΩ CL = 5.0 pF, RL = 667 kΩ SN74LS251 3-STATE AC WAVEFORMS VIN 1.3 V 1.3 V tPLH VOUT VIN 1.3 V tPHL tPLH 1.3 V 1.3 V tPHL 1.3 V 1.3 V VOUT Figure 1. VE Figure 2. 1.3 V VE 1.3 V tPZL VOUT 1.3 V 1.3 V tPZH tPLZ ≈ 1.3 V 1.3 V 1.3 V tPHZ VOUT ≥ VOH ≈ 1.3 V 1.3 V VOL 0.5 V 0.5 V Figure 3. Figure 4. 0.5 V AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SW1 TO OUTPUT UNDER TEST 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 5. http://onsemi.com 5 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed SN74LS251 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SN74LS251 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS251 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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