19-1072; Rev 2; 5/98 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ____________________________Features ♦ 4-Channel Single-Ended or 2-Channel Differential Inputs ♦ Single +2.7V to +5.25V Operation ♦ Internal 2.5V Reference (MAX1248) ♦ Low Power: 1.2mA (133ksps, +3V supply) 54µA (1ksps, +3V supply) 1µA (power-down mode) ♦ SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface ♦ Software-Configurable Unipolar or Bipolar Inputs ♦ 16-Pin QSOP Package (same area as 8-pin SO) ________________________Applications Portable Data Logging Medical Instruments Pen Digitizers _____________Ordering Information TEMP. RANGE MAX1248ACPE 0°C to +70°C 16 Plastic DIP ±1/2 MAX1248BCPE MAX1248ACEE MAX1248BCEE 0°C to +70°C 0°C to +70°C 0°C to +70°C 16 Plastic DIP 16 QSOP 16 QSOP ±1 ±1/2 ±1 PIN-PACKAGE Ordering Information continued at end of data sheet. factory for availability of alternate surface-mount packages. † Contact __________Typical Operating Circuit Data Acquisition Battery-Powered Instruments System Supervision +3V CH0 0V TO +2.5V ANALOG INPUTS VDD DGND C3 0.1µF VDD MAX1248 AGND CH3 SCLK VREF C1 4.7µF DIN DOUT REFADJ CPU COM CS Pin Configuration appears at end of data sheet. I/O SCK (SK) MOSI (SO) MISO (SI) SSTRB SHDN SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. INL (LSB) PART† VSS C2 0.01µF ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX1248/MAX1249 _______________General Description The MAX1248/MAX1249 10-bit data-acquisition systems combine a 4-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. They operate from a single +2.7V to +5.25V supply, and their analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPI™/ QSPI™ and MICROWIRE™ devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1248/MAX1249 use either the internal clock or an external serial-interface clock to perform successiveapproximation analog-to-digital conversions. The MAX1248 has an internal 2.5V reference, while the MAX1249 requires an external reference. Both parts have a reference-buffer amplifier with a ±1.5% voltage adjustment range. These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface automatically powers up the MAX1248/MAX1249, and the quick turn-on time allows them to be shut down between all conversions. This technique can cut supply current to under 60µA at reduced sampling rates. The MAX1248/MAX1249 are available in a 16-pin DIP and a very small QSOP that occupies the same board area as an 8-pin SO. For 8-channel versions of these devices, see the MAX148/MAX149 data sheet. MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND .............................................. -0.3V to +6V AGND to DGND.................................................... -0.3V to +0.3V CH0–CH3, COM to AGND, DGND ............ -0.3V to (VDD + 0.3V) VREF to AGND........................................... -0.3V to (VDD + 0.3V) Digital Inputs to DGND............................................ -0.3V to +6V Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW QSOP (derate 8.30mW/°C above +70°C) ................... 667mW CERDIP (derate 10.00mW/°C above +70°C) .............. 800mW Operating Temperature Ranges MAX1248_C_E/MAX1249_C_E .......................... 0°C to +70°C MAX1248_E_E/MAX1249_E_E........................ -40°C to +85°C MAX1248_MJE/MAX1249_MJE .................... -55°C to +125°C Storage Temperature Range ............................ -60°C to +150°C Lead Temperature (soldering, 10sec) ............................ +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS DC ACCURACY (Note 1) Resolution MIN TYP MAX 10 Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Bits MAX124_A MAX124_B No missing codes over temperature ±0.5 ±1.0 ±1 MAX124_A MAX124_B MAX124_A MAX124_B Offset Error Gain Error (Note 3) UNITS ±1 ±2 ±1 ±2 LSB LSB LSB LSB Gain Temperature Coefficient ±0.25 ppm/°C Channel-to-Channel Offset Matching ±0.05 LSB DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode) Signal-to-Noise + Distortion Ratio SINAD 66 dB Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Up to the 5th harmonic -70 dB 70 dB Channel-to-Channel Crosstalk 65kHz, 2.500Vp-p (Note 4) -75 dB Small-Signal Bandwidth -3dB rolloff 2.25 MHz 1.0 MHz Full-Power Bandwidth CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time tCONV Internal clock, SHDN = FLOAT 5.5 7.5 Internal clock, SHDN = VDD 35 65 µs External clock = 2MHz, 12 clocks/conversion 6 1.5 µs tACQ Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency 2 SHDN = FLOAT SHDN = VDD Data transfer only 30 ns <50 ps 1.8 0.225 MHz 0.1 0 _______________________________________________________________________________________ 2.0 2.0 MHz +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 (VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL ANALOG/COM INPUTS Input Voltage Range, SingleEnded and Differential (Note 6) CONDITIONS MIN Unipolar, COM = 0V Bipolar, COM = VREF / 2 On/off leakage current, VCH_ = 0V or VDD Multiplexer Leakage Current TYP MAX 0 to VREF ±VREF / 2 ±0.01 ±1 Input Capacitance 16 UNITS V µA pF INTERNAL REFERENCE (MAX1248 only, reference buffer enabled) VREF Output Voltage TA = +25°C (Note 7) 2.470 2.500 VREF Short-Circuit Current 2.530 30 VREF Temperature Coefficient MAX1248 Load Regulation (Note 8) 0mA to 0.2mA output load Internal compensation mode External compensation mode Capacitive Bypass at VREF Capacitive Bypass at REFADJ mA ±30 ppm/°C 0.35 mV 0 4.7 0.01 REFADJ Adjustment Range V µF µF ±1.5 % EXTERNAL REFERENCE AT VREF (Buffer disabled) VREF Input Voltage Range (Note 9) VDD + 50mV 1.0 VREF Input Current VREF = 2.500V VREF Input Resistance 100 18 Shutdown VREF Input Current 150 25 0.01 V µA kΩ 10 µA VDD 0.5 V Internal compensation mode External compensation mode MAX1248 MAX1249 MAX1248 MAX1249 0 4.7 µF VDD ≤ 3.6V VDD > 3.6V 2.0 3.0 REFADJ Buffer-Disable Threshold EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at VREF Reference-Buffer Gain REFADJ Input Current 2.06 2.00 V/V ±50 ±10 µA DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage VIH VIL VHYST VIN = 0V or VDD DIN, SCLK, CS Input Capacitance CIN (Note 10) SHDN Input High Voltage VSH VDD - 0.4 SHDN Input Mid Voltage VSM 1.1 SHDN Input Low Voltage VSL IS 0.8 V ±1 µA 15 pF 0.2 IIN SHDN Input Current V SHDN = 0V or VDD ±0.01 V V VDD - 1.1 V 0.4 V ±4.0 µA _______________________________________________________________________________________ 3 MAX1248/MAX1249 ELECTRICAL CHARACTERISTICS (continued) MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference; VREF = 2.500V applied to VREF pin, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SHDN Voltage, Floating VFLT SHDN Maximum Allowed Leakage, Mid Input CONDITIONS MIN SHDN = FLOAT TYP MAX VDD / 2 SHDN = FLOAT UNITS V ±100 nA DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low VOL Output Voltage High VOH Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage IL COUT ISINK = 5mA 0.4 ISINK = 16mA 0.8 ISOURCE = 0.5mA Supply Rejection (Note 12) 4 V ±0.01 CS = VDD (Note 10) VDD 2.70 Operating mode, full-scale input (Note 11) Positive Supply Current VDD - 0.5 CS = VDD IDD Full power-down ±10 µA 15 pF 5.25 V VDD = 5.25V 1.6 3.0 VDD = 3.6V 1.2 2.0 VDD = 5.25V 3.5 15 VDD = 3.6V 1.2 10 30 70 IDD Fast power-down (MAX1248) VDD = 5.25V PSR VDD = 2.7V to 5.25V, full-scale input, external reference = 2.500V V ±0.3 _______________________________________________________________________________________ mA µA mV +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 (VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time SYMBOL CONDITIONS MIN tACQ 1.5 DIN to SCLK Setup tDS 100 DIN to SCLK Hold tDH TYP MAX UNITS µs ns 0 MAX124_ _C/E 20 200 MAX124_ _M 20 240 ns SCLK Fall to Output Data Valid tDO Figure 1 CS Fall to Output Enable tDV Figure 1 240 ns CS Rise to Output Disable tTR Figure 2 240 ns CS to SCLK Rise Setup tCSS CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB ns 100 ns tCSH 0 ns tCH 200 ns tCL 200 tSSTRB ns Figure 1 240 ns tSDV External clock mode only, Figure 1 240 ns CS Rise to SSTRB Output Disable tSTR External clock mode only, Figure 2 240 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode only (Note 10) CS Fall to SSTRB Output Enable 0 ns Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX1248—internal reference, offset nulled; MAX1249 — external reference (VREF = +2.500V), offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7 Sample tested to 0.1% AQL. Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 10 Guaranteed by design. Not subject to production testing. Note 11: The MAX1249 typically draws 400µA less than the values shown. Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|. _______________________________________________________________________________________ 5 MAX1248/MAX1249 TIMING CHARACTERISTICS __________________________________________Typical Operating Characteristics (VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.25 CLOAD = 50pF MAX1249 1.00 CLOAD = 20pF 0.75 2.5 2.0 1.5 1.0 2.5000 0.5 3.25 3.75 4.25 4.75 0 2.25 5.25 2.75 3.25 3.75 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN CURRENT (µA) MAX1248 1.2 1.1 1.0 MAX1249 4.75 0.8 -60 -20 20 100 MAX1248-05 0.8 -20 20 60 0.20 100 VDD = 2.7V 2.498 2.497 2.496 2.495 -60 -40 -20 0 140 20 40 60 80 100 120 140 INTEGRAL NONLINEARITY vs. CODE 0.100 MAX1248-08 MAX1248-07 0.20 VDD = 3.6V INTEGRAL NONLINEARITY vs. TEMPERATURE VDD = 2.7V 0.25 5.25 2.499 TEMPERATURE (°C) 0.30 0.25 VDD = 5.25V 2.500 TEMPERATURE (°C) TEMPERATURE (°C) 0.30 4.75 2.494 -60 INTERGRAL NONLINEARITY vs. SUPPLY VOLTAGE 4.25 2.501 1.2 140 3.75 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 0 60 3.25 SHUTDOWN CURRENT vs. TEMPERATURE 1.6 RLOAD = ∞ CODE = 1010101000 2.75 SUPPLY VOLTAGE (V) 0.4 0.9 2.4975 2.25 5.25 VDD (V) 2.0 MAX1247-04 1.3 4.25 MAX1248-06 2.75 MAX1248-09 0.50 2.25 SUPPLY CURRENT (mA) MAX1248-09 3.5 3.0 2.5025 INTERNAL REFERENCE VOLTAGE (V) MAX1248 FULL POWER-DOWN MAX1248/49-02 CLOAD = 50pF CLOAD = 20pF 4.0 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE, VREF SUPPLY CURRENT (mA) MAX1248-01 RL = ∞ CODE = 10101010 1.75 1.50 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT (µA) 2.00 0.075 0.15 0.10 0.15 0.10 MAX1248 MAX1248 MAX1249 MAX1249 2.25 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 5.25 0 -0.050 -0.075 -0.100 0 00 0.025 -0.025 0.05 0.05 6 INL (LSB) INL (LSB) 0.050 INL (LSB) MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 -60 -40 -20 0 20 40 60 80 100 120 140 0 256 TEMPERATURE (°C) _______________________________________________________________________________________ 512 CODE 768 1024 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 PIN NAME FUNCTION 1 VDD Positive Supply Voltage 2–5 CH0–CH3 Sampling Analog Inputs 6 COM Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB. 7 SHDN Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. 8 VREF Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. 9 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. 10 AGND Analog Ground 11 DGND Digital Ground 12 DOUT Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high. 13 SSTRB Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). 14 DIN Serial Data Input. Data is clocked in at SCLK’s rising edge. 15 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. 16 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60%.) VDD DOUT DOUT CLOAD 50pF 6k VDD DOUT CLOAD 50pF DGND DGND a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Enable Time 6k 6k DOUT CLOAD 50pF 6k DGND a) VOH to High-Z CLOAD 50pF DGND b) VOL to High-Z Figure 2. Load Circuits for Disable Time _______________________________________________________________________________________ 7 MAX1248/MAX1249 ______________________________________________________________Pin Description MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 _______________Detailed Description The MAX1248/MAX1249 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 3 is a block diagram of the MAX1248/MAX1249. Pseudo-Differential Input The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0–CH3, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from two pairs: CH0/CH1 and CH2/CH3. Configure the channels with Tables 2 and 3. Please note that the codes for CH0–CH3 in the MAX1248/MAX1249 correspond to the codes for CH2–CH5 in the eight-channel (MAX148/MAX149) versions. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends CS SCLK on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10-bit resolution. This action is equivalent to transferring a charge of 16pF x [(V IN+) - (V IN-)] from C HOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. Track/Hold The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, 15 16 DIN 14 SHDN 7 CH0 2 CH1 3 CH2 4 CH3 5 CAPACITIVE DAC INPUT SHIFT REGISTER VREF INT CLOCK CONTROL LOGIC CH0 COM OUTPUT SHIFT REGISTER ANALOG INPUT MUX REFADJ 9 VREF 8 13 SSTRB RIN 9k CH1 CSWITCH CLOCK IN SAR ADC CH2 OUT REF 20k A ≈ 2.06* CH3 1 11 10 +2.500V MAX1248 MAX1249 VDD DGND AGND ZERO 16pF DOUT T/H 6 +1.21V REFERENCE (MAX1248) 12 COMPARATOR INPUT CHOLD MUX – + TRACK T/H SWITCH COM HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. SINGLE-ENDED MODE: IN+ = CHO–CH3, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3. *A ≈ 2.00 (MAX1249) Figure 3. Block Diagram 8 Figure 4. Equivalent Input Circuit _______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249 Table 1. Control-Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0 BIT NAME DESCRIPTION 7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte. 6 5 4 SEL2 SEL1 SEL0 These three bits select which of the four channels are used for the conversion (Tables 2 and 3). 3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF / 2 to +VREF / 2. 2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). 1 0(LSB) PD1 PD0 Selects clock and power-down modes. PD1 PD0 Mode 0 0 Full power-down 0 1 Fast power-down (MAX1248 only) 1 0 Internal clock mode 1 1 External clock mode the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 7.6 x (RS + RIN) x 16pF where RIN = 9kΩ, RS = the source impedance of the input signal, and tACQ is never less than 1.5µs. Note that source impedances below 3kΩ do not significantly affect the ADC’s AC performance. Higher source impedances can be used if a 0.01µF capacitor is connected to the individual analog inputs. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth. Input Bandwidth The ADC’s input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from AGND - 0.3V to V DD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than AGND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 4mA. How to Start a Conversion A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1248/MAX1249’s internal shift register. After CS falls, the first arriving logic “1” bit defines the control byte’s MSB. Until this first “start” bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX1248/MAX1249 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the sim- _______________________________________________________________________________________ 9 MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 DIF = 1) Table 2. Channel Selection in Single-Ended Mode (SGL/D SEL2 0 SEL1 0 SEL0 1 1 0 1 0 1 0 1 1 0 CH0 + CH1 CH2 CH3 COM – + – + – + – DIF = 0) Table 3. Channel Selection in Differential Mode (SGL/D SEL2 0 SEL1 0 SEL0 1 0 1 0 1 0 1 1 1 0 CH0 + plest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 10-bit conversion result). See Figure 19 for MAX1248/ MAX1249 QSPI connections. Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 5 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with one leading zero, two sub-bits, and three trailing zeros. The total conversion time is a function of the 10 – CH1 – CH2 CH3 + – – + + serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120µs. Digital Output In unipolar input mode, the output is straight binary (Figure 16). For bipolar inputs, the output is two’s complement (Figure 17). Data is clocked out at the falling edge of SCLK in MSB-first format. Clock Modes The MAX1248/MAX1249 may use either an external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1248/MAX1249. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 6–9 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 10 SCLK falling edges (Figure 5). SSTRB and DOUT go into a high-impedance state when ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249 CS tACQ SCLK 1 DIN 4 8 SEL2 SEL1 SEL0 UNI/ SGL/ PD1 PD0 BIP DIF 12 16 20 24 START SSTRB B9 MSB A/D STATE RB3 RB2 RB1 DOUT B8 B7 B6 ACQUISITION 1.5µs IDLE B5 B4 B3 B2 B1 B0 LSB S1 CONVERSION S0 FILLED WITH ZEROS IDLE (fCLK = 2MHz) Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK ≤ 2MHz) ••• CS tCSH tCSS tCL tCH SCLK tCSH ••• tDS tDH ••• DIN tDV tDO tTR ••• DOUT Figure 6. Detailed Serial-Interface Timing CS goes high; after the next CS falling edge, SSTRB will output a logic low. Figure 7 shows the SSTRB timing in external clock mode. The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serial-clock frequency is less than 100kHz, or if serial-clock interruptions could cause the conversion interval to exceed 120µs. ______________________________________________________________________________________ 11 MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ••• CS ••• tSTR tSDV SSTRB ••• ••• tSSTRB SCLK tSSTRB •• • • •••• PD0 CLOCKED IN Figure 7. External Clock Mode SSTRB Detailed Timing CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24 SGL/ SEL2 SEL1 SEL0 UNI/ BIP DIF PD1 PD0 DIN START SSTRB tCONV B9 MSB DOUT A/D STATE IDLE ACQUISITION 1.5µs CONVERSION 7.5µs MAX B8 B7 B0 LSB S1 S0 FILLED WITH ZEROS IDLE (fSCLK = 2MHz) (SHDN = FLOAT) Figure 8. Internal Clock Mode Timing Internal Clock In internal clock mode, the MAX1248/MAX1249 generate their own conversion clocks internally. This frees the µP from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor’s convenience, at any clock rate from 0MHz to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the 12 MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 8). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1248/MAX1249 and three-states DOUT, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 9 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX1248/MAX1249 at clock rates exceeding 2.0MHz if the minimum acquisition time, tACQ, is kept above 1.5µs. ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 3 of a conversion in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is complete, the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX1248/MAX1249 can run with CS held low between conversions is 15 clocks per conversion. Figure 10a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. CS Most microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the MAX1248/MAX1249. Figure 10b shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. __________ Applications Information Power-On Reset When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1248/MAX1249 in internal clock mode, ready to convert with SSTRB = high. After the power supplies have stabilized, the internal reset time is 10µs, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros (also see Table 4). Reference-Buffer Compensation In addition to its shutdown function, SHDN selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. The 100kHz minimum clock rate is limited by droop on the sample-and-hold, and is independent of the compensation used. ••• tCONV tSCK tCSH SSTRB tCSS ••• tSSTRB SCLK ••• tDO PD0 CLOCK IN DOUT ••• NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 9. Internal Clock Mode SSTRB Detailed Timing ______________________________________________________________________________________ 13 MAX1248/MAX1249 Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as: MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 CS 1 8 1 8 1 SCLK S DIN S CONTROL BYTE 0 DOUT S CONTROL BYTE 1 CONTROL BYTE 2 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 0 CONVERSION RESULT 1 SSTRB Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing CS ••• SCLK ••• DIN DOUT S S CONTROL BYTE 0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 0 ••• CONTROL BYTE 1 B9 B8 B7 B6 ••• CONVERSION RESULT 1 Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing Float SHDN to select external compensation. The Typical Operating Circuit uses a 4.7µF capacitor at VREF. A value of 4.7µF or greater ensures referencebuffer stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see Choosing Power-Down Mode and Table 4). Pull SHDN high to select internal compensation. Internal compensation requires no external capacitor at VREF and allows for the shortest power-up times. The maximum clock rate is 2MHz in internal clock mode and 400kHz in external clock mode. Choosing Power-Down Mode You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or floating (Tables 1 and 5). In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte. 14 Full power-down mode turns off all chip functions that draw quiescent current, reducing supply current typically to 2µA. Fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 30µA. Power-up time can be shortened to 5µs in internal compensation mode. Table 4 shows how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7µF compensation capacitor when the capacitor is initially fully discharged. From fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2LSB while shut down. In powerdown, leakage currents at VREF cause droop on the reference bypass capacitor. Figures 11a and 11b show the various power-down sequences in both external and internal clock modes. ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 REFERENCE BUFFER REFERENCE-BUFFER COMPENSATION MODE VREF CAPACITOR (µF) POWER-DOWN MODE POWER-UP DELAY (µs) MAXIMUM SAMPLING RATE (ksps) Enabled Internal — Fast 5 26 Enabled Internal — Full 300 26 Enabled External 4.7 Fast See Figure 13c 133 Enabled External 4.7 Full See Figure 13c 133 Disabled — — Fast 2 133 Disabled — — Full 2 133 CLOCK MODE EXTERNAL EXTERNAL SHDN SETS SOFTWARE POWER-DOWN SETS EXTERNAL CLOCK MODE DIN S X X X X X 1 1 DOUT SETS EXTERNAL CLOCK MODE SX X XX X 0 0 S XX XXX 1 1 VALID DATA 10+2 DATA BITS 10+2 DATA BITS POWERED UP POWERED UP MODE SOFTWARE POWER-DOWN INVALID DATA HARDWARE POWERDOWN POWERED UP Figure 11a. Timing Diagram Power-Down Modes, External Clock CLOCK MODE DIN INTERNAL S X X X X X 1 0 SX X XX X 0 0 DOUT SSTRB MODE SETS POWER-DOWN SETS INTERNAL CLOCK MODE S DATA VALID DATA VALID CONVERSION CONVERSION POWERED UP POWER-DOWN POWERED UP Figure 11b. Timing Diagram Power-Down Modes, Internal Clock ______________________________________________________________________________________ 15 MAX1248/MAX1249 Table 4. Typical Power-Up Delay Times Table 5. Software Power-Down and Clock Mode PD1 PD0 DEVICE 0 0 Full Power-Down 0 1 Fast Power-Down 1 0 Internal Clock 1 1 External Clock 10,000 100 4 CHANNELS 10 Table 6. Hardware Power-Down and Internal Clock Frequency 1 CHANNEL 1 SHDN STATE DEVICE MODE REFERENCEBUFFER COMPENSATION INTERNAL CLOCK FREQUENCY 1 Enabled Internal 225kHz Floating Enabled External 1.8MHz 0 PowerDown N/A N/A Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 5, PD1 and PD0 also specify the clock mode. When software shutdown is asserted, the ADC operates in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active, and conversion results may be clocked out after the MAX1248/MAX1249 enter a software power-down. The first logical 1 on DIN is interpreted as a start bit and powers up the MAX1248/MAX1249. Following the start bit, the data input word or control byte also determines clock mode and power-down states. For example, if the DIN word contains PD1 = 1, then the chip remains powered up. If PD0 = PD1 = 0, a power-down resumes after one conversion. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down (Table 6). Unlike software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the clock frequency in internal clock mode. Letting SHDN float sets the internal clock frequency to 1.8MHz. When returning to normal operation with SHDN floating, there is a tRC delay of approximately 2MΩ x CL, where CL is the capacitive loading on the SHDN pin. Pulling SHDN high sets the internal clock frequency to 225kHz. 16 VREF = VDD = 3.0V RLOAD = ∞ CODE = 1010101000 1000 IDD (µA) MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 0.1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) Figure 12. Average Supply Current vs. Conversion Rate with External Reference This feature eases the settling-time requirement for the reference voltage. With an external reference, the MAX1248/MAX1249 can be considered fully powered up within 2µs of actively pulling SHDN high. Power-Down Sequencing The MAX1248/MAX1249 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 12, 13a, and 13b show the average supply current as a function of the sampling rate. The following discussion illustrates the various power-down sequences. Lowest Power at up to 500 Conversions/Channel/Second The following examples illustrate two different powerdown sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. Figure 13a depicts the MAX1248 power consumption for one or eight channel conversions, utilizing full power-down mode and internal-reference compensation. A 0.01µF bypass capacitor at REFADJ forms an RC filter with the internal 20kΩ reference resistor with a 0.2ms time constant. To achieve full 10-bit accuracy, 8 time constants or 1.6ms are required after power-up. Waiting 1.6ms in FASTPD mode instead of in full powerup can reduce the power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 14. ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 10,000 RLOAD = ∞ CODE = 1010101000 10 AVERAGE SUPPLY CURRENT (µA) AVERAGE SUPPLY CURRENT (µA) MAX1248/MAX1249 100 4 CHANNELS RLOAD = ∞ CODE = 1010101000 1000 100 4 CHANNELS 1 CHANNEL 10 1 CHANNEL 1 1 0.01 0.1 1 10 100 1k 0.1 CONVERSION RATE (Hz) Lowest Power at Higher Throughputs Figure 13b shows the power consumption with external-reference compensation in fast power-down, with one and four channels converted. The external 4.7µF compensation requires a 75µs wait after power-up with one dummy conversion. This circuit combines fast multi-channel conversion with lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX1248/MAX1249 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. Internal and External References The MAX1248 can be used with an internal or external reference voltage, whereas an external reference is required for the MAX1249. An external reference can be connected directly at VREF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at VREF for both the MAX1248 and the MAX1249. The MAX1248’s internally trimmed 1.21V reference is buffered with a gain of 2.06. The MAX1249’s REFADJ pin is also buffered with a gain of 2.06 to scale an external 1.25V reference at REFADJ to 2.5V at VREF. 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) Figure 13b. MAX1248 Supply Current vs. Conversion Rate, FASTPD 3.0 2.5 POWER-UP DELAY (ms) Figure 13a. MAX1248 Supply Current vs. Conversion Rate, FULLPD 1 2.0 1.5 1.0 0.5 0 0 0.01 0.1 1 10 TIME IN SHUTDOWN (sec) Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown Internal Reference (MAX1248) The MAX1248’s full-scale range with the internal reference is 2.5V with unipolar inputs and ±1.25V with bipolar inputs. The internal-reference voltage is adjustable to ±1.5% with the circuit of Figure 15. ______________________________________________________________________________________ 17 MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 COMPLETE CONVERSION SEQUENCE 1.6ms WAIT DIN CH1 (ZEROS) 1 00 FULLPD 1 01 FASTPD (ZEROS) CH7 1 11 1 NOPD 00 1 FULLPD 01 FASTPD 1.21V REFADJ 0V 2.50V τ = RC = 20kΩ x CREFADJ VREF 0V tBUFFEN ≈ 75µs Figure 14. MAX1248 FULLPD/FASTPD Power-Up Sequence External Reference With both the MAX1248 and MAX1249, an external reference can be placed at either the input (REFADJ) or the output (VREF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 20kΩ for the MAX1248 and higher than 100kΩ for the MAX1249, where the internal reference is omitted. At VREF, the DC input resistance is a minimum of 18kΩ. During conversion, an external reference at VREF must deliver up to 350µA DC load current and have an output impedance of 10Ω or less. If the reference has higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7µF capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct VREF input, disable the internal buffer by tying REFADJ to VDD. In power-down, the input bias current to REFADJ can be as much as 25µA with REFADJ tied to V DD . Pull REFADJ to AGND to minimize the input bias current in power-down. +3.3V 24k MAX1248 510k 9 100k REFADJ 0.01µF Figure 15. MAX1248 Reference-Adjust Circuit OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 Transfer Function Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. The external reference must have a temperature coefficient of 20ppm/°C or less to achieve accuracy to within 1LSB over the commercial temperature range of 0°C to +70°C. Figure 16 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 17 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 2.44mV (2.500V / 1024) for unipolar operation and 1LSB = 2.44mV [(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation. 18 FS = VREF + COM ZS = COM VREF 1024 1LSB = 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 (COM) 2 3 INPUT VOLTAGE (LSBs) FS FS - 3/2LSB Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249 Table 7. Full Scale and Zero Scale UNIPOLAR MODE BIPOLAR MODE Full Scale Zero Scale VREF + COM COM Positive Zero Negative Full Scale Scale Full Scale VREF / 2 + COM COM -VREF / 2 + COM OUTPUT CODE 011 . . . 111 FS = VREF + COM 2 011 . . . 110 ZS = COM 000 . . . 010 000 . . . 001 000 . . . 000 SUPPLIES -VREF + COM 2 VREF 1LSB = 1024 -FS = +3V +3V GND +3V DGND R* = 10Ω 111 . . . 111 111 . . . 110 111 . . . 101 VDD AGND COM DGND 100 . . . 001 100 . . . 000 COM* - FS MAX1248 MAX1249 +FS - 1LSB INPUT VOLTAGE (LSB) DIGITAL CIRCUITRY * OPTIONAL *COM ≥ VREF / 2 Figure 17. Bipolar Transfer Function, Zero Scale (ZS) = COM, Full Scale (FS) = VREF / 2 + COM Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 18 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. For lowest noise operation, the ground return to the star ground’s power supply should be low impedance and as short as possible. Figure 18. Power-Supply Grounding Connection High-frequency noise in the VDD power supply may affect the ADC’s high-speed comparator. Bypass the supply to the star ground with 0.1µF and 1µF capacitors close to pin 1 of the MAX1248/MAX1249. Minimize capacitor lead lengths for best supply-noise rejection. If the +3V power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter (Figure 18). High-Speed Digital Interfacing with QSPI The MAX1248/MAX1249 can interface with QSPI using the circuit in Figure 19 (fSCLK = 2.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the four channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own micro-sequencer. The MAX1248/MAX1249 are QSPI compatible up to their maximum external clock frequency of 2MHz. ______________________________________________________________________________________ 19 MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 +3V +3V 1µF 0.1µF ANALOG INPUTS +2.5V 1 VDD 2 CH0 SCLK 16 3 CS 15 MAX1248 CH1 MAX1249 DIN 14 4 CH2 SSTRB 13 5 CH3 DOUT 12 6 COM DGND 11 7 SHDN AGND 10 8 VREF REFADJ SCK PCS0 MC683XX MOSI MISO (GND) 9 CLOCK CONNECTIONS NOT SHOWN 0.1µF Figure 19. MAX1248/MAX1249 QSPI Connections External Reference TMS320LC3x Interface Figure 20 shows an application circuit to interface the MAX1248/MAX1249 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 21. Use the following steps to initiate a conversion in the MAX1248/MAX1249 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are tied together with the MAX1248/MAX1249’s SCLK input. 2) The MAX1248/MAX1249’s CS pin is driven low by the TMS320’s XF_ I/O port, to enable data to be clocked into the MAX1248/MAX1249’s DIN. 3) An 8-bit word (1XXXXX11) should be written to the MAX1248/MAX1249 to initiate a conversion and place the device into external clock mode. Refer to Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX1248/MAX1249’s SSTRB output is monitored via the TMS320’s FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1248/MAX1249. 20 XF CLKX CS SCLK TMS320LC3x MAX1249 CLKR DX DIN DR DOUT FSR SSTRB Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 10 + 2-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1248/MAX1249 until the next conversion is initiated. ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249 CS SCLK DIN START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0 HIGH IMPEDANCE SSTRB DOUT MSB B8 B0 LSB S1 S0 HIGH IMPEDANCE Figure 21. TMS320 Serial-Interface Timing Diagram ___________________________________________Ordering Information (continued) INL (LSB) PART† 16 Plastic DIP ±1/2 16 Plastic DIP ±1 -40°C to +85°C -40°C to +85°C -55°C to +125°C 16 QSOP 16 QSOP 16 CERDIP* ±1/2 ±1 ±1/2 MAX1249ACEE MAX1249BCEE MAX1249AEPE 0°C to +70°C 0°C to +70°C -40°C to +85°C 16 QSOP 16 QSOP 16 Plastic DIP MAX1249BEPE -40°C to +85°C 16 Plastic DIP ±1 MAX1249AEEE -40°C to +85°C 16 QSOP ±1/2 PART† TEMP. RANGE PIN-PACKAGE MAX1248AEPE -40°C to +85°C MAX1248BEPE -40°C to +85°C MAX1248AEEE MAX1248BEEE MAX1248AMJE TEMP. RANGE PIN-PACKAGE INL (LSB) ±1/2 ±1 ±1/2 MAX1248BMJE -55°C to +125°C 16 CERDIP* ±1 MAX1249BEEE -40°C to +85°C 16 QSOP ±1 MAX1249ACPE 0°C to +70°C 16 Plastic DIP ±1/2 MAX1249AMJE -55°C to +125°C 16 CERDIP* ±1/2 MAX1249BCPE 0°C to +70°C 16 Plastic DIP ±1 MAX1249BMJE -55°C to +125°C 16 CERDIP* ±1 Contact factory for availability of alternate surface-mount packages. * Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. † ______________________________________________________________________________________ 21 _________________Pin Configuration ___________________Chip Information TRANSISTOR COUNT: 2554 TOP VIEW VDD 1 16 SCLK CH0 2 15 CS 14 DIN CH1 3 CH2 4 CH3 5 MAX1248 MAX1249 13 SSTRB 12 DOUT COM 6 11 DGND SHDN 7 10 AGND VREF 8 9 REFADJ DIP/QSOP ________________________________________________________Package Information QSOP.EPS MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 22 ______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 PDIPN.EPS CDIPS.EPS ______________________________________________________________________________________ 23 MAX1248/MAX1249 ___________________________________________Package Information (continued) MAX1248/MAX1249 +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.