TI SN74LVCZ161284AGR

SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
D
D
D
D
D
D
D
D
Power-On Reset (POR) Prevents Printer
Errors When Printer Is Turned On, But No
Valid Signal Is at Pins A9–A13
Operates From 3 V to 3.6 V
1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
Designed for the IEEE Std 1284-I (Level-1
Type) and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications
Flow-Through Architecture Optimizes PCB
Layout
Ioff and Power-Up 3-State Support Hot
Insertion
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 350-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
description/ordering information
The SN74LVCZ161284A is designed for 3-V to
3.6-V VCC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
DGG PACKAGE
(TOP VIEW)
HD
A9
A10
A11
A12
A13
VCC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
VCC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
DIR
Y9
Y10
Y11
Y12
Y13
VCC CABLE
B1
B2
GND
B3
B4
B5
B6
GND
B7
B8
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control
input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the
cable side and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line
and a driver to drive the PERI LOGIC line.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C
TSSOP – DGG
Tape and reel SN74LVCZ161284AGR
LVCZ161284A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
description/ordering information (continued)
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in
a totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive
requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel
peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT),
all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC
OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The Power-On Reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on until an
associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and
noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer
system errors caused by deasserting the BUSY signal in the cable at power on.
FUNCTION TABLE
INPUTS
2
DIR
HD
L
L
L
H
H
L
H
H
OUTPUT
MODE
Open drain
A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT
Totem pole
B1–B8 to A1–A8 and C14–C17 to A14–A17
Totem pole
B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14–C17 to A14–A17
Open drain
A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT
Totem pole
C14–C17 to A14–A17
Totem pole
A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
logic diagram
VCC CABLE
DIR
HD
42
See Note A
48
See Note A
1
See Note B
B1–B8
A1–A8
A9–A13
Y9–Y13
See
Note C
PERI LOGIC IN
19
30
A14–A17
HOST LOGIC OUT
PERI LOGIC OUT
C14–C17
24
25
HOST LOGIC IN
NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The
PMOS transistor is turned off when the associated driver is in the low state.
B. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND.
C. Active input detection circuit forces Y9–Y13 to the high state after power on, until one of the A9–A13 pins goes high (see below).
D
A9
A10
A11
A12
A13
Timer
Q
OUT
C
R
Power-On
Reset
Active Input Detection Circuit
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3
SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: VCC CABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input and output voltage range, VI and VO: Cable side (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . –2 V to 7 V
Peripheral side (see Note 1) . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO: Except PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Output high sink current, ISK (VO = 5.5 V and VCC CABLE = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than –0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC CABLE
VCC
MIN
MAX
Supply voltage for the cable side, VCC CABLE ≥ VCC
3
5.5
V
Supply voltage
3
3.6
V
A, B, DIR, and HD
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
VI
Input voltage
VO
Open-drain output voltage
IOH
High-level output current
2.3
HOST LOGIC IN
2.6
2
0.8
C14–C17
0.8
HOST LOGIC IN
1.6
PERI LOGIC IN
0.8
V
Peripheral side
0
Cable side
0
VCC
5.5
V
HD low
0
5.5
V
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
B and Y outputs
Low-level output current
V
A, B, DIR, and HD
HD high, B and Y outputs
IOL
2
C14–C17
PERI LOGIC IN
UNIT
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
–14
–4
mA
–0.5
14
4
mA
84
TA
Operating free-air temperature
0
70
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
electrical characteristics over recommended
VCC CABLE = 5 V (unless otherwise noted)
PARAMETER
∆Vt
Hysteresis
H t
i
(VT+ – VT–
T )
VOH
VOL
TEST CONDITIONS
33V
3.3
HOST LOGIC IN
C inputs
HD high,
high B and Y outputs
IOH = –14
14 mA
HD high,
g , A outputs,, and
HOST LOGIC OUT
IOH = –4 mA
IOH = –50 µA
3V
PERI LOGIC OUT
IOH = –0.5
0 5 mA
B and Y outputs
IOL = 14 mA
IOL = 50 µA
A outputs and HOST LOGIC OUT
Open-drain Y outputs
IOZPU
B and Y outputs
IOZPD
B and Y outputs
3.15 V
3.3 V‡
IOL = 4 mA
IOL = 84 mA
ZO
R pullup
Cable side
2.4
2.4
V
2.8
3.1
4.5
0.2
04
V
3 6 Vw
3.6
50
µA
–3.5
mA
±1
µA
3.6 V
±20
µA
VO = VCC CABLE
VO = GND (pullup resistors)
3.6 V
50
µA
3.6 Vw
–3.5
mA
3.6 Vw
–3.5
mA
VO = GND (pullup resistors)
VO = 5.5 V
VO = GND
VO = 5.5 V
0 tto 1.5
1 5 V¶
0 tto 1.5
1 5 V¶
VO = GND
350
µA
–5
mA
350
µA
–5
mA
100
µA
0§
100
3.6 V‡
VI = GND (12 × pullup)
I/O ports
2.23
3.6 V
VI or VO = 0 to 5.5 V
All inputs
V
0.2
VI = VCC or GND
VO = VCC or GND
Power-down output leakage,
B1–B8 and Y9–Y13 outputs
Cio
MAX
0.9
VI or VO = 0 to 3.6 V
Ci
UNIT
3V
Power-down input leakage,
except A1–A8 or B1–B8 inputs
ICC
TYP†
MIN
0.77
VI = VCC
VI = GND (pullup resistors)
C inputs
B outputs
range,
0.8
3V
3.3 V‡
A1–A8
Ioff
ff
VCC
temperature
0.4
All inputs except the B or C inputs
IOZ
free-air
All inputs except the
C inputs and HOST LOGIC IN
PERI LOGIC OUT
II
operating
VI = VCC,
VI = VCC or GND
IO = 0
VO = VCC or GND
IOH = –35 mA
Cable side
VO = 0 V (in high-impedance state)
† Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C.
‡ VCC CABLE = 4.7 V
§ VCC CABLE = 3.6 V
¶ Connect the VCC pin and the VCC CABLE pin.
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45
3.6 V
70
3.6 V
0.8
mA
3.3 V
3
pF
3.3 V
7
pF
3.3 V
45
Ω
3.3 V
1.15
1.65
kΩ
5
SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 and 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Totem pole
A1 A8
A1–A8
B1 B8
B1–B8
tPLH
tPHL
Totem pole
A9 A13
A9–A13
Y9 Y13
Y9–Y13
tPLH
tPHL
Totem pole
B1 B8
B1–B8
A1 A8
A1–A8
tPLH
tPHL
Totem pole
C14 C17
C14–C17
A14 A17
A14–A17
tPLH
tPHL
Totem pole
PERI LOGIC IN
PERI LOGIC OUT
tPLH
tPHL
Totem pole
HOST LOGIC IN
HOST LOGIC OUT
tslew
tPZH
Totem pole
B1–B8 and Y9–Y13 outputs
MAX
1
22
1
22
1
20
1
20
1
10
1
10
1
11
1
11
1
13
1
13
1
13
1
13
0.05
0.4
B1–B8,, Y9–Y13,, and
PERI LOGIC OUT
1
20
1
15
DIR
A1–A8
1
15
B1 B8
B1–B8
1
15
DIR
1
15
A1–A13
B1–B8 or Y9–Y13
ten–tdis
tPHZ
tPLZ
Open drain
TYP†
HD
tPHZ
tr, tf
MIN
tsk(o)‡
1
B1–B8 or A1–A8
2.5
A1–A8 or B1–B8
† Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C.
‡ Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction.
UNIT
ns
ns
ns
ns
ns
ns
V/ns
ns
ns
ns
120
ns
10
ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
VCC = 3.3 V
VCC CABLE = 5 V
TA = 25°C
TYP = 80 ns
TEST CONDITIONS
Outputs enabled
CL = 0,
f = 10 MHz
VCC and VCC CABLE
An (one of A9–A13)
50% VCC
Initial Activation Time
Y9–Y13, Other Than Yn
50% VCC CABLE
One of pins A9–A13 Is Switched as Shown Above, and Other Four Inputs Are Forced at Low State.
Figure 1. Error-Free Circuit Timing
6
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TYP
45
UNIT
pF
SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC CABLE
CL = 50 pF
(see Note A)
62 Ω
TP1
2.7 V
Input
(see Note B)
0V
tf1
Sink Load
From
B or Y Output
Under Test
95% (VCC CABLE = 5.0 V
50% (VCC CABLE = 5.0 V
Output
(see Note B)
tr1
Source Load
Output
(see Note B)
CL = 50 pF
(see Note A)
62 Ω
"0.5 V)
"0.5 V)
1.9 V (VCC CABLE = 5.0 V
0.4 V
"0.5 V)
VOLTAGE WAVEFORMS MEASURED AT TP1
SLEW RATE WAVEFORMS (B1–8 AND Y9–13)
SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE)
VCC CABLE
2.7 V
Input
(see Note C)
TP1
1.4 V
1.4 V
0V
500 Ω
From
B or Y Output
2V
Output
(see Note C)
CL = 50 pF
(see Note A)
VOH
2V
0.8 V
0.8 V
tr
VOL
tf
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN)
NOTES: A. CL includes probe and jig capacitance.
B. When VCC CABLE is 3.3 V 0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and
1.9 V for the falling edge. When VCC CABLE is 5 V
0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge
and between 95% VCC CABLE and 50% VCC CABLE for the falling edge.
t slew fall
C.
D.
E.
F.
G.
+V
CC
ǒ
"
Ǔ
95% – 50%
t f1
"
t slew rise
+
ǒ
1.9 V – 0.4 V
t r1
Ǔ
Input rise (tr) and fall (tf) times are 3 ns. Rise and fall times (open drain) are <120 ns.
The outputs are measured one at a time with one transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPLH and tPHL are the same as tpd.
Figure 2. Load Circuits and Voltage Waveforms
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7
SN74LVCZ161284A
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
VCC × 2 V
Open
When Measuring the Cable Side, VCC CABLE × 2 V
GND
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT
Input
(see Note B)
1.4 V
0V
tPLH
tPHL
2.7 V
1.4 V
1.4 V
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC × 2 V
(see Note C)
VOH
1.4 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
50% VCC
Output
S1
Open
VCC × 2 V
GND
Output
Control
2.7 V
1.4 V
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
VOH – 0.3 V
1.4 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
B-TO-A LOAD (TOTEM POLE)
VCC CABLE
CL = 50 pF
(see Note A)
500 Ω
TP1
From
B or Y Output
Under Test
tw
2.7 V
Input
(see Note D)
Sink Load
1.4 V
1.4 V
0V
tPHL
tPLH
tPLH
tPHL
Source Load
Output
500 Ω
VOL + 1.4 V
CL = 50 pF
(see Note A)
VOH
VOH – 1.4 V
VOL
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
A-TO-B LOAD OR A-TO-Y LOAD (TOTEM POLE)
NOTES: A. CL includes probe and jig capacitance.
B. Input rise and fall times are 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 µs.
E. The outputs are measured one at a time with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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