SCES541 − JANUARY 2004
D Auto-Power-Up Feature Prevents Printer
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Errors When Printer Is Turned On, But No
Valid Signal Is at A9−A13 Pins
1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
Designed for the IEEE Std 1284-I (Level-1
Type) and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications
Flow-Through Architecture Optimizes PCB
Layout
Ioff and Power-Up 3-State Support Hot
Insertion
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection
− ±4 kV − Human-Body Model
− ±8 kV − IEC 61000-4-2, Contact Discharge
(Connector Pins)
− ±15 kV − IEC 61000-4-2, Air-Gap
Discharge (Connector Pins)
− ±15 kV − Human-Body Model (Connector
Pins)
HD
A9
A10
A11
A12
A13
VCC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
VCC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
description/ordering information
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
DIR
Y9
Y10
Y11
Y12
Y13
VCC CABLE
B1
B2
GND
B3
B4
B5
B6
GND
B7
B8
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
The SN74LVCE161284 is designed for 3-V to
3.6-V VCC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control
input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the
cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and
a driver to drive the PERI LOGIC line.
ORDERING INFORMATION
0°C
0
C to 70
70°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP − DL
TOP-SIDE
MARKING
Tube
SN74LVCE161284DL
Tape and reel
SN74LVCE161284DLR
LVCE161284
TSSOP − DGG
Tape and reel SN74LVCE161284DGGR LVCE161284
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
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1
SCES541 − JANUARY 2004
description/ordering information (continued)
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in
a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive
requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel
peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT),
all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC
OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The Y outputs (Y9−Y13) stay in the high state after power on until an associated input (A9−A13) goes high.
When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated
inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting
the BUSY signal in the cable at power on.
FUNCTION TABLE
INPUTS
2
DIR
HD
L
L
L
H
H
L
H
H
OUTPUT
MODE
Open drain
A9−A13 to Y9−Y13 and PERI LOGIC IN to PERI LOGIC OUT
Totem pole
B1−B8 to A1−A8 and C14−C17 to A14−A17
Totem pole
B1−B8 to A1−A8, A9−A13 to Y9−Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14−C17 to A14−A17
Open drain
A1−A8 to B1−B8, A9−A13 to Y9−Y13, and PERI LOGIC IN to PERI LOGIC OUT
Totem pole
C14−C17 to A14−A17
Totem pole
A1−A8 to B1−B8, A9−A13 to Y9−Y13, C14−C17 to A14−A17, and PERI LOGIC IN to PERI LOGIC OUT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES541 − JANUARY 2004
logic diagram
VCC CABLE
DIR
HD
42
48
See Note A
See Note A
1
See Note B
B1−B8
A1−A8
A9−A13
Y9−Y13
See
Note C
PERI LOGIC IN
19
30
A14−A17
HOST LOGIC OUT
PERI LOGIC OUT
C14−C17
24
25
HOST LOGIC IN
NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The
PMOS transistor is turned off when the associated driver is in the low state.
B. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND.
C. Active input detection circuit forces Y9−Y13 to the high state after power-on, until one of the A9−A13 goes high (see Figure 1).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCES541 − JANUARY 2004
D
A9
A10
A11
A12
A13
Timer
Q
OUT
C
R
Auto-Power-Up
Active Input Detection Circuit
VCC = 3.3 V
VCC CABLE = 5 V
TA = 25°C
TYP = 80 ns
VCC and VCC CABLE
700 ns (TYP)
An (one of A9−A13)
50% VCC
Initial Activation Time
Y9−Y13 Other Than Yn
50% VCC CABLE
NOTE A: One of A9−A13 is switched as shown above, and the other four inputs are forced to low state.
Figure 1. Error-Free Circuit Timing
4
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SCES541 − JANUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: VCC CABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input and output voltage range, VI and VO: Cable side (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . −2 V to 7 V
Peripheral side (see Note 1) . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO: Except PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
PERI LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Output high sink current, ISK (VO = 5.5 V and VCC CABLE = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input-voltage pulse duration is limited to 40 ns if the amplitude is greater than −0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC CABLE
VCC
MIN
MAX
Supply voltage for the cable side, VCC CABLE ≥ VCC
3
5.5
V
Supply voltage
3
3.6
V
A, B, DIR, and HD
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Open-drain output voltage
IOH
High-level output current
2.3
HOST LOGIC IN
2.6
2
0.8
C14−C17
0.8
HOST LOGIC IN
1.6
PERI LOGIC IN
0.8
V
Peripheral side
0
Cable side
0
VCC
5.5
V
HD low
0
5.5
V
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
B and Y outputs
A outputs and HOST LOGIC OUT
Low-level output current
V
A, B, DIR, and HD
HD high, B and Y outputs
IOL
2
C14−C17
PERI LOGIC IN
UNIT
PERI LOGIC OUT
−14
−4
mA
−0.5
14
4
mA
84
TA
Operating free-air temperature
0
70
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES541 − JANUARY 2004
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
PARAMETER
∆V
Vt
Hysteresis
(VT+ − VT−)
VOH
VOL
TEST CONDITIONS
VCC
CABLE
VCC
All inputs except the
C inputs and HOST LOGIC IN
3.3 V
UNIT
V
0.2
0.8
HD high, B and Y outputs
IOH = −14 mA
HD high, A outputs, and
HOST LOGIC OUT
IOH = −4 mA
IOH = −50 µA
PERI LOGIC OUT
IOH = −0.5 mA
B and Y outputs
IOL = 14 mA
IOL = 50 µA
C inputs
MAX
3V
3V
2.23
3.3 V
4.7 V
2.4
3V
3V
3.15 V
3.15 V
3.1
3.3 V
4.7 V
4.5
2.4
V
2.8
0.77
0.2
3V
IOL = 4 mA
IOL = 84 mA
3V
04
V
0.9
VI = VCC
VI = GND
(pullup resistors)
50
µA
−3.5
mA
3.6 V
3.6 V
VI = VCC or GND
VO = VCC or GND
3.6 V
5.5 V
±1
µA
3.6 V
5.5 V
±20
µA
3.6 V
5.5 V
50
µA
B outputs
VO = VCC CABLE
VO = GND
(pullup resistors)
3.6 V
3.6 V
−3.5
mA
Open-drain Y outputs
VO = GND
(pullup resistors)
3.6 V
3.6 V
−3.5
mA
IOZPU
B and Y outputs
VO = 5.5 V
VO = GND
0 to 1.5 V‡
0 to 1.5 V‡
IOZPD
B and Y outputs
VO = 5.5 V
VO = GND
0 to 1.5 V‡
0 to 1.5 V‡
Power-down input leakage,
except A1−A8 or B1−B8 inputs
VI or VO = 0 to 3.6 V
II
All inputs except B or C inputs
A1−A8
IOZ
Ioff
Power-down output leakage,
B1−B8 and Y9−Y13 outputs
ZO
B1-B8, Y9-Y13
R pullup
B1-B8, Y9-Y13, C14-C17
IO = 0
VO = 0 V
(in high-impedance state)
mA
350
µA
−5
mA
µA
A
100
3.6 V
3.6 V
3.6 V
5.5 V
70
3.6 V
3.6 V
0.8
3.3 V
3.3 V
3.3 V
3.3 V
† Typical values are measured at TA = 25°C.
‡ Connect the VCC pin to the VCC CABLE pin.
POST OFFICE BOX 655303
µA
−5
0
VI or VO = 0 to 5.5 V
VI = VCC,
IOH = −35 mA
350
100
0
VI = GND
(12 × pullup)
ICC
6
5V
C inputs
PERI LOGIC OUT
TYP†
0.4
HOST LOGIC IN
A outputs and HOST LOGIC
OUT
MIN
• DALLAS, TEXAS 75265
45
Ω
36
1.15
mA
1.65
kΩ
SCES541 − JANUARY 2004
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
A9-A13, DIR, HD,
PERI LOGIC IN
Ci
VCC
VI = VCC or GND
VCC
CABLE
3.3 V
MIN
MAX
6.5
5V
HOST LOGIC IN
UNIT
pF
4
A1-A8
Cio
TYP†
VO = VCC or GND
B1-B8
3.3 V
8
5V
pF
13
† Typical values are measured at TA = 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 and 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Totem pole
A1−A8
B1−B8
tPLH
tPHL
Totem pole
A9−A13
Y9−Y13
tPLH
tPHL
Totem pole
B1−B8
A1−A8
tPLH
tPHL
Totem pole
C14−C17
A14−A17
tPLH
tPHL
Totem pole
PERI LOGIC IN
PERI LOGIC OUT
tPLH
tPHL
Totem pole
HOST LOGIC IN
HOST LOGIC OUT
tslew
tPZH
Totem pole
B1−B8 and Y9−Y13 outputs
MIN
TYP‡
MAX
2
30
2
30
2
30
2
30
2
12
2
12
2
14
2
14
2
16
2
16
1
18
1
18
0.05
0.4
30
UNIT
ns
ns
ns
ns
ns
ns
V/ns
HD
B1−B8, Y9−Y13, and
PERI LOGIC OUT
2
2
25
ten−tdis
DIR
A1−A8
2
25
tPHZ
tPLZ
2
25
DIR
B1−B8
2
25
A1−A13
B1−B8 or Y9−Y13
1
120
ns
A1−A8 or B1−B8
B1−B8 or A1−A8
10
ns
tPHZ
tr, tf
Open drain
tsk(o)§
3
ns
ns
ns
‡ Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C.
§ Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction.
ESD protection
PIN
TEST CONDITIONS
DIR, HD, A1−A8, A9−A13,
PERI LOGIC IN, A14−A17,
HOST LOGIC OUT
UNIT
±15
HBM
B1−B8, Y9−Y13, PERI LOGIC OUT,
C14−C17, HOST LOGIC IN
TYP
Contact discharge,
IEC 61000-4-2
±8
Air-gap discharge,
IEC 61000-4-2
±15
±4
HBM
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kV
kV
7
SCES541 − JANUARY 2004
operating characteristics, VCC and VCC CABLE = 3.3 V, CL = 0, f = 10 MHz, TA = 25°C
PARAMETER
Cpd
8
Power dissipation capacitance
POST OFFICE BOX 655303
FROM
(INPUT)
TO
(OUTPUT)
A
B
TYP
15
A
Y
6
PERI LOGIC IN
PERI LOGIC OUT
10
B
A
33
C
A
29
HOST LOGIC IN
HOST LOGIC OUT
29
• DALLAS, TEXAS 75265
UNIT
pF
SCES541 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
VCC CABLE
CL = 50 pF
(see Note A)
62 Ω
TP1
2.7 V
Input
(see Note B)
0V
tf1
Sink Load
From
B or Y Output
Under Test
95% (VCC CABLE = 5.0 V"0.5 V)
50% (VCC CABLE = 5.0 V"0.5 V)
Output
(see Note B)
tr1
Source Load
CL = 50 pF
(see Note A)
62 Ω
Output
(see Note B)
1.9 V (VCC CABLE = 5.0 V"0.5 V)
0.4 V
VOLTAGE WAVEFORMS MEASURED AT TP1
SLEW RATE WAVEFORMS (B1−8 AND Y9−13)
SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT
VCC CABLE
2.7 V
Input
(see Note C)
TP1
1.4 V
1.4 V
0V
500 Ω
From
B or Y Output
CL = 50 pF
(see Note A)
2V
Output
(see Note C)
VOH
2V
0.8 V
0.8 V
tr
VOL
tf
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN) OR PERI LOGIC IN TO PERI LOGIC OUT
NOTES: A. CL includes probe and jig capacitance.
B. When VCC CABLE is 3.3 V " 0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and
1.9 V for the falling edge. When VCC CABLE is 5 V " 0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge
and between 95% VCC CABLE and 50% VCC CABLE for the falling edge.
ǒ
Ǔ
t slew fall + V CC 95% – 50%
t f1
C.
D.
E.
F.
G.
ǒ
t slew rise + 1.9 V – 0.4 V
t r1
Ǔ
Input rise (tr) and fall (tf) times are 3 ns. Rise and fall times (open drain) are <120 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPLH and tPHL are the same as tpd.
Figure 2. Load Circuits and Voltage Waveforms
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SCES541 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
VCC × 2 V
Open
S1
When Measuring the Cable Side, VCC CABLE × 2 V
GND
CL = 50 pF
(see Note A)
500 Ω
2.7 V
1.4 V
1.4 V
0V
tPLH
tPHL
50% VCC
2.7 V
1.4 V
1.4 V
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC × 2 V
(see Note C)
VOH
1.4 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
S1
Open
VCC × 2 V
GND
Output
Control
LOAD CIRCUIT
Input
(see Note B)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
VOH − 0.3 V
1.4 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
HOST LOGIC IN TO HOST LOGIC OUT OR B-TO-A LOAD (TOTEM POLE)
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
S1
TEST
VCC CABLE × 2 V
Open
tPLH
tPHL
tPLZ/tPZL
tPHZ/tPZH
GND
500 Ω
S1
Open
VCC CABLE × 2 V
VCC CABLE × 2 V
GND
tw
LOAD CIRCUIT
2.7 V
Input
(see Note D)
1.4 V
1.4 V
0V
tPLH
Output
tPHL
VOL + 1.4 V
VOH
VOH − 1.4 V
VOL
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
A-TO-B LOAD OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT
NOTES: A. CL includes probe and jig capacitance.
B. Input rise and fall times are 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 µs.
E. The outputs are measured one at a time, with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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