LMX2542 PLLatinumTM Cellular and GPS Frequency Synthesizer System with Integrated VCO General Description Features LMX2542 is a highly integrated, high performance, low power frequency synthesizer system optimized for CellularCDMA 1xRTT and IS-95 mobile handsets and data systems with GPS capabilities. Using a proprietary digital phase locked loop technique, LMX2542 provides very stable, low noise local oscillator (LO) signals for up and down conversion in wireless communications devices. n Small Size 5.0 mm x 5.0 mm x 0.75 mm 28-Pin LLP n RF Synthesizer System Integrated RF VCO Integrated Loop Filter Low Spurious, Low Phase Noise Fractional-N RF PLL Based on 11-Bit ∆Σ modulator 5 kHz Frequency Resolution Cellular-CDMA LO: 2105.28 MHz to 2155.14 MHz (Requires an External LO /2 Circuit) GPS LO: 2087.73 MHz (Requires an External LO /1.5 Circuit) n IF Synthesizer System Integer-N IF PLL Programmable Charge Pump Current Levels IF LO: 367.20 MHz n Supports Various Reference Oscillator Frequencies: 19.20 MHz/ 19.68 MHz n Low Current Consumption: 22 mA typical at 2.8V n 2.7V to 3.3V Operation n RF Digital Filtered Lock Detect Output n Hardware and Software Powerdown Control LMX2542 includes a Voltage Controlled Oscillator (VCO) for both the Cellular-CDMA and GPS frequency bands, a loop filter, and a Fractional-N RF PLL based on a Delta Sigma (∆Σ) modulator. In concert, these blocks form a closed loop RF synthesizer system. The RF synthesizer system operates from 2087.73 MHz to 2155.14 MHz. LMX2542 includes an Integer-N IF PLL also. For more flexible loop filter designs, the IF PLL includes a 4-level programmable charge pump. Together with an external VCO and loop filter, LMX2542 makes a complete closed loop IF synthesizer system. The default IF frequency is 367.20 MHz. Serial data is transferred to the device via a three-wire MICROWIRETM interface (DATA, LE, CLK). Operating supply voltage ranges from 2.7V to 3.3V. LMX2542 features low current consumption: 22 mA at 2.8V. LMX2542 is available in a 28-Pin Leadless Leadframe Package (LLP). Applications n Cellular-CDMA 1xRTT and IS-95 Mobile Handsets with GPS n Cellular-CDMA 1xRTT and IS-95 Mobile Data Systems with GPS Leadless Leadframe Package (LQA28A) 20082411 PLLatinum™, MICROWIRE™ are trademarks of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS200824 www.national.com LMX2542 PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCOs May 2004 LMX2542 Functional Block Diagram 20082401 www.national.com 2 LMX2542 Connection Diagram Leadless Leadframe Package (LQ) (Top View) 20082402 Note: Analog GND connected through exposed die attached pad. Pin Description Pin No. Pin Name I/O Description 1 Fin I 2 VCC — Power supply bias for the IF PLL analog circuits. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. IF PLL buffer/prescaler input. Small signal input from the VCO. 3 CPout O IF PLL charge pump output. The output is connected to the external loop filter, which drives the input of the IF VCO. 4 NC — No Connect. Do not connect to any node on the printed circuit board. 5 LE I MICROWIRE Latch Enable Input. High impedance CMOS input. When LE transitions from LOW to HIGH, DATA stored in the shift register is loaded into one of 6 internal control registers. 6 CLK I MICROWIRE Clock Input. High impedance CMOS input. DATA is clocked into the 24-bit shift register on the rising edge of CLK. 7 DATA I MICROWIRE Data Input. High impedance CMOS input. Binary serial data. The MSB of DATA is shifted in first. 8 VDD — Power supply bias for the RF VCO. VDD may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 9 NC — No Connect. Do not connect to any node on the printed circuit board. 10 NC — No Connect. Do not connect to any node on the printed circuit board. 11 NC — No Connect. Do not connect to any node on the printed circuit board. 12 NC — No Connect. Do not connect to any node on the printed circuit board. 13 VDD — Power supply bias for the RF VCO. VDD may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 14 VDD — Power supply bias for the RF VCO output buffer. VDD may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 15 RFout O Buffered RF VCO output. 16 VCC — Power supply bias for the RF PLL prescaler. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 3 www.national.com LMX2542 Pin Description (Continued) Pin No. Pin Name I/O 17 VCC — Power supply bias for the RF PLL charge pump. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 18 VCC — Power supply bias for the RF PLL digital circuits. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 19 LD O Digital filtered lock detect output. 20 CE I Chip Enable input. High Impedance CMOS input. When this pin is set HIGH, the RF and IF synthesizer systems are powered up. Powerdown is then controlled through the MICROWIRE. When this pin is set LOW, the device is asynchronously powered down and the IF PLL charge pump output is forced to a high impedance state (TRI-STATE ® ). 21 GND — 22 OSCin I Reference oscillator input. The input is driven by an external AC coupled source. When the OSC_FREQ bit is set LOW, a 19.20 MHz reference frequency should be used. When the OSC_FREQ bit is set HIGH, a 19.68 MHz reference frequency should be used. 23 VCC — Power supply bias for the reference oscillator buffer. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 24 GND — Ground for the reference oscillator buffer. 25 GND — Ground for the IF PLL digital circuits. 26 VCC — Power supply bias for the IF PLL digital circuits. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. 27 NC — No Connect. Do not connect to any node on the printed circuit board. 28 VCC — Power supply bias for the IF PLL buffer/ prescaler. VCC may range from 2.7V to 3.3V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane on the printed circuit board. www.national.com Description Ground for the RF PLL digital circuits. 4 Model RF Min Frequency (MHz) RF Max Frequency (MHz) LMX2542LQX2121 2087.73 LMX2542LQ2121 2087.73 IF Frequency (MHz) Package Marking Packing 2155.14 RF Center Frequency (MHz) ~2121 367.20 25422121 4500 Units on Tape and Reel 2155.14 ~2121 367.20 25422121 1000 Units on Tape and Reel Part Number Description 20082403 5 www.national.com LMX2542 Ordering Information LMX2542 Absolute Maximum Ratings (Notes 1, 2, Recommended Operating Conditions 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC to GND Power Supply Voltage VCC to GND −0.3V to +3.6V VDD to GND −0.3V to +3.6V −0.3V to VCC+0.3V −0.3V to VDD+0.3V Storage Temperature Range (TS) −30˚C to +85˚C Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2kV and is ESD sensitive. Handling and assembly of this device should be done at ESD protected work stations. −65˚C to +150˚C Lead Temperature (solder 4 s) (TL) +2.7V to +3.3V Operating Temperature (TA) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed. Voltage on any pin to GND (VIN) VIN must be < +3.6V +2.7V to +3.3V VDD to GND +260˚C Note 3: GND = 0V. Electrical Characteristics VCC = VDD = CE = 2.8V, TA = +25˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units Icc PARAMETERS ICC + IDD Power Supply Current (RF and IF Synthesizer Systems) RF_EN Bit = 1 IF_EN Bit = 1 OB_CRL[1:0] Word = 00 VCO_CUR[1:0] Word = 11 IF_CUR[1:0] Word = 00 22.0 24.0 mA (ICC + IDD)RF Power Supply Current (RF Synthesizer System) RF_EN Bit = 1 IF_EN Bit = 0 OB_CRL[1:0] Word = 00 VCO_CUR[1:0] Word = 11 20.0 22.0 mA IPD Powerdown Current CE, CLK, DATA and LE = 0V OSCin = 0V (RF_EN Bit = 0 and IF_EN Bit = 0) 20.0 µA 2155.14 MHz RF SYNTHESIZER SYSTEM PARAMETERS RF VCO fRFout RF VCO Operating Frequency (Notes 4, 5) pRFout RF VCO Output Power φeRF RF VCO RMS Phase Error LRF(f) RF VCO Single Side Band Phase Noise www.national.com 2087.73 OB_CRL[1:0] Word = 00 −7.5 −4.5 −1.5 dBm OB_CRL[1:0] Word = 01 −5.0 −2.0 1.0 dBm OB_CRL[1:0] Word = 10 −2.5 0.5 3.5 dBm OB_CRL[1:0] Word = 11 0.0 3.0 6.0 dBm 1.3 Deg. f = 100 kHz Offset TCXO Reference Source OSC_FREQ Bit = 0 or 1 OB_CRL[1:0] Word = 11 IF_EN Bit = 0 −109 −107 dBc/ Hz f = 900 kHz Offset TCXO Reference Source OSC_FREQ Bit = 0 or 1 OB_CRL[1:0] Word = 11 IF_EN Bit = 0 −134 –133 dBc/ Hz 6 LMX2542 Electrical Characteristics (Continued) VCC = VDD = CE = 2.8V, TA = +25˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units RF VCO SPURSRF RF Synthesizer Reference Spurs OSC_FREQ Bit = 0 or 1 IF_EN Bit = 0 −75 dBc HSRF RF VCO Harmonic Suppression 2ND Harmonic OB_CRL[1:0] Word = 11 −25 dBc 3RD Harmonic OB_CRL[1:0] Word = 11 −25 dBc 1.3 ms tRFLOCK Channel Switch Lock Time (Note 6) 1.0 fINITIAL = 2087.73 MHz fFINAL = 2155.14 MHz IF SYNTHESIZER SYSTEM PARAMETERS fFin IF Synthesizer Operating Frequency (Note 7) fφIF IF Synthesizer Phase Detector Frequency pFin IF Synthesizer Input Sensitivity ICPoutIF IF Synthesizer Charge Pump Output Current SPI_DEF Bit = 1 IF_FREQ[1:0] Word = 00 170.76 MHz SPI_DEF Bit = 1 IF_FREQ[1:0] Word = 01 (Default) 367.20 MHz SPI_DEF Bit = 1 IF_FREQ[1:0] Word = 10 440.76 MHz 120 kHz -12 0 dBm IF_CUR[1:0] Word = 00 100 µA IF_CUR[1:0] Word = 01 200 µA IF_CUR[1:0] Word = 10 300 µA IF_CUR[1:0] Word = 11 800 µA REFERENCE OSCILLATOR PARAMETERS fOSCin vOSCin Reference Oscillator Input Operating Frequency (Note 8) OSC_FREQ Bit = 0 19.20 MHz OSC_FREQ Bit = 1 Reference Oscillator Input Sensitivity 0.2 7 19.68 MHz VCC VPP www.national.com LMX2542 Electrical Characteristics (Continued) VCC = VDD = CE = 2.8V, TA = +25˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units DIGITAL INTERFACE (CE, DATA, CLK, LE, LD) VIH High-Level Input Voltage VIL Low-Level Input Voltage 0.8 VDD IIH High-Level Input Current VIH = VDD = VCC IIL Low-Level Input Current VIL = 0V CI Input Capacitance VOH High-Level Output Voltage VDD V 0.8 VCC VCC V 0 0.2 VDD V 0 0.2 VCC V 10 µA −10 µA 3.0 pF 0.9 VDD V 0.9 VCC VOL CO Low-Level Output Voltage Output Capacitance V 0.1 VDD V 0.1 VCC V 5.0 pF MICROWIRE INTERFACE tCS DATA to CLK Set Up Time 50.0 ns tCH DATA to CLK Hold Time 10.0 ns tCWH CLK Pulse Width HIGH 50.0 ns tCWL CLK Pulse Width LOW 50.0 ns tES CLK to LE Set Up Time 50.0 ns tEW LE Pulse Width 50.0 ns Note 4: For other RF frequency ranges, please contact National Semiconductor Corporation. Note 5: When the Cellular-CDMA mode is used, an external /2 circuit is required before the Cellular mixer LO port. Furthermore, if an external /1.5 circuit is available before the GPS mixer LO port, the GPS frequency of 1391.82 MHz can be achieved by using a fixed RF frequency of 2087.73 MHz. Note 6: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/- 1 kHz of the final frequency. tLOCK = tFINAL − tINITIAL. Note 7: For frequencies other than the default values, the SPI_DEF bit should be set to 0 and registers R4 and R5 programmed appropriately. Refer to Section 2.2.5 for further details on how to program the SPI_DEF bit. Note 8: For other reference oscillator frequencies, please contact National Semiconductor Corporation. www.national.com 8 LMX2542 Typical Performance Characteristics IF PLL Input Impedance VDD = VCC = 2.8V, TA = 25˚C RF VCO Output Impedance VDD = VCC = 2.8V, TA = 25˚C 20082412 20082413 RFout (MHz) R Ω jX Ω |R + jX| Ω Fin (MHz) R Ω jX Ω |R + jX| Ω 2087.73 26.406 −34.650 46.564 170.76 33.789 −239.220 241.595 2105.28 25.385 −30.800 39.913 367.20 26.992 −137.620 140.242 2121.00 23.898 −28.122 36.905 440.76 27.844 −126.470 129.499 2155.14 19.979 −23.102 30.543 9 www.national.com LMX2542 Serial Data Input Timing 20082404 Notes: 1. 2. www.national.com DATA is clocked into the 24-bit shift register on the rising edge of CLK. The MSB of DATA is shifted in first. 10 LMX2542 is a highly integrated, high performance, low power, frequency synthesizer system optimized for CellularCDMA 1xRTT and IS-95 mobile handsets and data systems with GPS capabilities. Using a proprietary digital phase locked loop technique, LMX2542 generates very stable, low noise local oscillator (LO) signals for up and down conversion in wireless communications devices. RF_B : Preset divide ratio of the RF PLL binary 4-bit programmable counter (2 ≤ RF_B ≤ 15) RF_FN : Preset numerator of the RF PLL binary 11-bit modulus counter (0 ≤ RF_FN < 1920 for fOSCin = 19.20 MHz) LMX2542 includes a Voltage Controlled Oscillator (VCO) for the Cellular-CDMA and GPS frequency bands, a loop filter, and a Fractional-N RF PLL based on a ∆Σ modulator which supports frequency resolutions as low as 5 kHz. In concert, these blocks form a closed loop RF synthesizer system. The RF synthesizer system operates from 2087.73 MHz to 2155.14 MHz. The need for external components is limited to a few passive elements for matching the RF output impedance, and bypass elements for power line stabilization. The Fractional-N RF PLL (∆Σ modulator architecture) delivers low spurious thus providing a significant improvement over other PLL solutions. In addition, the Fractional-N RF PLL facilitates faster lock times, which reduces power consumption and system set-up time. Furthermore, the RF loop filter occupies a much smaller area as opposed to the Integer-N architecture. This allows the RF loop filter to be embedded into the circuit, thus minimizing the external noise coupling. LMX2542 includes an Integer-N IF PLL also. For more flexible loop filter designs, the IF PLL includes a 4-level programmable charge pump. Together with an external VCO and loop filter, LMX2542 makes a complete closed loop IF synthesizer system. The default IF frequency is 367.20 MHz. The circuit also supports commonly used reference oscillator frequencies of 19.20 MHz and 19.68 MHz. (0 ≤ RF_FN < 1968 for fOSCin = 19.68 MHz) Note: When the FREQ_OFF bit is set to 1, frequencies with 5 kHz resolution can be generated. In the same way outlined above, the divide ratio for the desired frequency less 5 kHz should be programmed. When the FREQ_OFF bit (R1[2]) is set to 1, the programmed frequency will be shifted by +5 kHz in order to achieve the desired frequency. Refer to Section 2.3.1 for details on how to program the FREQ_OFF bit. 1.1.2 IF Frequency Selection The IF synthesizer divide ratio can be calculated using the following equation: 20082409 where: IF_A < IF_B 1.1 FREQUENCY GENERATION 1.1.1 RF Frequency Selection The RF synthesizer (Cellular-CDMA) divide ratio can be calculated using the following equation: fFin : IF VCO output frequency fOSCin : Reference oscillator frequency IF_A : Preset divide ratio of the IF PLL binary 4-bit swallow counter (0 ≤ IF_A ≤ 15) IF_B : Preset divide ratio of the IF PLL binary 9-bit programmable counter (1 ≤ IF_B ≤ 511) IF_R : Preset divide ratio of the IF PLL binary 9-bit programmable reference counter (2 ≤ IF_R ≤ 511) 20082407 where: RF_A < RF_B fRFout : RF VCO output frequency fOSCin : Reference oscillator frequency RF_A : Preset divide ratio of the RF PLL binary 3-bit swallow counter (0 ≤ RF_A ≤ 7) From the above equation and with the SPI_DEF bit set to 1, LMX2542 generates a fixed IF frequency of 367.20 MHz as follows: 11 fFin (MHz) IF_B IF_A fOSCin / IF_R (kHz) 367.20 191 4 120 www.national.com LMX2542 1.0 Functional Description LMX2542 1.0 Functional Description (Continued) 1.2 VCO FREQUENCY TUNING The center frequency of the RF VCO is determined mainly by the resonant frequency of the tank circuit. This tank circuit is implemented on-chip and requires no external inductor. LMX2542 actively tunes the tank circuit to the required frequency with the built-in tracking algorithm. 1.3 POWER CONTROL LMX2542 includes a powerdown mode to reduce the power consumption. LMX2542 can be powered down when the CE pin is set LOW, independent of the state of the powerdown bits. When CE is set HIGH, powerdown is controlled through the MICROWIRE. The RF and IF circuitries are individually powered down by setting the RF_EN (R1[3]) and IF_EN (R2[2]) bits LOW respectively. Refer to Section 2.3.2 and Section 2.4.1 for details on how to program the RF_EN and IF_EN bits. www.national.com CE Pin RF_EN IF_EN RF Circuitry IF Circuitry 0 X X OFF OFF 1 0 0 OFF OFF 1 0 1 OFF ON 1 1 0 ON OFF 1 1 1 ON ON Note: 1. X refers to a don’t care condition. 2. The RF circuitry includes the whole RF synthesizer system (synthesizer and VCO). 3. The IF circuitry includes the IF synthesizer block only. 12 LMX2542 1.0 Functional Description (Continued) 1.4 RF DIGITAL FILTERED LOCK DETECT for 4 consecutive PFD comparison cycles, the RF PLL enters a locked state and the LD output is then forced HIGH. Once the phase error becomes greater than 10 ns (∆t > tW) the RF PLL falls out of lock and the LD is forced LOW (∼GND). The phase error in Figure 2 is measured on the leading edge. If the phase difference between the two inputs to the PFD is equal to 10 ns (∆t = tW), then the LD output becomes unpredictable. Refer to Section 2.2.4 for further details on how to program the digital filtered lock detect. Note: fR is the PFD input from the reference oscillator and fN is the PFD input from the programmable feedback divider (N counter). A digital filtered lock detect status genrated from the RF phase frequency detector (PFD) is available on the LD pin (Pin 19) when the RF_LD bit (R0[21]) is set to 1. The LD output is therefore used to indicate the lock status of the RF synthesizer system. Furthermore, the LD output can be forced to GND at all times when the RF_LD bit is set to 0. When used as a lock detect output, the two inputs to the PFD, fN and fR, are first divided by 64. The lock detect digital filter then compares the difference between the phases of the inputs to the PFD to an RC generated delay of approximately 10 ns. This delay is represented by tW in Figure 1 and Figure 2 below. If the phase error is less than 10 ns (∆t < tW) 20082406 FIGURE 1. Lock Detect Flow Diagram 13 www.national.com LMX2542 1.0 Functional Description (Continued) 20082405 FIGURE 2. Lock Detect Timing Diagram Waveform 1.5 MICROWIRE SERIAL INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The interface comprises three signal pins: CLK, DATA, and LE. Serial data is clocked into the 24-bit shift register on the rising edge of CLK. The least significant bits decode the internal control register address. www.national.com When LE transitions from LOW to HIGH, DATA stored in the shift registers is loaded into one of six control registers. The MSB of DATA is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0. 14 LMX2542 2.0 Programming Description 2.1 MICROWIRE INTERFACE The MICROWIRE Serial Port Interface (SPI) has a 24-bit shift register to store the incoming DATA bits temporarily. The incoming DATA is loaded into the shift register from MSB to LSB. The data is shifted at the rising edge of the CLK signal. When the LE signal transitions from LOW to HIGH, the DATA stored in the shift register is transferred to the proper register depending on the state of the ADDRESS bits. The selection of the particular register is determined by the address bits equal to the binary representation of the number of the control register. At start-up, the 24-bit shift register is loaded via the MICROWIRE interface. The loading requires 3 default words, with register R2 loaded first, and R0 loaded last. Once loaded, the RF VCO frequency can then be changed by only programming register R0 appropriately. If an IF frequency other than the default value is desired, the SPI_DEF bit should be set to 0, and registers R4 and R5 programmed appropriately. 2.1.1 Control Register Content Map The control register content map describes how the bits within each control register are allocated to specific control functions. The bits that are marked 0 should be programmed as such to ensure proper device operation. Reg 23 22 21 20 19 18 17 16 15 MSB R0 SPI_ DEF 1 RF_ LD 0 R1 1 1 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SHIFT REGISTER BIT LOCATION RF_B [3:0] 1 0 0 RF_A [2:0] 0 1 R2 1 1 0 0 1 0 0 1 0 R3 0 0 0 0 0 0 0 0 0 0 RF_FN [10:0] 1 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 VCO_CUR [1:0] 0 IF_A [3:0] 0 0 OSC_ FREQ 1 1 0 FREQ_ OFF 0 1 IF_ EN 1 0 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 OB_CRL [1:0] IF_FREQ [1:0] 0 0 0 0 0 0 0 0 0 0 R5 0 0 0 0 0 0 0 0 0 0 R6 0 0 0 0 0 0 0 1 1 1 IF_R [8:0] 1 1 1 1 1 1 1 1 0 RF_ EN IF_CUR [1:0] 1 IF_B [8:0] R4 0 LSB Note: Numbers in Bold represent the ADDRESS bits. 15 www.national.com LMX2542 2.0 Programming Description (Continued) 2.2 R0 REGISTER The R0 register contains the RF_FN, RF_A, RF_B, RF_LD, and SPI_DEF control words. The register address bits are R0[1:0] = 00. The detailed descriptions and programming information for each control word is discussed in the following sections. Reg 23 22 21 20 19 18 17 16 15 14 MSB 13 12 11 10 9 8 7 6 5 4 3 2 1 RF_ LD RF_B [3:0] 0 0 LSB ADDRESS [1:0] FIELD DATA[21:0] FIELD R0 SPI_ DEF 1 SHIFT REGISTER BIT LOCATION RF_A [2:0] RF_FN [10:0] 0 0 2.2.1 RF_FN[10:0] - RF Synthesizer Fractional Numerator Counter (R0[2:12]) The RF_FN control word is used to setup the 11-bit ∆Σ modulator. This corresponds to programming the fractional numerator counter portion of the RF feedback divider. The value programmed is dependent on the reference oscillator used. 2.2.1.1 Programming RF_FN[10:0] Using 19.20 MHz Reference Oscillator When a 19.20 MHz reference oscillator is used (OSC_FREQ bit = 0), the RF_FN can be programmed to values ranging from 0 to 1919. Numerator RF_FN[10:0] fOSCin = 19.20 MHz 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 • • • • • • • • • • • • 1919 1 1 1 0 1 1 1 1 1 1 1 2.2.1.2 Programming RF_FN[10:0] Using 19.68 MHz Reference Oscillator Similarly, when a 19.68 MHz reference oscillator is used (OSC_FREQ bit = 1), the RF_FN can be programmed to values ranging from 0 to 1967. Numerator RF_FN[10:0] fOSCin = 19.68 MHz 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 • • • • • • • • • • • • 1967 1 1 1 1 0 1 0 1 1 1 1 2.2.2 RF_A[2:0] - RF Synthesizer Swallow Counter (A Counter) (R0[13:15]) The RF_A control word is used to setup the RF synthesizer’s A counter. The A counter is a 3-bit swallow counter used in the programmable feedback divider. The RF_A control word can be programmed to values ranging from 0 to 7. Divide Ratio www.national.com RF_A[2:0] RF Mode 2 1 0 0 0 0 0 1 0 0 1 • 7 • 1 • 1 • 1 16 (Continued) 2.2.3 RF_B[3:0] - RF Synthesizer Programmable Binary Counter (B Counter) (R0[16:19]) The RF_B control word is used to setup the RF synthesizer’s B counter. The B counter is a 4-bit programmable binary counter used in the programmable feedback divider. The RF_B control word can be programmed to values ranging from 2 to 15. Divide ratios less than 2 are prohibited. Divide Ratio RF_B[3:0] 3 2 1 0 2 0 0 1 0 3 0 0 1 1 • 15 • 1 • 1 • 1 1 • 2.2.4 RF_LD - RF Synthesizer System Lock Detect (R0[21]) The RF_LD bit is used to indicate the lock status of the RF synthesizer system. Control Bit RF_LD Register Location R0[21] Description RF Synthesizer System Lock Detect Function 0 1 Hard Zero (GND) Lock Detect 2.2.5 SPI_DEF - Serial Port Interface Default Register Selection (R0[23]) The SPI_DEF bit selects between using the default IF counter values and user programmable values. Control Bit Register Location Description Function 0 SPI_DEF R0[23] Serial Port Interface Default Register Selection 17 Default Counter Values OFF. Program Registers R0 through R6 1 Default Counter Values ON. Program Registers R0 through R2 www.national.com LMX2542 2.0 Programming Description LMX2542 2.0 Programming Description (Continued) 2.3 R1 REGISTER The R1 register contains the FREQ_OFF, RF_EN and OB_CRL control words. The register address bits are R1[1:0] = 01. The detailed descriptions and programming information for each control word is discussed in the following sections. Reg 23 22 21 20 19 18 17 16 15 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 1 0 1 0 0 0 1 0 1 0 0 LSB ADDRESS [1:0] FIELD DATA[21:0] R1 1 SHIFT REGISTER BIT LOCATION 1 0 1 0 0 1 OB_CRL [1:0] RF_ EN FREQ_ OFF 0 1 2.3.1 FREQ_OFF - RF Synthesizer System Frequency Offset (R1[2]) The FREQ_OFF bit is used to offset the RF frequency by +5 kHz. Control Bit Register Location FREQ_OFF R1[2] Description Function 0 RF Synthesizer System Frequency Offset 1 RF Synthesizer System Frequency Offset Disabled RF Synthesizer System Frequency Offset Enabled 2.3.2 RF_EN - RF Synthesizer System Enable (R1[3]) The RF_EN bit is used to switch the RF synthesizer system (PLL and VCO) between a powered up and powered down mode. Control Bit Register Location Description Function 0 RF_EN R1[3] RF Synthesizer System Enable 1 RF Synthesizer System Powered Down RF Synthesizer System Active 2.3.3 OB_CRL[1:0] - RF VCO Output Buffer Power Control (R1[5:4]) The OB_CRL word is used to set the RF VCO output buffer power level. The power level can be set according to the system requirements. RF VCO Output Buffer Power Level (dBm) OB_CRL[1:0] www.national.com 0 0 −4.5 0 1 −2.0 1 0 0.5 1 1 3.0 18 (Continued) 2.4 R2 REGISTER The R2 register contains the IF_EN, IF_CUR, IF_FREQ, OSC_FREQ, and VCO_CUR control words. The register address bits are R2[1:0] = 10. The detailed descriptions and programming information for each control word is discussed in the following sections. Reg 23 22 21 20 19 18 17 16 15 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 0 0 1 0 0 1 0 0 0 0 0 0 LSB ADDRESS [1:0] FIELD DATA[21:0] FIELD R2 1 SHIFT REGISTER BIT LOCATION 0 VCO_CUR [1:0] OSC_ FREQ IF_FREQ [1:0] IF_CUR [1:0] IF_ EN 1 0 2.4.1 IF_EN - IF Synthesizer Enable (R2[2]) The IF_EN bit is used to switch the IF synthesizer between a powered up and powered down mode. Control Bit Register Location Description Function 0 IF_EN R2[2] IF Synthesizer Enable 1 IF Synthesizer Powered Down IF Synthesizer Active 2.4.2 IF_CUR[1:0] - IF Synthesizer Charge Pump Current Gain (R2[4:3]) The IF_CUR control word is used to set the IF synthesizer’s charge pump current gain. Four gain levels are available. IF Synthesizer Charge Pump Current Gain (µA) IF_CUR[1:0] 0 0 100 0 1 200 1 0 300 1 1 800 2.4.3 IF_FREQ[1:0] - IF Synthesizer Fixed Frequency Selection (R2[6:5]) The IF_FREQ control word is used to set the default fixed IF frequency applicable to the specific CDMA system. For LMX2542, the default fixed IF frequency is 367.20 MHz. IF_FREQ[1:0] Fixed IF Frequency (MHz) 0 0 170.76 0 1 367.20 1 0 440.76 2.4.4 OSC_FREQ - Reference Oscillator Frequency Select (R2[7]) The OSC_FREQ bit is used to select the appropriate reference oscillator frequency. Control Bit Register Location Description Function 0 OSC_FREQ R2[7] Reference Oscillator Select 19 19.20 MHz Reference Oscillator Selected 1 19.68 MHz Reference Oscillator Selected www.national.com LMX2542 2.0 Programming Description LMX2542 2.0 Programming Description (Continued) 2.4.5 VCO_CUR[1:0] - RF VCO Dynamic Current (R2[9:8]) The VCO_CUR control word is used to set the dynamic current for the RF VCO. A maximum dynamic current is recommended, and is achieved when VCO_CUR[1:0] word = 11. VCO_CUR[1:0] RF VCO Current Magnitude 0 0 Minimum • • 1 • • 1 • • Maximum 2.5 R3 REGISTER The R3 register is used for internal testing of the device and is not intended for customer use. The register address bits are R3[2:0] = 011. Register R3 is active only when the SPI_DEF bit in Register R0 is set to 0. Reg 23 22 21 20 19 18 17 16 15 14 MSB 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 1 0 LSB ADDRESS [2:0] FIELD DATA[20:0] FIELD R3 1 SHIFT REGISTER BIT LOCATION 0 1 0 0 1 0 0 1 0 0 1 1 2.6 R4 REGISTER The R4 register contains the IF_B and IF_A control words. The register address bits are R4[3:0] = 0111. Register R4 is active only when the SPI_DEF bit in Register R0 is set to 0. Regsiter R4 should only be used to set the IF N counter if the default value is not desired. The detailed descriptions and programming information for each control word is discussed in the following sections. Reg 23 22 21 20 19 18 17 16 15 14 MSB 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 LSB ADDRESS [3:0] FIELD DATA[19:0] R4 1 SHIFT REGISTER BIT LOCATION IF_A [3:0] IF_B [8:0] 0 1 1 1 2.6.1 IF_B[8:0] - IF Synthesizer Programmable Binary Counter (B Counter) (R4[12:4]) The IF_B control word is used to setup the IF synthesizer’s B counter. The B counter is a 9-bit programmable binary counter used in the programmable feedback divider. The IF_B control word can be programmed to values ranging from 1 to 511. Divide ratios less than 1 are prohibited. Divide Ratio IF_B[8:0] 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 0 • • • • • • • • • • 511 1 1 1 1 1 1 1 1 1 2.6.2 IF_A[3:0] - IF Synthesizer Swallow Counter (A Counter) (R4[16:13]) The IF_A control word is used to setup the IF synthesizer’s A counter. The A counter is a 4-bit swallow counter used in the programmable feedback divider. The IF_A control word can be programmed to values ranging from 0 to 15. Divide Ratio IF_A[3:0] 3 2 1 0 0 0 0 0 0 1 0 0 0 1 • 15 • 1 • 1 • 1 • 1 www.national.com 20 (Continued) 2.7 R5 REGISTER The R5 register contains the IF_R control word. The register address bits are R5[4:0] = 01111. Register R5 is active only when the SPI_DEF bit in Register R0 is set to 0. Regsiter R5 should only be used to set the IF R counter if the default value is not desired. The detailed description and programming information for this control word is discussed in the following section. Reg 23 22 21 20 19 18 17 16 15 14 MSB 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 0 0 0 LSB ADDRESS [4:0] FIELD DATA[18:0] FIELD R5 2 SHIFT REGISTER BIT LOCATION IF_R [8:0] 0 0 1 1 1 1 2.7.1 IF_R[8:0] - IF Synthesizer Programmable Reference Divider (R5[13:5]) The IF_R control word is used to setup the IF synthesizer’s reference divider. The IF_R control word can be programmed to values ranging from 2 to 511. Divide ratios less than 2 are prohibited. Divide Ratio IF_R[8:0] 8 7 6 5 4 3 2 1 0 2 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 1 1 • • • • • • • • • • 511 1 1 1 1 1 1 1 1 1 2.8 R6 REGISTER The R6 register is used for internal testing of the device and is not intended for customer use. The register address bits are R6[5:0] = 011111. Register R6 is active only when the SPI_DEF bit in Register R0 is set to 0. Reg 23 22 21 20 19 18 17 16 15 MSB 14 13 12 11 10 9 8 7 6 5 4 0 2 1 0 0 0 0 0 0 1 1 1 1 0 LSB ADDRESS [5:0] FIELD DATA[17:0] FIELD R6 3 SHIFT REGISTER BIT LOCATION 1 21 1 1 1 1 1 1 0 1 1 1 1 1 www.national.com LMX2542 2.0 Programming Description LMX2542 PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCOs Physical Dimensions inches (millimeters) unless otherwise noted 28-Pin Leadless Leadframe Package (LLP) NS Package Number LQA28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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