Features • • • • Operating Supply Range 3.0V to 3.6V Power Dissipation 1W Max Low-power Sleep Mode (<0.5 mW) RF Data Channel – Automatic Gain Control or Programmable Gain Mode – Wide Bandwidth VGA – VGA Accepts Inputs from 30–300 mV Peak-to-peak Differential (PPD), 60–600 mV PPD or 110–1100 mVPPD – Programmable Equalization via 7th-order Equiripple Filter with Programmable Symmetric Zeros – Programmable 5-to-1 Filter Cutoff Range – Data Slicer with DC Restore Circuit – Wide Frequency Range Clock Extraction – Frequency Synthesizer with Independent 7-bit M and 6-bit N Dividers, Better than 1% Resolution – Highly Programmable to Accommodate DVD (1–5X) and CD (6–30X) – Write Asymmetry Measurement for Adjusting Write-mode Power – Data Recovery Supports CLV, ZCLV, ZCAV Recording – Optional Internally-generated Timing for AGC and Timing Recovery • Synthesizer Functions – Supports Wobble Clock Synthesis, Using Low-jitter PLL • Servo Algebra and OPC Functions – 45 MHz Bandwidth for Differential Phase Tracking Detector – Land and Groove Detector for DVD RAM – Supports One Beam Push/Pull Tracking Output – Supports One Beam Differential Phase Tracking – Supports Three-beam Push/Pull Tracking Output, Using E, F, G, H – Focus Error Signal Output – Focus OK Signal – Track Crossing Detection – Mirror Signal Output – Wobble Detection for DVD RAM, DVD-RW, DVD-R – Detects Tracking Error OK – Provides Sample and Hold Functions for CD and DVD OPC – Formats Pre-pit Data, Using Raw Pre-pit Information from AT78C1503 • Header Detection for DVD RAM DVD/CD Read Channel AT78C1503 AT78C1507 Description The AT78C1503 is a programmable DVD/CD channel responsible for servo algebra, gain control, equalization, bit detection and clock extraction for CD-ROM, DVD-ROM, DVD-R, DVD-RW and DVD-RAM formats. Programmable features allow data rates up to 5X DVD. Also, for DVDRAM functionality, the channel serves the write path providing laser power control and pit asymmetry detection. Up to 2X DVD write speeds are supported for DVD-R, DVD-RW and DVDRAM. The extracted wobble frequency is supplied to the AT78C1507 companion chip which in turn synthesizes the write clock. The AT78C1507 is the companion chip to the AT78C1503 – DVD/CD Read Channel – and the AT78C1504 – DVD/CD Automatic Laser Power Controller. Working in conjunction with the read channel, the AT78C1507 is responsible for wobble clock synthesis for DVD-R and DVD-RAM formats. In addition, the two parts working together also support pre-pit data and clock recovery for the DVD-R format. Four separate inputs are provided to enable the AT78C1507 to perform tracking servo algebra, using just the outrigger photo detector signals (E, F, G, H for example) coming from the OPU. This extends the range of supported tracking servo algebra functions for the 1503-1507 combination. Lastly, OPC capability is supported for efficient writing of DVD-R, DVD-RAM and CD-R disks. Based on CMOS technology, both the AT78C1503 and AT78C1507 operate from a single 3.3V supply and are fully programmable through serial interfaces for both CD and DVD modes. Rev. 2054A–DVD–07/02 1 Figure 1. DVD System Block Diagram DRAM Flash AT78C1501 ATAPI I/F Controller DBM ECC SRAM ARM7TDMI AT78C1502 Servo Control System Sled Focus AT78C1503 Read Channel AT78C1507 Read Channel Adj. 2 Power Drivers Spindle Laser AT78C1504 Laser Power Controller T08XX Laser Amp AT78C1505 Pre-amp DVD/CD Read Channel 2054A–DVD–07/02 DVD/CD Read Channel Figure 2. AT78C1503 Block Diagram CAGC 100 SERREG AGCLZ 98 (RF Sequencer) Control FREQUENCY SYNTHESIZER AGC CONTROL 70 DATA7 AGCHLD 94 FCDAC REG9 <4 0> 58 FREF DATA PLL BST1 / BST2 REG 8 69 DATA6 68 DATA5 67 DATA4 RFGEN RFP/N 2/3 7th ORDER FILTER/ EQUALIZER VGA MUX 66 DATA3 VGA 65 DATA2 64 DATA1 Sum of Selectable Buffer FO1P/N 4/5 Sum of Difference 63 DATA0 VGA FO2P/N 6/7 VGA TR1P/N 8/9 VGA 10/ TR2P/N 11 DC RESTORE 62 RCLK 01 IDFIELD DIFFERENTIAL TRACKING DETECTOR VGA AGC Control Voltage MUX TRACK OK 48 TOK TRACK ZERO CROSS 47 TZC DTR2 Sum of Selectable Buffer AUTO INV 28 TE MUX Slow Arithmetic D/SE 09 RDSZ 44 WOBBLE and Normalization D/SE Push/Pull D/SE 45 ID12 46 ID34 Tracking D/SE Focus Error Mirror Detector Wobble Detector Land-groove FO1-CD 16 FO2-CD 17 TR1-CD 18 27 FE FOCUS OK 50 MIRROR 29 SLOWSUM Detector TR2-CD 19 49 FOK 59 RFDROP REXT 13 VREF 41 RG SERIAL REGISTER TEST / 127 MODE CONTROL 77 WG 93 82 P N TP3 85 84 P N TP4 51 53 52 ATA 91 90 P N TP2 CLK 93 92 P N TP1 NA 40 PD 3 2054A–DVD–07/02 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CACG RDSZ ACGLZ VDD10 VSS10 AGCFST AGCHLD TP1P TP1N TP2P TP2N VSS2 VDD2 CDCRP CDCRN TSDDTP2P TSDDTP2N TSDDTP1P TSDDTP1N TRSIN1P TRSIN1N TRSIN2P TRSIN2N WG WCLK Figure 3. AT78C1503 Pin-out 01 IDFEILD TRCST 75 02 RFP VDD3 74 03 RFN VSS3 73 04 FO1P VDD11 72 05 FO1N VSS11 71 06 FO2P DATA7 70 07 FO2N DATA6 69 08 TR1P DATA5 68 09 TR1N DATA4 67 10 TR2P DATA3 66 11 TR2N DATA2 65 12 FOHG DATA1 64 13 REXT DATA0 63 14 VDD1 RCLK 62 15 VSS1 RFDROP 61 16 FO1_CD VDD5 60 17 FO2_CD VSS5 59 18 TR1_CD FREF 58 19 TR2_CD VDD7 57 20 VDD6 VSS7 56 21 SS_H VDD4 55 22 VSS6 VSS4 54 23 REFFRONT SCLK 53 24 REFBACK SDATA 52 25 LENSPOS SENA 51 IDINT PD RG VSS9 VDD9 WOBBLE ID12 ID34 TZC TOK FOK MIRROR 40 41 42 43 44 45 46 47 48 49 50 BWUP 37 39 ADCSTRT 36 BWDWN SHLD 35 38 LHIPWR VSS8 31 34 PORB 30 IDSEL SLOWSUM 29 33 TE 28 VDD8 FE 27 32 ATP1 26 AT78C1503 Table 1. AT78C1503 Pin List 4 Pin # Pin Name Type Description 1 IDFIELD Digital Output Signal to Preamp to Drive ID Select 2 RFP Analog Input High-speed Signal Input 3 RFN Analog Input High-speed Signal Input 4 FO1P Diff Input Focus 1 Pos 5 FO1N Diff Input Focus 1 Neg 6 FO2P Diff Input Focus 2 Pos 7 FO2N Diff Input Focus 2 Neg 8 TR1P Diff Input Track 1 Pos 9 TR1N Diff Input Track 1 Neg 10 TR2P Diff Input Track 2 Pos 11 TR2N Diff Input Track 2 Neg DVD/CD Read Channel 2054A–DVD–07/02 DVD/CD Read Channel Table 1. AT78C1503 Pin List (Continued) Pin # Pin Name Type Description 12 FOHG Digital Input Focus High Gain 13 REXT Passive Passive for 0 TC Current Reference (16.5 K_, 1%) 14 VDD1 3.3V Supply DPD, IBIAS 15 VSS1 0V Supply DPD, IBIAS 16 FO1_CD Analog Input Focus 1, CD Input 17 FO2_CD Analog Input Focus 2, CD Input 18 TR1_CD Analog Input Track 1, CD Input 19 TR2_CD Analog Input Track 2, CD Input 20 VDD6 3.3V Supply Slow Servo Analog 21 SS_H Digital Input Servo Sample and Hold 22 VSS6 0V Supply Slow Servo Analog 23 REFFRONT Input/Output Servo Front-end Reference Level 24 REFBACK Input/Output Servo back-end Reference Level 25 LENSPOS Analog Input Lens Position Error Input 26 ATP1 Analog Output Servo Analog Test Point 27 FE Analog Output Focus Error Output 28 TE Analog Output Tracking Error Output 29 SLOWSUM Analog Output Low-pass Filtered Sum of Photodetector Outputs 30 PORB Digital Input Power-on Reset, Bar (active-low) 31 VSS8 0V Supply Servo DACs 32 VDD8 3.3V Supply Servo DACs 33 IDSEL Digital Input ID Field Select 34 LHIPWR Digital Input Laser High Power 35 SHLD Digital Input Servo Hold 36 ADCSTRT Digital Input Start On-chip 6-bit ADC 37 BWUP Digital Input Bandwidth Up 38 BWDN Digital Input Bandwidth Down 39 IDINT Digital Input Mode Select of Sequencer 40 PD Digital Input Power-down 41 RG Digital Input User Data Read Gate 42 VSS9 0V Supply Servo DAC Rings 43 VDD9 3.3V Supply Servo DAC Rings 44 WOBBLE Digital Output Wobble Detect Output 45 ID12 Digital Output ID Field 12 Detected 46 ID34 Digital Output ID Field 34 Detected 47 TZC Digital Output Track Zero Crossing 5 2054A–DVD–07/02 Table 1. AT78C1503 Pin List (Continued) 6 Pin # Pin Name Type Description 48 TOK Digital Output Track OK 49 FOK Digital Output Focus OK 50 MIRROR Digital Output Mirror Detect (ROM)/Mirror Field Detect (RAM) 51 SENA Digital Input Serial Data Enable; Must Be High to Read or Write Serial Registers 52 SDATA Input/Output Serial Data, Input (write data) or Output (read data) 53 SCLK Digital Input Serial Data Clock 54 VSS4 0V Supply ESD Ring, Digital Ring 55 VDD4 3.3V Supply ESD Ring, Digital Ring 56 VSS7 0V Supply Slow Servo Digital, Synthesizer Dividers 57 VDD7 3.3V Supply Slow Servo Digital, Synthesizer Dividers 58 FREF Digital Input Reference Clock Input to Synthesizer 59 VSS5 0V Supply Digital I/O Supply 60 VDD5 3.3V Supply Digital I/O Supply 61 RFDROP Digital Output RF Dropout Detected 62 RCLK Digital Output Recovered Clock Divided by 4 or 8 63 DATA0 Digital Output Recovered Data Out, Bit 0 (last in time) 64 DATA1 Digital Output Recovered Data Out, Bit 1 65 DATA2 Digital Output Recovered Data Out, Bit 2 66 DATA3 Digital Output Recovered Data Out, Bit 3 67 DATA4 Digital Output Recovered Data Out, Bit 4 68 DATA5 Digital Output Recovered Data Out, Bit 5 69 DATA6 Digital Output Recovered Data Out, Bit 6 70 DATA7 Digital Output Recovered Data Out, Bit 7 (first in time) 71 VSS11 0V Supply Digital I/O Ring 72 VDD11 3.3V Supply Digital I/O Ring 73 VSS3 0V Supply TR CML, Synthesizer CML, DC Restore 74 VDD3 3.3V Supply TR CML, Synthesizer CML, DC Restore 75 TRCST Digital Input Timing Recovery Coast 76 WCLK Digital Output Write Clock 77 WG Digital Input Write Gate (enables write clock) 78 TRSIN2N Diff Input Timing Recovery/Synthesizer Test Input 79 TRSIN2P Diff Input Timing Recovery/Synthesizer Test Input 80 TRSIN1N Diff Input Timing Recovery/Synthesizer Test Input 81 TRSIN1P Diff Input Timing Recovery/Synthesizer Test Input 82 TSDDTP1N Test Output TR/Detector/Phase Detector Test Input DVD/CD Read Channel 2054A–DVD–07/02 DVD/CD Read Channel Table 1. AT78C1503 Pin List (Continued) Pin # Pin Name Type Description 83 TSDDTP1P Test Output TR/Detector/Phase Detector Test Point 84 TSDDTP2N Test Output TR/Detector/Phase Detector Test Input 85 TSDDTP2P Test Output TR/Detector/Phase Detector Test Input 86 CDCRN Diff Passive Detector Duty Cycle Feedback Cap 87 CDCRP Diff Passive Detector Duty Cycle Feedback Cap 88 VDD2 3.3V Supply RF Front-end Ring 89 VSS2 0V Supply RF Front-end Ring 90 TP2N Diff Output Test Point 2 Output 91 TP2P Diff Output Test Point 2 Output 92 TP1N Diff Output Test Point 1 Output 93 TP1P Diff Output Test Point 1 Output 94 AGCHLD Digital Input AGC Hold Input 95 AGCFST Digital Input AGC Fast Recovery Input 96 VSS10 0V Supply AGC, LPF 97 VDD10 3.3V Supply AGC, LPF 98 AGCLZ Digital Input Low Z Control for AGC Input 99 RDSZ Analog Output AGC Cap/Detector Cap Voltage Outputs 100 CAGC Passive External Capacitor for AGC Loop Table 2. Supply Pins Supply Pin Circuitry VDD/SS1 DPD, IBIAS, RTRIM VDD/SS2 RF Front-end Ring VDD/SS3 TR & Synth CML, DC Restore, RF Dropout Analog VDD/SS4 ESD & Digital Ring VDD/SS5 Digital I/O Supply VDD/SS6 Servo Analog VDD/SS7 Servo, Synth and RF Dropout Digital, CMOSTPMUX, Serial Registers 1 and 3, Calibrator VDD/SS8 Servo DACs VDD/SS9 Servo DAC Rings VDD/SS10 AGC, LPF VDD/SS11 Digital I/O Ring 7 2054A–DVD–07/02 Figure 4. AT78C1507 Block Diagram – Wobble PLL and OPC Sample and Hold 75 SFLTP WBLIN SFLTN Phase/Frequency Comparator 87 86 VCO Q Pump 1/(P+1) WOBBLE 76 WOBLE X 186 1/186 WCLK WOB2X SELOPC CD/DVD 37 Reg50 <3:2> PCLK SHCD S&H 19 OPCOUT for MUX 38 61 27 OPC SHDVD DVDOPC WOBBLE + 180 DEG 18 98 CDOPC PTSEL RS Q 95 94 8 PTOP D FF PDATA 62 MUX PBOT DVD/CD Read Channel 2054A–DVD–07/02 DVD/CD Read Channel Figure 5. AT78C1507 – Tracking Error Path SHSB 21 "E" P/N GSEL Reg 49<7:4> Sample & Hold 4/5 D2SE BWSEL Reg 49<3:0> SE TP2 29 Reg. 51–58 <7:3> Gain & Offset Adj V21 BW/LPF Reg. 62–65 SE TP2 30 "F" P/N Sample & Hold 6/7 D2SE V21 BW/LPF (E+F) − (G+H) + Normalization Gain & Offset Adj (−) SE TP2 31 Outrigger Signals "G" P/N Sample & Hold 8/9 D2SE BW/LPF V21 Gain & Offset Adj V21 Gain & Offset Adj SE TP2 32 "H" 10/11 P/N Sample & Hold D2SE BW/LPF (+) SUMSB 29 Outrigger Tracking Error SE TP2 28 REFBACK SELTE Reg 56 <0> IDINT Reg 32 <6> LPF 24 VGA 12V 28 TE 100 kHz TRI2VHIG Reg 56<2> TEG1\I2VLOG Reg 68 <3:0> SE TP2 25 TEGOUT Reg 69 <3:0> TEOFF Reg 57 <2:0> + SGNTEOFF Reg 56 <1> TEG1\I2VHIG Reg 68 <7:4> DC Offset ENMB Reg 66<1> POLMB Reg 66 <2> TEMB Pin 25 Main Beam 25 From 1503 GSELMB Reg 68 <7:4> Vref 9 2054A–DVD–07/02 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Figure 6. AT78C1507 Pin-out 01 NC0 WBLIN 75 02 NC1 VDD3 74 03 NC2 VSS3 73 04 EP VDD11 72 05 EN VSS11 71 06 FP CTP7 70 07 FN CTP6 69 08 GP CTP5 68 09 GN CTP4 67 10 HP CTP3 66 11 HN CTP2 65 12 WBLCOAST CTP1 64 13 REXT CTP0 63 14 VDD1 PDATA 62 15 VSS1 PCLK 61 16 TLOW2 VDD5 60 17 TLOW3 VSS6 59 18 CDOPC FREF 58 19 DVDOPC VDD7 57 20 VDD6 VSS7 56 21 SHSB VDD4 55 22 VSS6 VSS4 54 23 REFFRONT SCLK 53 24 REFBACK SDATA 52 25 TEMB SENA 51 ATP1 OPCOUT TE SUMSB PORB VSS6 VDD8 TLOW4 LHIPWR THI1 ADCSTRT SHCD SHDVD TLOW7 TLOW8 THI2 VSS9 VDD9 NC4 NC9 NC10 TZC TOK NC5 ND6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AT78C1507 Table 3. AT78C1507 Pin List 10 Pin # Pin Name Type Description 1 NC0 Digital Output Not Used 2 NC1 Analog Input Not Used 3 NC2 Analog Input Not Used 4 EP Diff Input “E” Input Pos 5 EN Diff Input “E” Input Neg 6 FP Diff Input “F” Input Pos 7 FN Diff Input “F” Input Neg 8 GP Diff Input “G” Input Pos 9 GN Diff Input “G” Input Neg 10 HP Diff Input “H” Input Pos 11 HN Diff Input “H” Input Neg DVD/CD Read Channel 2054A–DVD–07/02 DVD/CD Read Channel Table 3. AT78C1507 Pin List (Continued) Pin # Pin Name Type Description 12 WBLCOAST Digital Input Coast Wobble Clock Synthesizer 13 REXT Passive 16 K_, 1% Resistor to 0V Supply (for on-chip biasing) 14 VDD1 3.3V Supply Power Supply 15 VSS1 0V Supply Power Supply 16 TLOW2 0V Tie-down to a 0V Supply 17 TLOW3 0V Tie-down to a 0V Supply 18 CDOPC Analog Input CD Monitor Diode 19 DVDOPC Analog Input DVD Monitor Diode 20 VDD6 3.3V Supply Power Supply 21 SHSB Digital Input Sample/Hold Control for E, F, G, H (1 = Sample, 0 = Hold) 22 VSS6 0V Supply Power Supply 23 REFFRONT Input/Output Front-end Reference Voltage 24 REFBACK Input/Output Back-end Reference Voltage 25 TEMB Analog Input Tracking Error Main Beam from AT78C1503 (generated using A, B, C, D) 26 ATP1 Analog Output Analog Test Point (single-ended) 27 OPCOUT Analog Output Sampled Monitor Diode Output 28 TE Analog Output Tracking Error Output 29 SUMSB Analog Output E+F+G+H 30 PORB Digital Input Power-on Reset, Bar (active-low) 31 VSS8 0V Supply Power Supply 32 VDD8 3.3V Supply Power Supply 33 TLOW4 0V Tie-down to a 0V Supply 34 LHIPWR Digital Input Laser High Power 35 THI1 3.3V Tie-up to a 3.3V Supply 36 ADCSTRT Digital Input Start on-chip 6-bit ADC 37 SHCD Digital Input Sample/Hold Control for CD Monitor Diode (1 = Sample, 0 = Hold) 38 SHDVD Digital Input Sample/Hold Control for DVD Monitor Diode (1 = Sample, 0 = Hold) 39 TLOW7 0V Tie-down to a 0V Supply 40 TLOW8 0V Tie-down to a 0V Supply 41 THI2 3.3V Tie-up to a 3.3V Supply 42 VSS9 0V Supply Power Supply 43 VDD9 3.3V Supply Power Supply 11 2054A–DVD–07/02 Table 3. AT78C1507 Pin List (Continued) 12 Pin # Pin Name Type Description 44 NC4 Digital Output Not Used 45 NC9 Digital Output Not Used 46 NC10 Digital Output Not Used 47 TZC Digital Output Track Zero Crossing 48 TOK Digital Output Tracking Error OK 49 NC5 Digital Output Not Used 50 NC6 Digital Output Not Used 51 SENA Digital Input Serial Data Enable (must be high to read or write serial registers) 52 SDATA Input/Output Serial Data, Input (write data) or Output (read data) 53 SCLK Digital Input Serial Data Clock 54 VSS4 0V Supply Power Supply 55 VDD4 3.3V Supply Power Supply 56 VSS7 0V Supply Power Supply 57 VDD7 3.3V Supply Power Supply 58 FREF Digital Input Frequency Reference for Wobble Clock Synthesizer 59 VSS5 0V Supply Power Supply 60 VDD5 3.3V Supply Power Supply 61 PCLK Digital Output Pre-pit Clock 62 PDATA Digital Output Pre-pit Data 63 CTP0 Digital Output Digital Test Point Out, Bit 0 64 CTP1 Digital Output Digital Test Point Out, Bit 1 65 CTP2 Digital Output Digital Test Point Out, Bit 2 66 CTP3 Digital Output Digital Test Point Out, Bit 3 67 CTP4 Digital Output Digital Test Point Out, Bit 4 68 CTP5 Digital Output Digital Test Point Out, Bit 5 69 CTP6 Digital Output Digital Test Point Out, Bit 6 70 CTP7 Digital Output Digital Test Point Out, Bit 7 71 VSS11 0V Supply Power Supply 72 VDD11 3.3V Supply Power Supply 73 VSS3 0V Supply Power Supply 74 VDD3 3.3V Supply Power Supply 75 WBLIN Digital Input Raw Digital Wobble from AT78C1503 76 WCLK Digital Output Write Clock (synthesized wobble clock) 77 WCLKEN Digital Input Write Clock Enable DVD/CD Read Channel 2054A–DVD–07/02 DVD/CD Read Channel Table 3. AT78C1507 Pin List (Continued) Pin # Pin Name Type Description 78 TLOW9 0V Tie-down to a 0V Supply 79 TLOW10 0V Tie-down to a 0V Supply 80 TLOW11 0V Tie-down to a 0V Supply 81 TLOW12 0V Tie-down to a 0V Supply 82 TSDDTP1N Test Output Differential Analog/CML Test Point1 Neg 83 TSDDTP1P Test Output Differential Analog/CML Test Point1 Pos 84 TSDDTP2N Test Output Differential Analog/CML Test Point2 Neg 85 TSDDTP2P Test Output Differential Analog/CML Test Point2 Pos 86 SFILTN Diff Passive Wobble Synthesizer Filter Neg 87 SFILTP Diff Passive Wobble Synthesizer Filter Pos 88 VDD2 3.3V Supply Power Supply 89 VSS2 0V Supply Power Supply 90 TP2N Diff Output Not Used 91 TP2P Diff Output Not Used 92 TP1N Diff Output Not Used 93 TP1P Diff Output Not Used 94 PBOT Digital Input Bottom Pre-pit Detect from AT78C1503 95 PTOP Digital Input Top Pre-pit Detect from AT78C1503 96 VSS10 0V Supply Power Supply 97 VDD10 3.3V Supply Power Supply 98 PTSEL Digital Input Pre-pit Top Select (PTSEL = 1 selects input on pin PTOP; PTSEL = 0 selects input on PBOT) 99 NC7 Analog Output Not Used 100 NC8 Passive Not Used 13 2054A–DVD–07/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® is the registered trademark of Atmel. Printed on recycled paper. 2054A–DVD–07/02