AD ADP3334AR

a
High Accuracy Low IQ, 500 mA
anyCAP® Adjustable Low Dropout Regulator
ADP3334
FEATURES
High Accuracy Over Line and Load: ⴞ0.9% @ 25ⴗC,
ⴞ1.8% over Temperature
Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA
Requires Only CO = 1.0 ␮F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1.0 ␮A (Typ)
2.6 V to 11 V Supply Range
1.5 V to 10 V Output Range
–40ⴗC to +85ⴗC Ambient Temperature Range
Thermally-Enhanced 8-Lead SO Package
FUNCTIONAL BLOCK DIAGRAM
Q1
IN
OUT
ADP3334
THERMAL
PROTECTION
CC
FB
gm
DRIVER
SD
BANDGAP
REF
GND
APPLICATIONS
Cellular Phones
Camcorders, Cameras
Networking Systems, DSL/Cable Modems
Cable Set-Top Boxes
DSP Supplies
Personal Digital Assistants
GENERAL DESCRIPTION
The ADP3334 is a member of the ADP333x family of precision
low dropout anyCAP voltage regulators. The ADP3334 operates
with an input voltage range of 2.6 V to 11 V and delivers a
continuous load current up to 500 mA. The novel anyCAP
architecture requires only a very small 1 µF output capacitor for
stability, and the LDO is insensitive to the capacitor’s equivalent series resistance (ESR). This makes ADP3334 stable with any
capacitor, including ceramic (MLCC) types for space restricted
applications.
The ADP3334 achieves exceptional accuracy of ± 0.9% at room
temperature and ± 1.8% over temperature, line, and load. The
dropout voltage of the ADP3334 is only 200 mV (typical) at
500 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown
mode, the ground current is reduced to less than 1 µA. The
ADP3334 has low quiescent current 90 µA (typical) in light
load situations.
ADP3334
VIN
IN
OUT
IN
OUT
VOUT
R1
CIN
1␮F
FB
SD
GND
CNR
COUT
1␮F
R2
OFF
ON
Figure 1. Typical Application Circuit
The ADP3334 also features ADI’s thermally enhanced Thermal
Coastline package. This allows 1 W of power dissipation without
any external heat sinking.
anyCAP is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADP3334–SPECIFICATIONS1, 2, 3 (V
IN
= 6.0 V, CIN = COUT = 1.0 ␮F, TA = –40ⴗC to +85ⴗC, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
OUTPUT
Voltage Accuracy4
VOUT
VIN = VOUT(NOM) + 0.4 V to 11 V
IL = 0.1 mA to 500 mA
TA = 25°C
VIN = VOUT(NOM) + 0.4 V to 11 V
IL = 0.1 mA to 500 mA
TA = 85°C
VIN = VOUT(NOM) + 0.4 V to 11 V
IL = 0.1 mA to 500 mA
TJ = 150°C
VIN = VOUT(NOM) + 0.4 V to 11 V
IL = 0.1 mA
TA = 25°C
IL = 0.1 mA to 500 mA
TA = 25°C
VOUT = 98% of VOUT(NOM)
IL = 500 mA
IL = 300 mA
IL = 100 mA
IL = 1 mA
VIN = VOUT(NOM) + 1 V
f = 10 Hz–100 kHz, CL = 10 µF
IL = 500 mA, CNR = 10 nF
f = 10 Hz–100 kHz, CL = 10 µF
IL = 500 mA, CNR = 0 nF
Line Regulation4
Load Regulation
Dropout Voltage
Peak Load Current
Output Noise
GROUND CURRENT5
In Regulation
VDROP
ILDPK
VNOISE
IGND
In Dropout
IGND
In Shutdown
IGNDSD
SHUTDOWN
Threshold Voltage
SD Input Current
Output Current In Shutdown
VTHSD
ISD
IOSD
Max
Unit
–0.9
+0.9
%
–1.8
+1.8
%
–2.3
+2.3
%
0.04
mV/V
0.04
mV/mA
200
140
60
10
800
27
400
250
140
mV
mV
mV
mV
mA
µV rms
µV rms
45
IL = 500 mA
IL = 300 mA
IL = 50 mA
IL = 0.1 mA
VIN = VOUT(NOM) – 100 mV
IL = 0.1 mA
SD = 6 V, VIN = 11 V
LDO OFF
LDO ON
0 ≤ SD ≤ 5 V
TA = 25°C, VIN = 11 V
TA = 85°C, VIN = 11 V
Typ
4.5
2.6
0.5
90
150
10
6
1.5
130
450
mA
mA
mA
µA
µA
0.9
3
µA
1.2
0.01
0.01
0.4
3
5
5
V
V
µA
µA
µA
2.0
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2
Ambient temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full load test conditions.
3
Application stable with no load.
4
VIN = 2.6 V to 11 V for models with V OUT(NOM) ≤ 2.2 V.
5
Ground current includes current through external resistors.
Specifications subject to change without notice.
–2–
REV. 0
ADP3334
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40°C to +85°C
Operating Junction Temperature Range . . . –40°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
␪JA 2-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3°C/W
␪JA 4-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.6°C/W
Lead Temperature Range (Soldering 6 sec) . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device
to be permanently damaged.
ORDERING GUIDE
Model
Output
Package
Description
Package
Option
ADP3334AR
ADJ
Standard Small
Outline Package
(SOIC-8)
SO-8
Pin
No.
Mnemonic
Function
1
2
GND
SD
3, 4
IN
Ground Pin.
Shutdown Control. Pulling this pin low
turns on the regulator.
Regulator Input.
5, 6
OUT
7
FB
8
NC
Output. Bypass to ground with a 1.0 µF
or larger capacitor.
Feedback Input. FB should be connected
to an external resistor divider which sets
the output voltage.
No connection.
PIN CONFIGURATION
GND 1
SD 2
8
ADP3334
NC
7
FB
TOP VIEW
IN 3 (Not to Scale) 6 OUT
IN 4
5
OUT
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3334 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3334–Typical Performance Characteristics
2.201
2.202
IL = 0
VOUT = 2.2V
VIN = 6V
2.199
150mA
2.198
2.197
300mA
2.196
2.195
2.199
2.197
2.196
2.195
80
4
6
8
10
INPUT VOLTAGE – Volts
12
40
20
0
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
100
200
300
400
OUTPUT LOAD – mA
0
500
TPC 2. Output Voltage vs. Load
Current
OUTPUT CHANGE – %
0.3
0.2
0.1
500mA
0
1.0
–0.1
0
100
200
300
400
OUTPUT LOAD – mA
IL = 500mA
TPC 5. Output Voltage Variation %
vs. Junction Temperature
12
VIN = 6V
VOUT = 2.2V
6
5
300mA
4
3
2
100mA
1
50mA
500mA
0
0
0
25
50
75 100 125 150
–50 –25
JUNCTION TEMPERATURE – ⴗC
0
–0.2
0
25
50
75 100 125 150
–50 –25
JUNCTION TEMPERATURE – ⴗC
500
TPC 4. Ground Current vs. Load
Current
GROUND CURRENT – mA
300mA
4.0
2.0
4
6
8
10
INPUT VOLTAGE – Volts
7
0.4
3.0
2
8
0
VIN = 6V
VOUT = 2.2V
0
TPC 3. Ground Current vs. Supply
Voltage
0.5
5.0
IL = 0
60
2.193
2
VOUT = 2.2V
100
2.198
2.194
500mA
2.194
0
IL = 100␮A
120
GROUND CURRENT – ␮A
OUTPUT VOLTAGE – Volts
2.200
2.200
TPC 6. Ground Current vs. Junction
Temperature
250
150
100
50
0
0
100
200
300
400
OUTPUT LOAD – mA
TPC 7. Dropout Voltage vs.
Output Current
500
VOUT = 2.2V
SD = GND
RL = 4.4⍀
3.0
2.5
2.0
3
2 COUT = 1␮F
1
1.5
0
1.0
4
VIN – V
INPUT/OUTPUT VOLTAGE – V
200
VOUT – V
VOUT = 2.2V
DROPOUT VOLTAGE – mV
OUTPUT VOLTAGE – Volts
2.201
GROUND CURRENT – mA
140
VOUT = 2.2V
0.5
COUT = 10␮F
2
VOUT = 2.2V
SD = GND
RL = 4.4⍀
0
0
1
2
3
TIME – Sec
4
TPC 8. Power-Up/Power-Down
–4–
200
400
600
TIME – ␮s
800
TPC 9. Power-Up Response
REV. 0
2.189
2.179
2.190
3.000
40
80
140
TIME – ␮s
VOUT = 2.2V
RL = 4.4⍀
CL = 10␮F
2.189
2.179
VIN – V
3.500
3.500
3.000
40
180
2.3
2.2
200
400
600
TIME – ␮s
0
VIN = 4V
0
800
200
400
600
TIME – ␮s
CL = 10␮F
IL = 500mA
10␮F
10␮F
1␮F
0
VIN = 6V
VOUT = 2.2V
RL = 4.4⍀
–70
IL = 500mA WITHOUT
NOISE REDUCTION
100
IL = 500mA WITH
NOISE REDUCTION
80
IL = 0mA WITHOUT
NOISE REDUCTION
60
40
CL = 10␮F
IL = 50␮A
–80
1k
10k
100k
FREQUENCY – Hz
1M
400
600
TIME – ␮s
800
TPC 15. Turn Off/On Response
10
VOUT = 2.2V
IL = 1mA
CL = 10␮F
CL = 10␮F
CNR = 10nF CNR = 0
1
CL = 1␮F
CNR = 0
0.1
CL = 1␮F
CNR = 10nF
0.01
20
–90
100
0
100
120
–60
2
200
VOUT = 2.0V
CNR = 10nF
140
CL = 1␮F
IL = 50␮A
800
1␮F
1
TPC 14. Short Circuit Current
RMS NOISE – ␮V
CL = 1␮F
IL = 500mA
–40
10M
TPC 16. Power Supply Ripple
Rejection
REV. 0
2
800
160
–30
RIPPLE REJECTION – dB
FULL SHORT
800m⍀
SHORT
1
TPC 13. Load Transient Response
VOUT = 2.2V
400
600
TIME – ␮s
TPC 12. Load Transient Response
VSD – V
IOUT – A
IOUT – mA
0
10
0
2
VOUT = 2.2V
VIN = 6V
CL = 10␮F
200
–50
VIN = 6V
VOUT = 2.2V
CL = 1␮F
200
2.2
3
–20
400
200
2.1
400
2.1
180
TPC 11. Line Transient Response
VOUT – V
TPC 10. Line Transient Response
80
140
TIME – ␮s
2.2
VOLTAGE NOISE SPECTRAL
DENSITY – ␮V/ Hz
VIN – V
2.200
VOUT = 2.2V
RL = 4.4⍀
CL = 1␮F
2.3
VOUT – V
2.190
VOUT – V
2.210
IOUT – mA
2.200
VOUT – V
2.210
VOUT – V
VOUT – V
ADP3334
0
0
IL = 0mA WITH NOISE REDUCTION
10
20
30
CL – ␮F
40
TPC 17. RMS Noise vs. CL
(10 Hz–100 kHz)
–5–
50
0.001
10
100
1k
10k
100k
FREQUENCY – Hz
TPC 18. Output Noise Density
1M
ADP3334
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive ± 1.8%
accuracy is guaranteed over line, load, and temperature.
THEORY OF OPERATION
The new anyCAP LDO ADP3334 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
Additional features of the circuit include current limit and thermal shutdown.
APPLICATION INFORMATION
Capacitor Selection
OUTPUT
INPUT
Q1
NONINVERTING
WIDEBAND
DRIVER
ATTENUATION
(VBANDG AP / VOUT)
COMPENSATION
CAPACITOR
R3 D1
PTAT
FB
VOS
gm
PTAT
CURRENT
R4
ADP3334
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3334 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 1 µF is all that is
needed for stability; larger capacitors can be used if high output
current surges are anticipated. The ADP3334 is stable with
extremely low ESR capacitors (ESR ⬇ 0), such as multilayer
ceramic capacitors (MLCC) or OSCON. Note that the effective
capacitance of some capacitor types may fall below the minimum over temperature or with DC voltage.
R1
CLOAD
(a)
RLOAD
R2
GND
Input Bypass Capacitor
Figure 2. Functional Block Diagram
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit’s sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capacitor is also recommended.
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input, “offset voltage”
that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more
flexibility on the trade-off of noise sources that leads to a low
noise design.
Noise Reduction
A noise reduction capacitor (CNR) can be placed between the
output and the feedback pin to further reduce the noise by
6 dB–10 dB (TPC 18). Low leakage capacitors in 100 pF to
1 nF range provide the best performance. Since the feedback
pin (FB) is internally connected to a high impedance node, any
connection to this node should be carefully done to avoid noise
pickup from external sources. The pad connected to this pin
should be as small as possible and long PC board traces are not
recommended.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider thus avoiding the error resulting from
base current loading in conventional circuits.
When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown.
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values of 1 nF, this delay may be
on the order of several milliseconds.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
ADP3334
VIN
IN
OUT
IN
OUT
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
VOUT
R1
CIN
1␮F
FB
SD
GND
CNR
COUT
1␮F
R2
OFF
ON
Figure 3. Typical Application Circuit
With the ADP3334 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the output. Additional advantages of the pole-splitting scheme include
Output Voltage
The ADP3334 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be divided
by R1 and R2, and then fed back to the FB pin.
–6–
REV. 0
ADP3334
In order to have the lowest possible sensitivity of the output
voltage to temperature variations, it is important that the parallel resistance of R1 and R2 is always 50 kΩ.
R1 × R2
= 50 kΩ
R1 + R2
Also, for the best accuracy over temperature the feedback voltage should be set for 1.178 V:
VFB = VOUT
 R2 
×

 R1 + R2 
where VOUT is the desired output voltage and VFB is the “virtual
bandgap” voltage. Note that VFB does not actually appear at the
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2 gives
the following formulas:
R1 = 50 kΩ ×
R2 =
VOUT
VFB
50 kΩ

VFB 
1 −

 VOUT 
Table I. Feedback Resistor Selection
VOUT (V)
R1(1% Resistor) (kΩ) R2 (1% Resistor) (kΩ)
1.5
63.4
232
1.8
76.8
147
2.2
93.1
107
2.7
115
88.7
3.3
140
78.7
5
210
64.9
10
422
56.2
Thermal Overload Protection
The ADP3334 is protected against damage from excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a
safe level. The output current is restored when the die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
REV. 0
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (VIN – VOUT) ILOAD + (VIN) IGND
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and
VOUT = 2.8 V, device power dissipation is:
PD = (5 – 2.8) 400 mA + 5.0 (4 mA) = 900 mW
The proprietary package used in the ADP3334 has a thermal
resistance of 86.6°C/W, significantly lower than a standard
SOIC-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately
equal to:
∆TJA = 0.900 W × 86.6o C /W = 77.9o C
To limit the maximum junction temperature to 150°C, maximum allowable ambient temperature will be:
TAMAX = 150°C – 77.9°C/W = 72.1°C
Printed Circuit Board Layout Consideration
All surface mount packages rely on the traces of the PC board to
conduct heat away from the package.
In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be
attached to these fused pins.
The patented thermal coastline lead frame design of the ADP3334
uniformly minimizes the value of the dominant portion of the
thermal resistance. It ensures that heat is conducted away by all
pins of the package. This yields a very low 86.6°C/W thermal
resistance for an SOIC-8 package, without any special board
layout requirements, relying only on the normal traces connected
to the leads. This yields a 15% improvement in heat dissipation
capability as compared to a standard SOIC-8 package. The
thermal resistance can be decreased by, approximately, an additional 10% by attaching a few square cm of copper area to the
IN or OUT pins of the ADP3334 package.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3334’s pins since it will increase
the junction-to-ambient thermal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output OFF. Pulling SD down
to 0.4 V or below, or tying it to ground will turn the output ON.
In shutdown mode, quiescent current is reduced to much less
than 1 µA.
–7–
ADP3334
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C02610–1.5–7/01(0)
8-Lead SOIC
(R-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
8ⴗ
0.0098 (0.25) 0ⴗ 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
PRINTED IN U.S.A.
0.0098 (0.25)
0.0040 (0.10)
–8–
REV. 0