12-Bit R/D Converter with Reference Oscillator AD2S1205 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Complete monolithic R/D converter Parallel and serial 12-bit data ports System fault detection Absolute position and velocity outputs Differential inputs ±11 arc minutes of accuracy 1,250 rps maximum tracking rate, 12-bit resolution Incremental encoder emulation (1,024 pulses/rev) Programmable sinusoidal oscillator on-board Compatible with DSP and SPI® interface standards 204.8 kHz square wave output Single-supply operation (5.00 V ± 5%) −40°C to +125°C temperature rating 44-lead LQFP package 4 kV ESD protection The AD2S1205 is a complete 12-bit resolution tracking resolver-to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation for resolvers. An external crystal is recommended to provide a precision time reference. The converter accepts 3.15 V p-p ± 27% input signals, in the range of 10 kHz to 20 kHz on the Sin and Cos inputs. A Type II servo loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The maximum tracking rate of the converter is set internally by the input clock frequency. The nominal clock frequency is 8.192MHz which allows a tracking rate of 1,000rps. However by increasing the clock frequency to 10.24MHz a maximum tracking rate of 1,250 rps can be achieved. FUNCTIONAL BLOCK DIAGRAM REFERENCE PINS CRYSTAL AD2S1205 VOLTAGE REFERENCE REFERENCE OSCILLATOR (DAC) EXCITATION OUTPUTS INTERNAL CLOCK GENERATOR SYNTHETIC REFERENCE ADC INPUTS FROM RESOLVER FAULT DETECTION TYPE II TRACKING LOOP FAULT DETECTION OUTPUTS ADC POSITION REGISTER ENCODER EMULATION OUTPUTS ENCODER EMULATION VELOCITY REGISTER MULTIPLEXER DATA BUS OUTPUT RESET DATA I/O Figure 1. Rev. PrB_10/06 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved. AD2S1205 Preliminary Technical Data APPLICATIONS Electric power steering Electric vehicles Integrated starter generator/alternator Encoder emulation Automotive motion sensing and control PRODUCT HIGHLIGHTS • • Complete Resolver-to-Digital Interface: The AD2S1205 provides the complete solution for digitizing resolver signals (12-bit resolution) with on-board programmable sinusoidal oscillator. Ratiometric Tracking Conversion: This technique provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. • Triple Format Position Data: Absolute 12-bit angular binary position data accessed either via a 12-bit parallel port or via a 3-wire serial interface. Incremental encoder emulation in standard A QUAD B format, with direction output is available. • Digital Velocity Output: 12-bit signed digital velocity, twos complement format, accessed either via a 12-bit parallel port or via a 3-wire serial interface. • Programmable Excitation Frequency: Excitation frequency easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz by using the frequency select pins. • System Fault Detection: A fault detection circuit will detect any loss of resolver signals, out of range input signals, input signal mismatch, or loss of position tracking. Rev.PrB | Page 2 of 25 Preliminary Technical Data AD2S1205 TABLE OF CONTENTS AD2S1205–Specifications ................................................................4 Incremental Encoder Outputs...................................................16 Absolute Maximum Ratings ............................................................6 On-Board Programmable Sinusoidal Oscillator.....................17 ESD Caution ..................................................................................6 Supply Sequencing and Reset....................................................17 Pin Configuration and Function Descriptions .............................7 Charge Pump Output .................................................................18 Resolver Format Signals ...................................................................8 Circuit Dynamics ............................................................................19 Principle of Operation ......................................................................9 AD2S1205 Loop Response Model ............................................19 Fault Detection Circuit.................................................................9 Sources of Error...........................................................................20 Connecting the Converter .........................................................11 Clock Requirements ...................................................................21 Absolute Position and Velocity Output....................................12 Connecting to the DSP...............................................................21 Parallel Interface..........................................................................12 Outline Dimensions........................................................................22 Serial Interface.............................................................................14 Ordering Guide ...........................................................................22 Rev. PrB | Page 3 of 25 AD2S1205 Preliminary Technical Data AD2S1205–SPECIFICATIONS Table 1. (AVDD = DVDD = 5.0 V ± 5% @ −40°C to +125°C CLKIN 6.144MHz to 10.24MHz, unless otherwise noted.) Parameter Sin, Cos INPUTS1 Voltage Input Bias Current Input Impedance Common Mode Volts Phase Lock Range ANGULAR ACCURACY Angular Accuracy Resolution Linearity INL Linearity DNL Repeatability Hysteresis VELOCITY OUTPUT Velocity Accuracy Resolution Linearity Offset Dynamic Ripple DYNAMIC PERFORMANCE Bandwidth Tracking Rate Acceleration Error Settling Time 179° Step Input Settling Time 179° Step Input EXC, EXC OUTPUTS Voltage Center Voltage Frequency Typ Max Unit Conditions/Comments 2.3 3.15 4.0 V p-p 2 μA MΩ mV Peak Degrees Sinusoidal waveforms, Sin-SinLO, Cos-CosLO, differential inputs VIN = 3.96 V p-p VIN = 3.96 V p-p CMV with respect to REFOUT/2 @ 10 kHz Sin/Cos vs. EXC output 1.0 100 +45 −45 ±11 ±22 arc min arc min Bits LSB LSB LSB LSB Zero acceleration Y Grade Zero acceleration W Grade Guaranteed no missing codes Zero acceleration, 0 to 1,000 rps Guaranteed monotonic LSB Bits LSB LSB LSB Zero acceleration 2,000 1,250 Hz rps 5.2 4.0 arc min ms ms Fixed CLKIN 10.24MHz. Guaranteed by design. Tested to 800 rps. At 10,000 rps2 To within stated accuracy To within one degree 12 2 0.3 1 1 2 11 1 0 1 1,160 1,600 1 30 −60 35 −55 V p-p V kHz kHz kHz kHz mV dB 2.24 2.3 V p-p Angular Accuracy (Worst Case) 57 Degrees Angular Latency (Worst Case) 114 Degrees Time Latency 125 μs EXC/EXC DC Mismatch THD FAULT DETECTION BLOCK LOS Sin/Cos Threshold 1 Min 3.34 2.39 2.18 3.6 2.47 10 12 15 20 3.83 2.52 The voltages Sin, SinLO, Cos, and CosLO relative to AGND must always be between 0.2 V and AVDD. Rev.PrB | Page 4 of 25 Guaranteed by design 2 LSB max Zero acceleration Zero acceleration Load ±100 μA FS1 = high, FS2 = high FS1 = high, FS2 = low FS1 = low, FS2 = high FS1 = low, FS2 = low First five harmonics DOS and LOT go low when Sin or Cos fall below threshold. LOS indicated before angular output error exceeds limit (4.0 V p-p input signal and 2.2 V LOS threshold). Maximum electrical rotation before LOS is indicated (4.0 V p-p input signal and 2.2 V LOS threshold). Preliminary Technical Data Parameter FAULT DETECTION BLOCK (CONT.) DOS Sin/Cos Threshold Sin/Cos Mismatch AD2S1205 Min Typ Max Unit Conditions/Comments 4.0 4.09 385 4.2 420 V p-p mV 33 Degrees 66 125 Degrees μs DOS goes low when Sin or Cos exceeds threshold. DOS latched low when Sin/Cos amplitude mismatch exceeds the threshold. DOS indicated before angular output error exceeds limit. Maximum electrical rotation before DOS is indicated. Angular Accuracy (Worst Case) Angular Latency (Worst Case) Time Latency LOT Tracking Threshold Time Latency Hysteresis VOLTAGE REFERENCE REFOUT Drift PSRR CHARGE PUMP OUTPUT (CPO) Frequency Duty Cycle POWER SUPPLY IDD Dynamic ELECTRICAL CHARACTERISTICS VIL Voltage Input Low VIH Voltage Input High VOL Voltage Output Low VOH Voltage Output High IIL Low Level Input Current IIH High Level Input Current IOZH High Level Three-State Leakage IOZL Low Level Three-State Leakage 5 Degrees 1.1 4 2.39 2.47 70 −60 2.52 204.8 50 ms Degrees ±IOUT = 100 μA kHz % Square wave output mA 0.8 V V V V μA μA μA μA 0.4 4.0 10 −10 −10 10 Guaranteed by design V ppm/°C dB 18 2.0 LOT goes low when internal error signal exceeds threshold. Guaranteed by design. Rev. PrB | Page 5 of 25 2 mA load −1 mA load AD2S1205 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VDD) Supply Voltage (AVDD) Input Voltage Output Voltage Swing Operating Temperature Range (Ambient) Storage Temperature Range Lead Temperature Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +7.0 V −0.3 V to + 7.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev.PrB | Page 6 of 25 Preliminary Technical Data AD2S1205 EXC EXC AGND Sin SinLO AVDD CosLO Cos AGND REFBYP REFOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 DVDD 1 33 RESET RD 2 32 FS2 CS 3 31 FS1 SAMPLE 4 30 LOT RDVEL 5 AD2S1205 29 DOS SOE 6 TOP VIEW (Not to Scale) 28 DIR 27 NM DB10/SCLK 8 26 B DB9 9 25 A DB8 10 24 CPO DB7 11 23 DGND 04406-0-002 DB11/SO 7 CLKIN XTALOUT DB0 DB1 DB2 DVDD DGND DB3 DB4 DB5 DB6 12 13 14 15 16 17 18 19 20 21 22 Figure 2. Pin Configuration 44-Lead Low Profile Quad Flat Package [LQFP] (ST-44) Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9–15 16 17 18–20 21 22 23 24 25 26 Pin Name DVDD RD CS SAMPLE RDVEL SOE DB11/SO DB10/SCLK DB9–DB3 DGND DVDD DB2–DB0 XTALOUT CLKIN DGND CPO A B Pin Type Supply Input Input Input Input Input Output Input, output Output Ground Supply Output Output Input Ground Output Output Output Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Rev. PrB | Page 7 of 25 Pin Name NM DIR DOS LOT FS1 FS2 RESET EXC EXC AGND Sin SinLO AVDD CosLO Cos AGND REFBYP REFOUT Pin Type Output Output Output Output Input Input Input Output Output Ground Input Input Supply Input Input Ground Input Output AD2S1205 Preliminary Technical Data RESOLVER FORMAT SIGNALS Vr = Vp × Sin(ϖt) Vr = Vp × Sin(ϖt) R1 S2 S2 Va = Vs × Sin(ϖt) × Cos(θ) θ R1 Va = Vs × Sin(ϖt) × Cos(θ) θ S4 S4 R2 R2 S3 S1 S3 Vb = Vs × Sin(ϖt) × Sin(θ) Vb = Vs × Sin(ϖt) × Sin(θ) (A) CLASSICAL RESOLVER (B) VARIABLE RELUCTANCE RESOLVER 04406-0-003 S1 Figure 3. Classical Resolver vs. Variable Reluctance Resolver A resolver is a rotating transformer typically with a primary winding on the rotor and two secondary windings on the stator. In the case of a variable reluctance resolver, there are no windings on the rotor as shown in Figure 3. The primary winding is on the stator as well as the secondary windings, but the saliency in the rotor design provides the sinusoidal variation in the secondary coupling with the angular position. Either way, the resolver output voltages (S3–S1, S2–S4) will have the same equations as shown in Equation 1. The stator windings are displaced mechanically by 90° (see Figure 3). The primary winding is excited with an ac reference. The amplitude of subsequent coupling onto the stator secondary windings is a function of the position of the rotor (shaft) relative to the stator. The resolver, therefore, produces two output voltages (S3–S1, S2–S4) modulated by the Sine and Cosine of shaft angle. Resolver format signals refer to the signals derived from the output of a resolver as shown in Equation 1. Figure 4 illustrates the output format. S3 − S1 = E 0 Sinωt × Sinθ S2 − S 4 = E 0 Sinωt × Cosθ θ = Shaft Angle Sinωt = Rotor Excitation Frequency E 0 = Rotor Excitation Amplitude S2 TO S4 (Cos) S3 TO S1 (Sin) Equation 1. 04406-0-004 R2 TO R4 (REF) 0° 90° 180° 270° θ Figure 4. Electrical Resolver Representation Rev.PrB | Page 8 of 25 360° Preliminary Technical Data AD2S1205 PRINCIPLE OF OPERATION The AD2S1205 operates on a Type II tracking closed-loop principle. The output continually tracks the position of the resolver without the need for external convert and wait states. As the resolver moves through a position equivalent to the least significant bit weighting, the output is updated by one LSB. The converter tracks the shaft angle θ by producing an output angle ϕ that is fed back and compared to the input angle θ, and the resulting error between the two is driven towards 0 when the converter is correctly tracking the input angle. To measure the error, S3–S1 is multiplied by Cosϕ and S2–S4 is multiplied by Sinϕ to give E0 Sinωt × Sinθ Cosφ S1 to S 3 E0 Sinωt × Cosθ Sinφ S 2 to S 4 FAULT DETECTION CIRCUIT The AD2S1205 fault detection circuit will detect loss of resolver signals, out of range input signals, input signal mismatch, or loss of position tracking. In these cases, the position indicated by the AD2S1205 may differ significantly from the actual shaft position of the resolver. Monitor Signal The AD2S1205 generates a monitor signal by comparing the angle in the position register to the incoming Sin and Cos signals from the resolver. The monitor signal is created in a similar fashion to the error signal described in the Principle of Operation section. The incoming signals Sinθ and Cosθ are multiplied by the Sin and Cos of the output angle, respectively, and then added together as shown below: The difference is taken, giving Monitor = A1 × Sinθ x Sinφ + A2 × Cosθ × Cosφ E0 Sinωt × (Sinθ Cosφ − Cosθ Sinφ) Equation 4. Equation 2. Where A1 is the amplitude of the incoming Sin signal (A1 × Sinθ), A2 is the amplitude of the incoming Cos signal (A2 × Cosθ), θ is the resolver angle, and ϕ is the angle stored in the position register. Note that Equation 4 is shown after demodulation, with the carrier signal Sinωt removed. Also note that for matched input signal (i.e., no-fault condition), A1 = A2. This signal is demodulated using the internally generated synthetic reference, yielding E0 ( Sinθ Cosφ − Cosθ Sinφ ) Equation 3. Equation 3 is equivalent to E0 Sin (θ − ϕ), which is approximately equal to E0 (θ − ϕ) for small values of θ − ϕ, where θ − ϕ = angular error. The value E0 (θ − ϕ) is the difference between the angular error of the rotor and the converter’s digital angle output. A phase-sensitive demodulator, integrators, and a compensation filter form a closed-loop system that seeks to null the error signal. When this is accomplished, ϕ equals the resolver angle θ within the rated accuracy of the converter. A Type II tracking loop is used so that constant velocity inputs can be tracked without inherent error. For more information about the operation of the converter, see the Circuit Dynamics section. When A1 = A2 and the converter is tracking (θ = ϕ), the monitor signal output has a constant magnitude of A1 (Monitor = A1 × (Sin2 θ + Cos2 θ) = A1), independent of shaft angle. When A1 ≠ A2, the monitor signal magnitude varies between A1 and A2 at twice the rate of shaft rotation. The monitor signal is used as described in the following sections to detect degradation or loss of input signals. Loss of Signal Detection Loss of signal (LOS) is detected when either resolver input (Sin or Cos) falls below the specified LOS Sin/Cos threshold by comparing the monitor signal to a fixed minimum value. LOS is indicated by both DOS and LOT latching as logic low outputs. The DOS and LOT pins are reset to the no fault state by a rising edge of SAMPLE. The LOS condition has priority over both the DOS and LOT conditions, as shown in Table 4. LOS is indicated within 45° of angular output error worst case. Rev. PrB | Page 9 of 25 AD2S1205 Preliminary Technical Data Signal Degradation Detection Responding to a Fault Condition Degradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold by comparing the monitor signal to a fixed maximum value. DOS is also detected when the amplitude of the input signals Sin and Cos mismatch by more than the specified DOS Sin/ Cos mismatch by continuously storing the minimum and maximum magnitude of the monitor signal in internal registers, and calculating the difference between the minimum and maximum. DOS is indicated by a logic low on the DOS pin, and is not latched when the input signals exceed the maximum input level. When DOS is indicated due to mismatched signals, the output is latched low until a rising edge of SAMPLE resets the stored minimum and maximum values. The DOS condition has priority over the LOT condition, as shown in Table 4. DOS is indicated within 30° of angular output error worst case. If any fault condition (LOS, DOS, or LOT) is indicated by the AD2S1205, the output data must be presumed to be invalid. This means that even if a RESET or SAMPLE pulse releases the fault condition, the output data may be corrupted, even though a fault may not be immediately indicated after the RESET/ SAMPLE event. As discussed earlier, there are some fault conditions with inherent latency. If the device fault is cleared, there could be some latency in the resolver’s mechanical position before the fault condition is re-indicated. Loss of Position Tracking Detection Loss of tracking (LOT) is detected for three separate conditions: • When the internal error signal of the AD2S1205 has exceeded 5° • When the input signal exceeds the maximum tracking rate of 60,000 rpm (1,000 rps) • When the internal position (at the position integrator) differs from the external position (at the position register) by more than 5° LOT is indicated by a logic low on the LOT pin, and is not latched. LOT has a 4° hysteresis, and is not cleared until the internal error signal or internal/external position mismatch is less than 1°. When the maximum tracking rate is exceeded, LOT is cleared when both the velocity is less than 1,000 rps and the internal/external position mismatch is less than 1°. LOT can be indicated for step changes in position (such as after a RESET signal is applied to the AD2S1205), or for accelerations >~85,000 rps2. LOT is useful as a built-in test (BIT) that the tracking converter is functioning properly. The LOT condition has lower priority than both the DOS and LOS conditions as shown in Table 4. The LOT and DOS conditions cannot be indicated at the same time. Table 4. Fault Detection Decoding Condition Loss of Signal Degradation of Signal Loss of Tracking No Fault DOS 0 0 1 1 LOT 0 1 0 1 When a fault is indicated, all output pins will still provide data, although the data may or may not be valid. The fault condition will not force the parallel, serial, or encoder outputs to a known state. Response to specific fault conditions is a system-level requirement. The fault outputs of the AD2S1205 indicate that the device has sensed a potential problem with either the internal or external signals of the AD2S1205. It is the responsibility of the system designer to implement the appropriate fault-handling schemes within the control hardware and/or algorithm of a given application based on the indicated fault(s) and the velocity or position data provided by the AD2S1205. False Null Condition Resolver-to-digital converters that employ Type II tracking loops based on the error equation (Equation 3) presented in the Principle of Operation section can suffer from a condition known as “false null.” This condition is caused by a metastable solution to the error equation when θ − ϕ = 180°. The AD2S1205 is not susceptible to this condition because its hysteresis is implemented externally to the tracking loop. Because of the loop architecture chosen for the AD2S1205, the internal error signal always has some movement (1 LSB per clock cycle), and so, in a metastable state, the converter will always move to an unstable condition within one clock cycle, causing the tracking loop to respond to the false null condition as if it were a 180° step change in input position (the response time is the same as specified in Dynamic Performance section of Table 1). Therefore, it is impossible to enter the metastable condition any time after the startup sequence as long as the resolver signals are valid. Priority 1 2 3 Rev.PrB | Page 10 of 25 Preliminary Technical Data AD2S1205 CONNECTING THE CONVERTER Refer to Figure 5. Ground should be connected to the AGND pin and DGND pin. Positive power supply VDD = +5 V dc ± 5% should be connected to the AVDD pin and DVDD pin. Typical values for the decoupling capacitors are 10 nF and 4.7 μF, respectively. These capacitors should be placed as close to the device pins as possible, and should be connected to both AVDD and DVDD. If desired, the reference oscillator frequency can be changed from the nominal value of 10 kHz using FS1 and FS2. Typical values for the oscillator decoupling capacitors are 20 pF. Typical values for the reference decoupling capacitors are 10 μF and 0.01 μF, respectively. S2 R1 S3 4.7μF S1 5V In this recommended configuration, the converter introduces a VREF/2 offset in the Sin, Cos signals coming from the resolver. Of course, the SinLO and CosLO signals may be connected to a different potential relative to ground, as long as the Sin and Cos signals respect the recommended specifications. Note that since the EXC/EXC outputs are differential, there is an inherent gain of 2×. For example, if the primary to secondary turns ratio is 2:1, the buffer will have unity gain. Likewise, if the turns ratio is 5:1, the gain of the buffer should be 2.5×. Figure 6 suggests a buffer circuit. The gain of the circuit is R2 S4 The gain of the buffer depends on the type of resolver used. Since the specified excitation output amplitudes are matched to the specified Sin/Cos input amplitudes, the gain of the buffer is determined by the attenuation of the resolver. BUFFER CIRCUIT BUFFER CIRCUIT Gain = − (R2 / R1) 10nF ⎛ and VOUT = ⎜ V REF ⎝ 10μF EXC EXC Sin AGND AVDD SinLO Cos 33 30 5 29 AD2S1205 R2 12V EXC/EXC (VIN) 27 26 9 25 (VREF) 442Ω 1.24kΩ 5V DGND 23 12 13 14 15 16 17 18 19 20 21 22 5V 4.7μF 33Ω R1 33Ω Figure 6. Buffer Circuit 8.192 MHz 10nF 20pF VOUT 2.7kΩ 24 DVDD DGND 8 2.7kΩ 12V 28 7 11 12V 31 4 10 VREF is set so that VOUT is always a positive value, eliminating the need for a negative supply. 32 3 6 RESET 20pF 04406-0-005 2 CosLO 1 DVDD AGND 5V REFBYP 44 43 42 41 40 39 38 37 36 35 34 R2 ⎞ ⎞ ⎛ R 2 × ⎛⎜1 + × V IN ⎞⎟ ⎟⎟ − ⎜ R1 ⎠ ⎠ ⎝ R1 ⎝ ⎠ 04406-0-006 10nF Separate screened twisted cable pairs are recommended for analog inputs Sin/SinLO and Cos/CosLO. The screens should terminate to REFOUT. To achieve the dynamic performance specified, an 8.192 MHz crystal must be used. Figure 5. Connecting the AD2S1205 to a Resolver Rev. PrB | Page 11 of 25 AD2S1205 Preliminary Technical Data The angular position and angular velocity are represented by binary data and can be extracted either via a 12-bit parallel interface or a 3-wire serial interface that operates at clock rates up to 25 MHz. The chip select pin, CS, must be held low to enable the device. Angular position and velocity can be selected using a dedicated polarity input, RDVEL. RDVEL polarity pin selects which register from the position or the velocity registers is transferred to the output register. The CS pin must be held low to transfer the selected data register to the output register. Finally, the RD input is used to read the data from the output register and to enable the output buffer. The timing requirements for the read cycle are shown in Figure 7. SOE Input SAMPLE Input The serial output enable pin, SOE, is held high to enable the parallel interface. The SOE pin is held low to enable the serial interface, which places pins (DB0–DB9) in the high impedance state, while DB11 is the serial output (SO), and DB10 is the serial clock input (SCLK). Data is transferred from the position and velocity integrators, respectively, to the position and velocity registers following a high-to-low transition on the SAMPLE signal. This pin must be held low for at least t1 ns to guarantee correct latching of the data. RD should not be pulled low before this time since data would not be ready. The converter will continue to operate during the read process. Also, a rising edge of SAMPLE resets the internal registers that contain the minimum and maximum magnitude of the monitor signal. ABSOLUTE POSITION AND VELOCITY OUTPUT Data Format The digital angle signal represents the absolute position of the resolver shaft as a 12-bit unsigned binary word. The digital velocity signal is a 12-bit twos complement word, which represents the velocity of the resolver shaft rotating in either a clockwise or a counterclockwise direction. Finally, the RD input is used to read the data from the output register and to enable the output buffer. The timing requirements for the read cycle are illustrated in Figure 7. SAMPLE Input Data is transferred from the position and velocity integrators respectively to the position and velocity registers following a high to low transition of the SAMPLE signal. This pin must be held low for at least t1 ns to guarantee correct latching of the data. RD should not be pulled low before this time. Also, a rising edge of SAMPLE resets the internal registers that contain the minimum and maximum magnitude of the monitor signal. PARALLEL INTERFACE The angular position and angular velocity are available on the AD2S1205 in two 12-bit registers, which can be accessed via the 12-bit parallel port. The parallel interface is selected holding the SOE pin high. Data is transferred from the velocity and position integrators, respectively, to the position and velocity registers following a high-to-low transition on the SAMPLE pin. The CS Input The device will be enabled when CS is held low. RDVEL Input RDVEL input is used to select between the angular position and velocity registers as shown in Figure 7. RDVEL is held high for angular position and low for angular velocity. The RDVEL pin must be set (stable) at least t4 ns before the RD pin is pulled low. RD Input The 12-bit data bus lines are normally in a high impedance state. The output buffer is enabled when CS and RD are held low. A falling edge of the RD signal transfers data to the output buffer. The selected data is made available to the bus to be read within t6 ns of the RD pin going low. The data pins will return to high impedance state when the RD returns to high state, within t7 ns. If the user is reading data continuously, RD can be reapplied a minimum of t3 ns after it was released. Rev.PrB | Page 12 of 25 Preliminary Technical Data AD2S1205 tCK CLKIN t1 t1 SAMPLE t2 CS t3 t3 RD t5 t5 RDVEL t4 t4 VEL t7 DON'T CARE t6 04406-0-007 POS DATA t7 t6 Figure 7. Parallel Port Read Timing Table 5. Parallel Port Timing Parameter tCK t1 t2 t3 t4 t5 t6 t7 Description Clock Period (= 1/8.192 MHz) SAMPLE Pulse Width Delay from SAMPLE before RD/CS Low RD Pulse Width Set Time RDVEL before RD/CS Low Hold Time RDVEL after RD/CS Low Enable Delay RD/CS Low to Data Valid Disable Delay RD/CS Low to Data High Z Rev. PrB | Page 13 of 25 Min Typ ~122 ns Max 2 × tCK + 20 ns 6 × tCK + 20 ns 18 ns 5 ns 7 ns 12 ns 18 ns AD2S1205 Preliminary Technical Data SAMPLE Input SERIAL INTERFACE The angular position and angular velocity are available on the AD2S1205 in two 12-bit registers. These registers can be accessed via a 3-wire serial interface, SO, RD, and SCLK, that operates at clock rates up to 25 MHz and is compatible with SPI and DSP interface standards. The serial interface is selected by holding low the SOE pin. Data from the position and velocity integrators are first transferred to the position and velocity registers, using the SAMPLE pin. The RDVEL polarity pin selects which register from the position or the velocity registers is transferred to the output register. The CS pin must be held low to transfer the selected data register to the output register. Finally, the RD input is used to read the data that will be clocked out of the output register and will be available on the serial output pin, SO. When the serial interface is selected, DB11 is used as the serial output pin, SO, and DB10 is used as the serial clock input, SCLK, while pins DB0–DB9 are placed in the high impedance state. The timing requirements for the read cycle are described in Figure 8. SO Output The output shift register is 16-bit wide. Data is shifted out of the device as a 16-bit word under the control of the serial clock input, SCLK. The timing diagram for this operation is shown in Figure 8. The 16-bit word consists of 12 bits of angular data (position or velocity depending on RDVEL input), one RDVEL status bit and three status bits, a parity bit, degradation of signal bit, and loss of tracking bit. Data is read out MSB first (bit 15) on the SO pin. Bit 15 through bit 4 correspond to the angular information. The angular position data format is unsigned binary, with all zeros corresponding to 0 degrees and all ones corresponding to 360 degrees –l LSB. The angular velocity data format instead is twos complement binary, with the MSB representing the rotation direction. Bit 3 is the RDVEL status bit, 1 indicating position and 0 indicating velocity. Bit 2 is DOS, the degradation of signal flag (refer to the Fault Detection Circuit section). Bit 1 is LOT, the loss of tracking flag (refer to the Fault Detection Circuit section). Bit 0 is PAR, the parity bit: both position and velocity data are odd parity format; the data read out will always contain an odd number of logic highs (1s). Data is transferred from the position and velocity integrators, respectively, to the position and velocity registers following a high-to-low transition on the SAMPLE signal. This pin must be held low for at least t1 ns to guarantee correct latching of the data. RD should not be pulled low before this time since data would not be ready. The converter will continue to operate during the read process. CS Input The device will be enabled when CS is held low. RD Input The 12-bit data bus lines are normally in a high impedance state. The output buffer is enabled when CS and RD are held low. The RD input is an edge-triggered input that acts as frame synchronization signal and output enable. A falling edge of the RD signal transfers data to the output buffer and data will be available on the serial output pin, SO. RD must be held low for t9 before the data is valid on the outputs. After RD goes low, the serial data will be clocked out of the SO pin on the falling edges of the SCLK (after a minimum of t10 ns): the MSB will be already available at the SO pin on the very first falling edge of the SCLK. Each other bit of the data word will be shifted out on the rising edge of SCLK and will be available at the SO pin on the falling edge of SCLK for the next 15 clock pulses. The high-to-low transition of RD must happen during the high time of the SCLK to avoid MSB being shifted on the first rising edge of the SCLK and lost. RD may rise high after the falling edge of the last bit transmitted. Subsequent negative edges greater than the defined word length will clock zeros from the data output if RD remains in a low state. If the user is reading data continuously, RD can be reapplied a minimum of t5 ns after it is released. RDVEL Input RDVEL input is used to select between the angular position and velocity registers. RDVEL is held high for angular position and low for angular velocity. The RDVEL pin must be set (stable) at least t4 ns before the RD pin is pulled low. Rev.PrB | Page 14 of 25 Preliminary Technical Data AD2S1205 tCK CLKIN t1 t1 SAMPLE t2 CS t3 t3 RD t5 t5 RDVEL t4 t4 t6 t6 t7 t7 POS SO VEL t8 RD tSCLK SCLK t10 MSB MSB–1 LSB RDVEL DOS LOT PAR 04406-0-008 SO t11 t9 Figure 8. Serial Port Read Timing Table 6. Serial Port Timing Parameter t8 t9 t10 t11 tSCLK Description MSB Read Time from RD/CS to SCLK Enable Time RD/CS to DB Valid Delay SCLK to DB Valid Disable Time RD/CS to DB High Z Serial Clock Period (25 MHz Max) Rev. PrB | Page 15 of 25 Min 15 ns 40 ns Typ Max tSCLK 12 ns 14 ns 18 ns switching frequency is 1 / 4 × 4.096 MHz = 1.024 MHz (4Updates = 1Pulse) INCREMENTAL ENCODER OUTPUTS The incremental encoder emulation outputs A, B, and NM are free running and are always valid, providing that valid resolver format input signals are applied to the converter. The AD2S1205 emulates a 1024-line encoder. Relating this to converter resolution means one revolution produces 1,024 A, B pulses. A leads B for increasing angular rotation (i.e., clockwise direction). The addition of the DIR output negates the need for external A and B direction decode logic. The DIR output indicates the direction of the input rotation and it is high for increasing angular rotation. DIR can be considered as an asynchronous output and can make multiple changes in state between two consecutive LSB update cycles. This occurs when the direction of rotation of the input changes but the magnitude of the rotation is less than 1 LSB. The north marker pulse is generated as the absolute angular position passes through zero. The north marker pulse width is set internally for 90° and is defined relative to the A cycle. Figure 9 details the relationship between A, B, and NM. A 04406-0-009 B NM Figure 9. A, B, and NM Timing for Clockwise Rotation Unlike incremental encoders, the AD2S1205 encoder output is not subject to error specifications such as cycle error, eccentricity, pulse and state width errors, count density, and phase ϕ. The maximum speed rating, n, of an encoder is calculated from its maximum switching frequency, fMAX, and its pulses per revolution (PPR). n= 60 × f MAX PPR The AD2S1205 A, B pulses are initiated from XTALOUT, which has a frequency of 4.096 MHz. The equivalent encoder Rev. PrB_10/06 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved. Preliminary Technical Data AD2S1205 At 12 bits, the PPR = 1,024. Therefore, the maximum speed, n, of the AD2S1205 is n= 60 × 1,024,000 = 60000 rpm 1,024 To get a maximum speed of 60,000 rpm, an external crystal of 8.192 MHz has to be chosen in order to produce an internal CLOCKOUT equal to 4.096 MHz. This compares favorably with encoder specifications where fMAX is specified from 20 kHz (photo diodes) to 125 kHz (laser based) depending on the light system used. A 1,024 line laserbased encoder will have a maximum speed of 7,300 rpm. The inclusion of A, B outputs allows the AD2S1205 plus resolver solution to replace optical encoders directly without the need to change or upgrade existing application software. ON-BOARD PROGRAMMABLE SINUSOIDAL OSCILLATOR An on-board oscillator provides the sinusoidal excitation signal (EXC) to the resolver as well as its complemented signal (EXC). The frequency of this reference signal is programmable to four standard frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) using the FS1 and FS2 pins (see Table 7). FS1 and FS2 have internal pullups, so the default frequency is 10 kHz. The amplitude of this signal is centered on 2.5 V and has an amplitude of 3.6 V p-p. Table 7. Excitation Frequency Selection Frequency Selection (kHz) 10 12 15 20 FS1 1 1 0 0 FS2 1 0 1 0 Synthetic Reference Generation When a resolver undergoes a high rotation rate, the RDC tends to act as an electric motor and produces speed voltages, along with the ideal Sin and Cos outputs. These speed voltages are in quadrature to the main signal waveform. Moreover, nonzero resistance in the resolver windings causes a non-zero phase shift between the reference input and the Sin and Cos outputs. The combination of speed voltages and phase shift causes a tracking error in the RDC that is approximated by Error = Phase Shift × Rotation Rate Reference Frequency To compensate for the described phase error between the resolver reference excitation and the Sin/Cos signals, an internal synthetic reference signal is generated in phase with the reference frequency carrier. The synthetic reference is derived using the internally filtered Sin and Cos signals. It is generated by determining the zero crossing of either the Sin or Cos (whichever signal is larger, to improve phase accuracy) and evaluating the phase of the resolver reference excitation. The synthetic reference reduces the phase shift between the reference and Sin/Cos inputs to less than 10°, and will operate for phase shifts of ±45°. SUPPLY SEQUENCING AND RESET The AD2S1205 requires an external reset signal to hold the RESET input low until VDD is within the specified operating range of 4.5 V to 5.5 V. The RESET pin must be held low for a minimum of 10 μs after VDD is within the specified range (tRST in Figure 10). Applying a RESET signal to the AD2S1205 initializes the output position to a value of 0x000 (degrees output through the parallel, serial, and encoder interfaces) and causes LOS to be indicated (LOT and DOS pins pulled low) as shown in Figure 10. The reference output of the AD2S1205 will need an external buffer amplifier to provide gain and the additional current to drive a resolver. Refer to Figure 6 for a suggested buffer circuit. Failure to apply the above (correct) power-up/reset sequence can result in an incorrect position indication. The AD2S1205 also provides an internal synchronous reference signal that is phase locked to its Sin and Cos inputs. Phase errors between the resolver primary and secondary windings could degrade the accuracy of the RDC and are compensated by this synchronous reference signal. This also compensates the phase shifts due to temperature and cabling and eliminates the need of an external preset phase compensation circuits. Rev. PrB | Page 17 of 25 AD2S1205 Preliminary Technical Data After a rising edge on the RESET input, the device must be allowed at least 20 ms (tTRACK) as shown in Figure 10 for internal circuitry to stabilize and the tracking loop to settle to the step change in input position. After tTRACK, a SAMPLE pulse must be applied, releasing the LOT and DOT pins to the state determined by the fault detection circuitry and providing valid position data at the parallel and serial outputs (note that if position data is being acquired via the encoder outputs, they may be monitored during tTRACK). 4.75V tRST RESET tTRACK SAMPLE LOT VALID OUTPUT DATA DOS 04406-0-010 The RESET pin is internally pulled up. VDD Figure 10. Power Supply Sequencing and Reset CHARGE PUMP OUTPUT A 204.8 kHz square wave output with 50% duty cycle is available at the CPO output pin of the AD2S1205. This square wave output can be used for negative rail voltage generation, or to create a VCC rail. Rev.PrB | Page 18 of 25 Preliminary Technical Data AD2S1205 CIRCUIT DYNAMICS AD2S1205 LOOP RESPONSE MODEL θIN k1 × k2 – The closed-loop magnitude and phase responses are that of a second-order low-pass filter (see Figure 12 and Figure 13). VELOCITY c 1–z –1 1–az –1 1–bz –1 c 1–z –1 θOUT 04406-0-011 ERROR (ACCELERATION) Sin/Cos LOOKUP To convert G(z) into the s-plane, we perform an inverse bilinear transformation by substituting for z, where T = the sampling period (1/4.096 MHz ≈ 244 ns). 2 +s T z= 2 −s T Figure 11. RDC System Response Block Diagram The RDC is a mixed-signal device, which uses two A/D converters to digitize signals from the resolver and a Type II tracking loop to convert these to digital position and velocity words. The first gain stage consists of the ADC gain on the Sin/Cos inputs, and the gain of the error signal into the first integrator. The first integrator generates a signal proportional to velocity. The compensation filter contains a pole and a zero, used to provide phase margin and reduce high frequency noise gain. The second integrator is the same as the first integrator and generates the output position from the velocity signal. The Sin/Cos lookup has unity gain. Values are given below for each section: Substitution yields the open-loop transfer function G(s). G( s ) = k1 × k2(1 − a) × a −b This transformation produces the best matching at low frequencies (f << fSAMPLE). At lower frequencies (within the closed-loop bandwidth of the AD2S1205), the transfer function can be simplified to G ( s) ≅ VIN (V p ) • ADC gain parameter (k1nom = 1.8/2.5) k1 = • Error gain parameter k 2 = 18 x 10 6 × 2π • Compensator zero coefficient a= 4095 4096 • Compensator pole coefficient b= 4085 4096 • Integrator gain parameter c= VREF (V ) K a 1 + st1 × s 2 1 + st 2 where: T (1 + a ) 2(1 − a ) T (1 + b) t2 = 2(1 − b) k1 × k 2(1 − a ) Ka = a −b t1 = Solving for each value gives t1 = 1 ms, t2 = 90 μs, and Ka ≈ 7.4 × 106 s-2. Note that the closed-loop response is described as 1 4096000 H ( s) = • INT1 and INT2 transfer function I (z ) = c 1 − z −1 • Compensation filter transfer function C (z ) = 1 − az −1 1 − bz −1 • R2D open-loop transfer function G(z ) = k1 × k 2 × I (z )2 × C(z ) • R2D closed-loop transfer function H (z ) = G( z ) 1 + G( z ) s 2T 2 1 + s × T (1 + a) 2(1 − a) 4 × T (1 + b) s2 1+ s × 2(1 − b) 1 + sT + G (s) 1 + G(s) By converting to the s-domain, we are able to quantify the open-loop dc gain (Ka). This value is useful during calculation of acceleration error of the loop as discussed in the Sources of Error section. The step response to a 10° input step is shown in Figure 14. Because the error calculation (Equation 3) is nonlinear for large values of θ − ϕ, the response time for larger step changes in position (90°–180°) will typically take three times as long as the response to a small step change in position (<20°). In response to a step change in velocity, the AD2S1205 will exhibit the same response characteristics as for a step change in position. Rev. PrB | Page 19 of 25 AD2S1205 Preliminary Technical Data 5 SOURCES OF ERROR –0 Acceleration –5 A tracking converter employing a Type II servo loop does not suffer any velocity lag. There is, however, an error associated with acceleration. This error can be quantified using the acceleration constant (Ka) of the converter. MAGNITUDE (dB) –10 –15 –20 –25 Ka = –30 –35 –45 1 10 100 1k 10k Tracking Error Conversely, 04406-0-012 –40 Input Acceleration Tracking Error = 100k Input Acceleration Ka FREQUENCY (Hz) Figure 12. RDC System Magnitude Response Figure 15 shows tracking error versus acceleration for the AD2S1205. 0 The numerator and denominator’s units must be consistent. The maximum acceleration of the AD2S1205 has been defined as the acceleration that creates an output position error of 5° (when LOT is indicated). The maximum acceleration can be calculated as –20 –40 PHASE (Degrees) –60 –80 –100 Maximum Acceleration = –120 K a (sec −2 ) × 5° ≅ 103,000 rps 2 360(° / rev) –140 04406-0-013 –160 –180 –200 1 10 100 1k 10k The AD2S1205 will be able to withstand the maximum acceleration of 103,000 rps2 for approximately 10 ms before reaching its maximum tracking rate of 1,000 rps. 100k 1,000(rps ) FREQUENCY (Hz) 103,000(rps 2 ) Figure 13. RDC System Phase Response 10 18 9 16 8 12 10 8 6 4 04406-0-014 ANGLE (Degrees) 14 2 0 0 1 2 3 4 7 6 5 4 3 2 04406-0-015 TRACKING ERROR (Degrees) 20 ≅ 10 ms 1 0 5 0 40k 80k 120k 160k ACCELERATION (rps2) TIME (ms) Figure 14. RDC Small Step Response Figure 15. Tracking Error vs. Acceleration Rev.PrB | Page 20 of 25 200k Preliminary Technical Data AD2S1205 CLOCK REQUIREMENTS To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN, XTALOUT pins. The position and velocity accuracy are guaranteed for operation with a range of input frequencies from 6.144MHz to 10.24 MHz., based around a nominal value of 8.192 MHz. The velocity outputs are scaled in proportion to the clock frequency so that if the clock is 25% higher than the nominal, the fullscale velocity will be 25% higher than nominal. The maximum tracking rate, the tracking loop bandwidth and the excitation output frequencies also vary with the clock frequency. CONNECTING TO THE DSP The AD2S1205 serial port is ideally suited for interfacing to DSP configured microprocessors. Figure 16 shows the AD2S1205 interfaced to ADMC401, one of the DSP based motor controllers. The SAMPLE signal on the AD2S1205 could be provided either by using a PIO or by inverting the PWMSYNC signal to synchronize the position and velocity reading with the PWM switching frequency. CS and RDVEL may be obtained using two PIO outputs of the ADMC401. The 12 bits of significant data plus status bits are available on each consecutive negative edge of the clock following the low going of the RD signal. Data is clocked from the AD2S1205 into the data receive register of the ADMC401. This is internally set to 16 bits (12 bits data, 4 status bits) because 16 bits are received overall. The serial port automatically generates an internal processor interrupt. This allows the ADMC401 to read 16 bits at once and continue processing. All ADMC401 products can interface to the AD2S1205 with similar interface circuitry. The on-chip serial port of the ADMC401 is used in the following configuration: • • SCLK Alternate framing transmit mode with internal framing (internally inverted) AD2S1205 SCLK DR SO TFS RD SOE RFS Normal framing receive mode with external framing (internally inverted) PWMSYNC Internal serial clock generation In this mode, the ADMC401 uses the internal TFS signal as external RFS to fully control the timing of receiving data and it uses the same TFS as RD to the AD2S1205. The ADMC401 also provides an internal continuous serial clock to the AD2S1205. Rev. PrB | Page 21 of 25 SAMPLE PIO CS PIO RDVEL Figure 16. Connecting to the ADMC401 04406-0-016 • ADMC401 AD2S1205 Preliminary Technical Data OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 12.00 BSC 44 34 1 33 SEATING PLANE PIN 1 10.00 BSC TOP VIEW (PINS DOWN) 10° 6° 2° 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY SEATING PLANE VIEW A 11 23 12 0.80 BSC VIEW A 22 0.45 0.37 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BCB Figure 17. 44-Lead Low Profile Quad Flat Package [LQFP] (ST-44) Dimensions shown in millimeters ORDERING GUIDE Model AD2S1205YSTZ AD2S1205WSTZ Temperature Range −40°C to +125°C −40°C to +125°C Angular Accuracy ±11 arc min ±22 arc min Package Description 44-Lead Low Profile Quad Flat Package (LQFP) 44-Lead Low Profile Quad Flat Package (LQFP) Rev.PrB | Page 22 of 25 Package Option ST-44 ST-44 Preliminary Technical Data AD2S1205 NOTES Rev. PrB | Page 23 of 25 AD2S1205 Preliminary Technical Data NOTES Rev.PrB | Page 24 of 25 Preliminary Technical Data AD2S1205 NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06339-0-10/06(PrB) Rev. PrB | Page 25 of 25