Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A DESCRIPTION PIN CONFIGURATION The NE568A is a monolithic phase-locked loop (PLL) which operates from 1Hz to frequencies in excess of 150MHz and features an extended supply voltage range and a lower temperature coefficient of the VCO center frequency in comparison with its predecessor, the NE 568. The NE568A is function and pin-compatible with the NE568, requiring only minor changes in peripheral circuitry (see Figure 3). Temperature compensation network is different, no resistor on Pin 12, needs to be grounded and Pin 13 has a 3.9kΩ resistor to ground. Timing cap, C2, is different and for 70MHz operation with temperature compensation network should be 16pF, not 34pF as was used in the NE568. The NE568A has the following improvements: ESD protected; extended VCC range from 4.5V to 5.5V; operating temperature range -55 to 125°C (see Signetics Military 568A data sheet); less layout sensitivity; and lower TC of VCO (center frequency). The integrated circuit consists of a limiting amplifier, a current-controlled oscillator (ICO), a phase detector, a level shift circuit, V/I and I/V converters, an output buffer, and bias circuitry with temperature and frequency compensating characteristics. The design of the NE568A is particularly well-suited for demodulation of FM signals with extremely large deviation in systems which require a highly linear output. In satellite receiver applications with a 70MHz IF, the NE568A will demodulate ±20% deviations with less than 1.0% typical non-linearity. In addition to high linearity, the circuit has a loop filter which can be configured with series or shunt elements to optimize loop dynamic performance. The NE568A is available in 20-pin dual in-line and 20-pin SO (surface mounted) plastic packages. D, N Packages VCC2 1 20 LF1 2 19 LF2 GND1 3 18 LF3 TCAP1 4 17 LF4 TCAP2 5 16 FREQ ADJ GND1 6 15 OUT FILT GND2 VCC1 7 14 VOUT REFBYP 8 13 TCADJ2 PNPBYP 9 12 TCADJ1 INPBYP 10 11 VIN TOP VIEW SR01037 Figure 1. Pin Configuration • Series or shunt loop filter component capability • External loop gain control • Temperature compensated • ESD protected1 APPLICATIONS • Satellite receivers • Fiber optic video links • VHF FSK demodulators • Clock Recovery FEATURES • Operation to 150MHz • High linearity buffered output ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 20-Pin Plastic Small Outline Large (SOL) Package 0 to +70°C NE568AD SOT163-1 20-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE568AN SOT146-1 20-Pin Plastic Small Outline Large (SOL) Package -40 to +85°C SA568AD SOT163-1 20-Pin Plastic Dual In-Line Package (DIP) -40 to +85°C SA568AN SOT146-1 BLOCK DIAGRAM LF1 LF2 20 19 LF3 LF4 18 FREQ ADJ 16 17 OUTFILT 15 LEVEL SHIFT VOUT 14 TCADJ2 13 TCADJ OUT BUF TCADJ1 12 VIN 11 BIAS LEVEL SHIFT V/I CONVERTER I/V CONVERTER PHASE DETECTOR NOTE: Pins 4 and 5 can tolerate 1000V only, and all other pins, greater than 2000V for ESD (human body model). AMP ICO 1 VCC2 2 GND2 3 GND1 4 TCAP1 5 TCAP2 6 GND1 7 VCC1 8 REFBYP 9 PNPBYP 10 INPBYP SR01038 Figure 2. Block Diagram 1996 Feb 1 1 853-1558 16328 Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VCC RATING Supply voltage TJ Junction temperature UNITS 6 V +150 °C TSTG Storage temperature range -65 to +150 °C PDMAX Maximum power dissipation 400 mW Thermal resistance 80 °C/W θJA layout-sensitive. Evaluation of performance for correlation to the data sheet should be done with the circuit and layout of Figures 3, 4, and 5 with the evaluation unit soldered in place. (Do not use a socket!) ELECTRICAL CHARACTERISTICS The elctrical characteristics listed below are actual tests (unless otherwise stated) performed on each device with an automatic IC tester prior to shipment. Performance of the device in automated test set-up is not necessarily optimum. The NE568A is DC ELECTRICAL CHARACTERISTICS VCC = 5V; TA = 25°C; fO = 70MHz, Test Circuit Figure 3, fIN = -20dBm, R4 = 3.9kΩ, unless otherwise specified. LIMITS SYMBOL PARAMETER TEST CONDITIONS NE/SA568A MIN VCC Supply voltage ICC Supply current 4.5 UNITS TYP MAX 5 5.5 V 54 70 mA AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS NE/SA568A fOSC Maximum oscillator operating frequency3 150 Input signal level 50 –201 MIN BW Demodulated bandwidth Non-linearity5 Lock range2 Capture range2 TC of fO RIN MAX MHz 2000 +10 fO/7 Dev = ±20%, Input = -20dBm 1.0 Input = -20dBm ±25 Input = -20dBm ±20 Figure 3 Input resistance4 Dev = ±20% of fO measured at Pin 14 AM rejection VIN = -20dBm (30% AM) referred to ±20% deviation fO Distribution6 Centered at 70MHz, R2 = 1.2kΩ, C2 = 16pF, R4 = 3.9kΩ (C2 + CSTRAY = 20pF) fO Drift with supply 4.5V to 5.5V 0.40 -15 mVP-P dBm MHz 4.0 ±35 % % of fO ±30 % of fO 100 ppm/°C 1 Output impedance Demodulated VOUT TYP UNITS kΩ 6 Ω 0.52 VP-P 50 dB 0 2 +15 % %/V NOTE: 1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance. 2. Limits are set symmetrical to fO. Actual characteristics may have asymmetry beyond the specified limits. 3. Not 100% tested, but guaranteed by design. 4. Input impedance depends on package and layout capacitances. See Figures 6 and 5. 5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (VOUT). Non-linearity is then calculated from a straight line over the deviation range specified. 6. Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied. 1996 Feb 1 2 Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A 1 C1 2 VCC2 LF1 20 GND2 LF2 19 C10 R1 3 GND1 LF3 TCAP1 LF4 TCAP2 FREQADJ 18 C9 4 17 C2 RFC1 5 6 OUTFILT GND1 16 15 C8 7 14 R2 C11 C12 8 C5 C6 RFC2 VOUT VOUT VCC1 C3 VCC R3 R4 13 REFBYP TCADJ2 PNPBYP TCADJ1 C4 9 10 12 11 INPBYP VIN C13 VIN C7 R5 SR01039 Figure 3. Test Circuit for AC Parameters voltage-controlled oscillator (VCO), because the output of the phase comparator and the loop filter is a voltage. To control the frequency of an integrated ICO multivibrator, the control signal must be conditioned by a voltage-to-current converter. In the NE568A, special circuitry predistorts the control signal to make the change in frequency a linear function over a large control-current range. FUNCTIONAL DESCRIPTION The NE568A is a high-performance phase-locked loop (PLL). The circuit consists of conventional PLL elements, with special circuitry for linearized demodulated output, and high-frequency performance. The process used has NPN transistors with fT > 6GHz. The high gain and bandwidth of these transistors make careful attention to layout and bypass critical for optimum performance. The performance of the PLL cannot be evaluated independent of the layout. The use of the application layout in this data sheet and surface-mount capacitors are highly recommended as a starting point. The free-running frequency of the oscillator depends on the value of the timing capacitor connected between Pins 4 and 5. The value of the timing capacitor depends on internal resistive components and current sources. When R2 = 1.2kΩ and R4 = 0Ω, a very close approximation of the correct capacitor value is: 0.0014 C* F fO where The input to the PLL is through a limiting amplifier with a gain of 200. The input of this amplifier is differential (Pins 10 and 11). For single-ended applications, the input must be coupled through a DC-blocking capacitor with low impedance at the frequency of interest. The single-ended input is normally applied to Pin 11 with Pin 10 AC-bypassed with a low-impedance capacitor. The input impedance is characteristically slightly above 500Ω. Impedance match is not necessary, but loading the signal source should be avoided. When the source is 50 or 75Ω, a DC-blocking capacitor is usually all that is needed. C * C 2 C STRAY The temperature-compensation resistor, R4, affects the actual value of capacitance. This equation is normalized to 70MHz. See 10 for correction factors. The loop filter determines the dynamic characteristics of the loop. In most PLLs, the phase detector outputs are internally connected to the ICO inputs. The NE568A was designed with filter output to input connections from Pins 20 (φ DET) to 17 (ICO), and Pins 19 (φ DET) to 18 (ICO) external. This allows the use of both series and shunt loop-filter elements. The loop constratints are: Input amplification is low enough to assure reasonable response time in the case of large signals, but high enough for good AM rejection. After amplification, the input signal drives one port of a multiplier-cell phase detector. The other port is driven by the current-controlled oscillator (ICO). The output of the phase comparator is a voltage proportional to the phase difference of the input and ICO signals. The error signal is filtered with a low-pass filter to provide a DC-correction voltage, and this voltage is converted to a current which is applied to the ICO, shifting the frequency in the direction which causes the input and ICO to have a 90° phase relationship. K O 0.12VRadian (Phase Detector Constant) K O 4.2 10 9 The loop filter determines the general characteristics of the loop. Capacitors C9, C10, and resistor R1, control the transient output of the phase detector. Capacitor C9 suppresses 70MHz feedthrough by interaction with 100Ω load resistors internal to the phase detector. The oscillator is a current-controlled multivibrator. The current control affects the charge/discharge rate of the timing capacitor. It is common for this type of oscillator to be referred to as a 1996 Feb 1 Radians (ICO Constant) at 70MHz V –sec 3 Philips Semiconductors Product specification 150MHz phase-locked loop C9 NE/SA568A 1 F 2 (50) (f O) Parts List and Layout 70MHz Application NE568AN At 70MHz, the calculated value is 45pF. Empirical results with the test and application board were improved when a 47pF capacitor was used. The natural frequency for the loop filter is set by C10 and R1. If the center frequency of the loop is 70MHz and the full demodulated bandwidth is desired, i.e., fBW = fO/7 = 10MHz, and a value for R1 is chosen, the value of C10 can be calculated. C 10 1 F 2 R 1 f BW Also, C 11 1 2350f BW(Hz) This capacitance determines the signal bandwidth of the output buffer amplifier. (For further inofrmation see Philips application note AN1881 “The NE568A Phase Locked Loop as a Wideband Video Demodulator”. Parts List and Layout 40MHz Application NE568AD C1 100nF ±10% Ceramic chip 1206 C2 1 18pF ±2% Ceramic chip 0805 C1 100nF ±10% Ceramic chip C2 1 18pF ±2% Ceramic chip 50V C2 2 16pF ±2% Ceramic chip 0805 C3 100nF ±10% Ceramic chip 50V C4 100nF ±10% Ceramic chip 50V C5 6.8µF ±10% Tantalum 35V C6 100nF ±10% Ceramic chip 50V C7 100nF ±10% Ceramic chip 50V C8 100nF ±10% Ceramic chip 50V C9 47pF ±2% Ceramic chip 50V C10 560pF ±2% Ceramic chip 50V C11 47pF ±2% Ceramic chip 50V C12 100nF ±10% Ceramic chip 50V C13 100nF ±10% Ceramic chip R1 27Ω ±10% Ceramic CR32 R2 1.2kΩ R3 3 43Ω ±10% R4 4 3.9kΩ R5 3 50V 50V chip 1/4W Ceramic CR32 chip 1/4W ±10% Ceramic CR32 chip 1/4W 50Ω ±10% Ceramic CR32 chip 1/4W Trim pot C2 2 16pF ±2% Ceramic ORChip C3 100nF ±10% Ceramic chip 1206 C4 100nF ±10% Ceramic chip 1206 RFC1 10µH ±10% Surface mount C5 6.8µF ±10% Tantalum 35V RFC2 10µH ±10% Surface mount C6 100nF ±10% Ceramic chip 1206 C7 100nF ±10% Ceramic chip 1206 C8 100nF ±10% Ceramic chip 1206 C9 47pF ±2% Ceramic chip 0805 or 1206 C10 560pF ±2% Ceramic chip 0805 or 1206 C11 47pF ±2% Ceramic chip 0805 or 1206 C12 100nF ±10% Ceramic chip 1206 C13 100nF ±10% Ceramic chip 1206 R1 27Ω ±10% Chip CR32 1/4W R2 1.2kΩ R3 3 43Ω ±10% Chip CR32 1/4W R4 4 3.9kΩ ±10% Chip CR32 1/4W R5 3 50Ω ±10% Chip CR32 1/4W 5 10µH ±10% Surface mount RFC25 10µH ±10% Surface mount RFC1 NOTES: 1. 18pF with Pin 12 ground and Pin 13 no connect (open). 2. C2 + CSTRAY = 16pF for temperature-compensated configuration with R4 = 3.9kΩ. 3. For 50Ω setup. R1 = 62Ω, R3 = 75Ω for 75Ω application. 4. For test configuration R4 = 0Ω (GND) and C2 = 18pF. Trim pot NOTES: 1. 18pF with Pin 12 ground and Pin 13 no connect (open). 2. C2 + CSTRAY = 16pF for temperature-compensated configuration with R4 = 3.9kΩ. 3. For 50Ω setup. R1 = 62Ω, R3 = 75Ω for 75Ω application. 4. For test configuration R4 = 0Ω (GND) and C2 = 18pF. 5. 0Ω chip resistors (jumpers) may be substituted with minor degradation of performance. 1996 Feb 1 4 Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A NE568A KT10/89 GND VCC VOUT VIN SR01040 Figure 4. N Package Layout (Not Actual Size) GND SIGNETICS NE568A SO VCC OUTPUT INPUT SR01041 1.25E3 1.25E3 1.0E3 1.0E3 750.0 ZIN 500.0 250.0 0.0 1.0 RIN 500.0 250.0 10.0 0.0 1.0 100.0 FREQUENCY (MHz) 10.0 100.0 1.0E3 FREQUENCY (MHz) SR01042 SR01043 Figure 6. NE568A Input Impedance With CP = 0.5pF 20-Pin SO Package 1996 Feb 1 ZIN 750.0 Z IN Ω Z IN Ω Figure 5. D Package Layout (Not Actual Size) Figure 7. NE568A Input Impedance WithCP = 1.49pF 20-Pin Dual In-Line Plastic Package 5 Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A 4.0 VOLTS 3.5 3.0 2.5 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz) SR01044 Figure 8. Typical Output Linearity 100 80 78 FO MHz 95 76 74 90 72 70 85 68 75 64 ICC 62 60 I CC mA MHz FO 66 80 58 70 56 54 65 52 50 60 48 46 55 44 42 50 40 0.8 0.9 1.0 1.1 1.2 1.3 Frequency Adjust (kΩ) Figure 9. NE568: Frequency Adjust vs FO and ICC 1996 Feb 1 6 1.4 1.5 1.6 SR01045 Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A 12.0 11.5 C = 6.8pF 11.0 10.5 10.0 9.5 R tc (k Ω ) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 C = 16pF 4.0 3.5 C = 150pF 3.0 2.5 2.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 FO MHz 160 SR01046 Figure 10. NE568A: Rtc (Pin 13) vs FO; Choosing the Optimum Temperature Compensation Resistor RFC1 10µH +5V VCC + C6 10µF C1 0.1µF C5 0.1µF 1 VCC2 LF1 20 2 GND2 LF2 19 3 GND LF3 18 GND1 J1 4 C2 18pF TCAP1 LF4 17 5 6 C8 0.1µF 7 C3 0.1µF 8 C4 0.1µF C10 560pF C9 47pF R6 1.5kΩ TCAP2 FREQADJ 9 GND1 R2 2kΩ OUTFILT VCC1 VOUT REFBYP TCADJ2 PNPBYP TCADJ1 (Optional. Leave it open if not used) 16 NE/SA568A RFC2 10µH R1 27Ω 15 14 13 C12 0.1µF (Output Amp Gain Adj -2dB) C11 47pF J3 VOUT R3 43Ω (ZO = 50Ω)* R4 3.9kΩ 12 J2 VIN 10 INPBYP VIN 11 C7 0.1µF C13 0.1µF R5 51Ω *NOTE: For 75Ω output impedance, use R3 = 68Ω. SR01113 Figure 11. Phase Locked Loop NE/SA568A 1996 Feb 1 7 Philips Semiconductors Product specification 150MHz phase-locked loop NE/SA568A NE568AN C10 70MHz PLL10569 RFC2 +5V C9 C1 R2 R1 RFC1 C5 C6 COMPONENTS LAYOUT C11 R6 C2 GND C12 R4 R3 OUT C13 C3 C8 C4 IN C7 R5 TOP BOTTOM SR01114 Figure 12. NE568AN Board Layout (Not Actual Size) 1996 Feb 1 8 Philips Semiconductors Product specification 70MHz PLL10570 U1 560pF C10 27 C9 47pF R1 R2 2K NE568AD R5 C11 47pF 43 3.9k 0.1µF 0.1µF R3 C12 R4 10 µ H 18pF C4 0.1 µ F C7 0.1µF VOUT J3 C13 51 J2 VIN NE568AD 10 µ H RFC1 C3 0.1 µ F RFC2 J1 C8 0.1 µ F 10 µ F C6 GND R6 1.5k C1 0.1µF C5 +5V NE/SA568A 0.1 µ F 150MHz phase-locked loop SR01115 Figure 13. NE568AD Board Layout (Not Actual Size) 1996 Feb 1 9