AD ADP1870ARMZ-0.3-R7

Synchronous Buck Controller with
Constant On-Time and Valley Current Mode
ADP1870/ADP1871
FEATURES
TYPICAL APPLICATIONS CIRCUIT
VIN = 2.95V TO 20V
VIN
CC
VOUT
RTOP
RC
ADP1870/
ADP1871
CC2
COMP/EN BST
CBST
FB
COUT
Q2
SW
VREG
DRVL
PGND
RRES
LOAD
Figure 1.
100
VIN = 5V (PSM)
95
90
75
EFFICIENCY (%)
80
VIN = 16.5V
70
65
VIN = 13V
60
VIN = 13V (PSM)
55
50
45
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well
suited for a wide range of applications that require a single-input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal LDO.
VOUT
CVREG
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
The ADP1871 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1871)
section for more information).
L
08730-001
GND
CVREG2
85
The ADP1870/ADP1871 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable currentlimit, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by utilizing valley
current-mode control architecture. This allows the ADP1870/
ADP1871 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.
Q1
DRVH
RBOT
APPLICATIONS
GENERAL DESCRIPTION
CIN
40 VIN = 16.5V (PSM)
35
30
25
10
100
TA = 25°C
VOUT = 1.8V
fSW = 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
10k
LOAD CURRENT (mA)
100k
08730-102
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1871 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged load
Small, 10-lead MSOP package
Figure 2. Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
In addition, an internally fixed soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulsewidth modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1870/ADP1871 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP
package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADP1870/ADP1871
TABLE OF CONTENTS
Features .............................................................................................. 1 Power Saving Mode (PSM) Version (ADP1871) ................... 22 Applications ....................................................................................... 1 Timer Operation ........................................................................ 22 General Description ......................................................................... 1 Pseudo-Fixed Frequency ........................................................... 23 Typical Applications Circuit............................................................ 1 Applications Information .............................................................. 24 Revision History ............................................................................... 2 Feedback Resistor Divider ........................................................ 24 Specifications..................................................................................... 3 Inductor Selection ...................................................................... 24 Absolute Maximum Ratings............................................................ 5 Output Ripple Voltage (ΔVRR) .................................................. 24 Thermal Resistance ...................................................................... 5 Output Capacitor Selection....................................................... 24 Boundary Condition .................................................................... 5 Compensation Network ............................................................ 25 ESD Caution .................................................................................. 5 Efficiency Considerations ......................................................... 26 Pin Configuration and Function Descriptions ............................. 6 Input Capacitor Selection .......................................................... 27 Typical Performance Characteristics ............................................. 7 Thermal Considerations............................................................ 28 ADP1870/ADP1871 Block Diagram............................................ 18 Design Example .......................................................................... 29 Theory of Operation ...................................................................... 19 External Component Recommendations .................................... 31 Startup .......................................................................................... 19 Layout Considerations ................................................................... 33 Soft Start ...................................................................................... 19 IC Section (Left Side of Evaluation Board) ............................. 37 Precision Enable Circuitry ........................................................ 19 Power Section ............................................................................. 37 Undervoltage Lockout ............................................................... 19 Differential Sensing .................................................................... 38 On-Board Low Dropout Regulator .......................................... 19 Typical Applications Circuits ........................................................ 39 Thermal Shutdown..................................................................... 20 15 A, 300 kHz High Current Application Circuit .................. 39 Programming Resistor (RES) Detect Circuit .......................... 20 5.5 V Input, 600 kHz Application Circuit ............................... 39 Valley Current-Limit Setting .................................................... 20 300 kHz High Current Application Circuit ............................ 40 Hiccup Mode During Short Circuit ......................................... 21 Outline Dimensions ....................................................................... 41 Synchronous Rectifier ................................................................ 22 Ordering Guide .......................................................................... 41 REVISION HISTORY
3/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
ADP1870/ADP1871
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
VBST − VSW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range
Quiescent Current
Shutdown Current
Undervoltage Lockout
UVLO Hysteresis
INTERNAL REGULATOR
CHARACTERISTICS
VREG Operational Output Voltage
Symbol
Conditions
VIN
CIN = 22 μF to PGND (at Pin 1)
ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz)
ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz)
ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz)
VFB = 1.5 V, no switching
COMP/EN < 285 mV
IQ_REG + IQ_BST
IREG,SD +
IBST,SD
UVLO
VREG
VREG Output in Regulation
Load Regulation
Line Regulation
VIN to VREG Dropout Voltage
Short VREG to PGND
SOFT START
Soft Start Period
ERROR AMPLIFER
FB Regulation Voltage
Transconductance
FB Input Leakage Current
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from DRVL to PGND
SWITCHING FREQUENCY
ADP1870ARMZ-0.3/
ADP1871ARMZ-0.3 (300 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
Min
Typ
Max
Unit
2.95
2.95
3.25
12
12
12
1.1
190
20
20
20
V
V
V
mA
μA
Rising VIN (see Figure 35 for temperature variation)
Falling VIN from operational state
CVREG = 1 μF to PGND, 0.22 μF to GND, VIN = 2.95 V to 20 V
ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz)
ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz)
ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz)
VIN = 7 V, 100 mA
VIN = 12 V, 100 mA
0 mA to 100 mA, VIN = 7 V
0 mA to 100 mA, VIN = 20 V
VIN = 7 V to 20 V, 20 mA
VIN = 7 V to 20 V, 100 mA
100 mA out of VREG, VIN ≤ 5 V
VIN = 20 V
2.65
190
2.75
2.75
3.05
4.8
4.8
See Figure 58
VFB
Gm
IFB, Leak
TJ = +25°C
TJ = −40°C to +85°C
TJ = −40°C to +125°C
280
5
5
5
4.981
4.982
32
33
2.5
2.0
300
229
V
mV
5.5
5.5
5.5
5.16
5.16
415
320
3.0
V
V
V
V
V
mV
mV
mV
mV
mV
mA
ms
596
594.2
320
600
600
600
496
1
604
605.8
670
50
mV
mV
mV
μS
nA
RES = 47 kΩ ± 1%
2.7
3
3.3
V/V
RES = 22 kΩ ± 1%
RES = none
RES = 100 kΩ ± 1%
Typical values measured at 50% time points with 0 nF
at DRVH and DRVL; maximum values are guaranteed
by bench evaluation 1
5.5
11
22
6
12
24
6.5
13
26
V/V
V/V
V/V
VFB = 0.6 V, COMP/EN = released
300
VIN = 5 V, VOUT = 2 V, TJ = 25°C
VIN = 20 V
84% duty cycle (maximum)
Rev. 0 | Page 3 of 44
1120
1200
146
340
kHz
1280
190
400
ns
ns
ns
ADP1870/ADP1871
Parameter
ADP1870ARMZ-0.6/
ADP1871ARMZ-0.6 (600 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
ADP1870ARMZ-1.0/
ADP1871ARMZ-1.0 (1.0 MHz)
On-Time
Minimum On-Time
Minimum Off-Time
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time 2
Fall Time2
Low-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time2
Fall Time2
Propagation Delays
DRVL Fall to DRVH Rise2
DRVH Fall to DRVL Rise2
SW Leakage Current
Integrated Rectifier
Channel Impedance
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
COMP VOLTAGE
COMP Clamp Low Voltage
Symbol
Conditions
Min
Typ
600
Max
Unit
kHz
VIN = 5 V, VOUT = 2 V, TJ = 25°C
VIN = 20 V, VOUT = 0.8 V
65% duty cycle (maximum)
500
540
82
340
1.0
580
110
400
ns
ns
ns
MHz
VIN = 5 V, VOUT = 2 V, TJ = 25°C
VIN = 20 V
45% duty cycle (maximum)
285
312
60
340
340
85
400
ns
ns
ns
2.25
0.7
25
11
3
1
tr,DRVH
tf,DRVH
ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V)
ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V)
VBST − VSW = 4.4 V, CIN = 4.3 nF (see Figure 60)
VBST − VSW = 4.4 V, CIN = 4.3 nF (see Figure 61)
Ω
Ω
ns
ns
1.6
0.7
18
16
2.2
1
tr,DRVL
tf,DRVL
ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V)
ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V)
VREG = 5.0 V, CIN = 4.3 nF (see Figure 61)
VREG = 5.0 V, CIN = 4.3 nF (see Figure 60)
Ω
Ω
ns
ns
ttpdhDRVH
ttpdhDRVL
ISWLEAK
VBST − VSW = 4.4 V (see Figure 60)
VBST − VSW = 4.4 V (see Figure 61)
VBST = 25 V, VSW = 20 V, VREG = 5 V
15.4
18
ISINK = 10 mA
22
COMP Clamp High Voltage
COMP Zero Current Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Hiccup Current Limit Timing
VCOMP(high)
VCOMP_ZCT
TTMSD
VCOMP(low)
110
VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V
VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V
245
From disabled state, release COMP/EN pin to enable
device (2.75 V ≤ VREG ≤ 5.5 V)
(2.75 V ≤ VREG ≤ 5.5 V)
(2.75 V ≤ VREG ≤ 5.5 V)
0.47
Rising temperature
1
285
37
ns
ns
μA
Ω
330
mV
mV
V
1.07
2.55
V
V
155
15
6
°C
°C
ms
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), CGATE = 4.3 nF, and the upper- and lower-side
MOSFETs being Infineon BSC042N03MSG.
2
Not automatic test equipment (ATE) tested.
Rev. 0 | Page 4 of 44
ADP1870/ADP1871
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VREG to PGND, GND
VIN to PGND
FB, COMP/EN to GND
DRVL to PGND
SW to PGND
BST to SW
BST to PGND
DRVH to SW
PGND to GND
θJA (10-Lead MSOP)
2-Layer Board
4-Layer Board
Operating Junction Temperature
Range
Storage Temperature Range
Soldering Conditions
Maximum Soldering Lead
Temperature (10 sec)
THERMAL RESISTANCE
Rating
−0.3 V to +6 V
−0.3 V to +28 V
−0.3 V to (VREG + 0.3 V)
−0.3 V to (VREG + 0.3 V)
−2.0 V to +28 V
−0.6 V to (VREG + 0.3 V)
−0.3 V to 28 V
−0.3 V to VREG
±0.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
213.1°C/W
171.7°C/W
−40°C to +125°C
BOUNDARY CONDITION
Table 3. Thermal Resistance
Package Type
θJA (10-Lead MSOP)
2-Layer Board
4- Layer Board
1
θJA1
Unit
213.1
171.7
°C/W
°C/W
θJA is specified for the worst-case conditions; that is, θJA is specified for the
device soldered in a circuit board for surface-mount packages.
In determining the values given in Table 2 and Table 3, natural
convection was used to transfer heat to a 4-layer evaluation board.
−65°C to +150°C
JEDEC J-STD-020
300°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
Rev. 0 | Page 5 of 44
ADP1870/ADP1871
VIN 1
FB 3
ADP1870/
ADP1871
GND 4
TOP VIEW
(Not to Scale)
COMP/EN 2
VREG 5
10
BST
9
SW
8
DRVH
7
PGND
6
DRVL
08730-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
VIN
COMP/EN
FB
GND
5
VREG
6
DRVL
7
8
9
10
PGND
DRVH
SW
BST
Description
High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations section).
Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers).
A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended.
Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 69).
Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET.
Drive Output for the External Upper-Side, N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VREG and BST for increased gate drive capability.
Rev. 0 | Page 6 of 44
ADP1870/ADP1871
VIN = 16.5V
VIN = 13V
TA = 25°C
VOUT = 0.8V
fSW = 300kHz
WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
100k
EFFICIENCY (%)
08730-105
EFFICIENCY (%)
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 16.5V
TA = 25°C
VOUT = 7V
fSW = 300kHz
WÜRTH INDUCTOR:
7443551200, L = 2.0µH, DCR = 2.6mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
100k
08730-106
EFFICIENCY (%)
100
1k
10k
100k
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
VIN = 13V
VIN = 13V (PSM)
VIN = 16.5V
VIN = 16.5V (PSM)
TA = 25°C
VOUT = 1.8V
fSW = 600kHz
WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
100
1k
10k
100k
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
VIN = 13V
10k
WÜRTH INDUCTOR:
744355147, L = 0.47µH, DCR = 0.67mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
LOAD CURRENT (mA)
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
1k
TA = 25°C
VOUT = 0.8V
fSW = 600kHz
VIN = 16.5V
(PSM)
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
100
95
VIN = 5V (PSM)
90
85
80
75
70
VIN = 16.5V
65
VIN = 13V (PSM)
60
55
VIN = 13V
50
45
40 VIN = 16.5V (PSM)
35
TA = 25°C
30
VOUT = 1.8V
25
fSW = 300kHz
20
WÜRTH INDUCTOR:
15
744325120, L = 1.2µH, DCR = 1.8mΩ
10
INFINEON FETs:
5
BSC042N03MS G (UPPER/LOWER)
0
10
100
1k
10k
100k
LOAD CURRENT (mA)
VIN = 16.5V
LOAD CURRENT (mA)
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
100
95 VIN = 16.5V (PSM)
90
85
80
75 V = 13V (PSM)
IN
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
100
VIN = 13V (PSM)
08730-108
10k
VIN = 13V
Figure 6. Efficiency—300 kHz, VOUT = 7 V
100
VIN = 13V (PSM)
95
90 V = 16.5V (PSM)
IN
85
80
75
70
65
VIN = 16.5V
60
55
50
VIN = 20V (PSM)
VIN = 20V
45
40
35
TA = 25°C
30
VOUT = 5V
25
fSW = 600kHz
20
WÜRTH INDUCTOR:
15
744318180, L = 1.4µH, DCR = 3.2mΩ
10
INFINEON FETs:
5
BSC042N03MS G (UPPER/LOWER)
0
10
100
1k
10k
100k
LOAD CURRENT (mA)
Figure 9. Efficiency—600 kHz, VOUT = 5 V
Rev. 0 | Page 7 of 44
08730-109
1k
LOAD CURRENT (mA)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
08730-107
EFFICIENCY (%)
100
95
90
85
VIN = 13V (PSM)
80
75
70
65
60
55
50
45
40
35 V = 16.5V (PSM)
IN
30
25
20
15
10
5
0
10
100
08730-104
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
0.807
100
95
90
85
80
75
70
65 VIN = 13V (PSM)
60
55
50
45
40
35
30
VIN = 16.5V (PSM)
25
20
15
10
5
0
10
100
0.806
VIN = 13V
0.805
VIN = 16.5V
TA = 25°C
VOUT = 0.8V
fSW = 1.0MHz
10k
100k
LOAD CURRENT (mA)
0.798
0.797
0.796
VIN = 13V
+125°C
+25°C
–40°C
0.792
0
2000
VIN = 16.5V
+125°C
+25°C
–40°C
4000
6000
8000
10,000
LOAD CURRENT (mA)
1.821
VIN = 13V
VIN = 16.5V
TA = 25°C
VOUT = 1.8V
fSW = 1.0MHz
WÜRTH INDUCTOR:
744303022, L = 0.22µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
10k
100k
TA = 25°C
VOUT = 5V
fSW = 1.0MHz
0
VIN = 13V
+125°C
+25°C
–40°C
VIN = 16.5V
+125°C
+25°C
–40°C
1500
3000
4500
6000
7500
9000 10,500 12,000 13,500 15,000
LOAD CURRENT (mA)
100k
08730-112
WÜRTH INDUCTOR:
744355090, L = 0.9µH, DCR = 1.6mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
10k
VIN = 5.5V
+125°C
+25°C
–40°C
1.786
OUTPUT VOLTAGE (V)
VIN = 13V
1k
1.796
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
VIN = 16.5V
LOAD CURRENT (mA)
1.801
1.791
VIN = 13V (PSM)
VIN = 16.5V (PSM)
1.806
Figure 12. Efficiency—1.0 MHz, VOUT = 5 V
7.100
7.095
7.090
7.085
7.080
7.075
7.070
7.065
7.060
7.055
7.050
7.045
7.040
7.035
7.030
7.025
7.020
7.015
7.010
7.005
7.000
+125°C
+25°C
–40°C
0
1000
2000
VIN = 13V
VIN = 16.5V
3000
4000
5000
6000
7000
8000
LOAD CURRENT (mA)
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
Rev. 0 | Page 8 of 44
9000
08730-015
1k
1.811
08730-014
OUTPUT VOLTAGE (V)
1.816
08730-111
EFFICIENCY (%)
EFFICIENCY (%)
0.799
0.793
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
100
0.800
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
LOAD CURRENT (mA)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
0.801
0.794
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
100
95
90
85
80
VIN = 13V (PSM)
75
70
65
60
55
50
45
40 V = 16.5V (PSM)
IN
35
30
25
20
15
10
5
0
10
100
0.802
0.795
WÜRTH INDUCTOR:
744303012, L = 0.12µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
0.803
08730-013
OUTPUT VOLTAGE (V)
0.804
08730-110
EFFICIENCY (%)
ADP1870/ADP1871
ADP1870/ADP1871
0.808
0.807
0.805
0.806
0.803
OUTPUT VOLTAGE (V)
FREQUENCY (kHz)
0.804
0.802
0.800
0.798
0.801
0.799
0.797
0.795
0.793
0.796
0.791
0.792
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
0.787
0
6000
8000
10,000
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V
OUTPUT VOLTAGE (V)
1.815
1500
3000
4500
VIN = 16.5V
+125°C
+25°C
–40°C
6000
7500
9000
1.810
1.805
1.800
VIN = 13V
+125°C
+25°C
–40°C
1.795
10,500 12,000
LOAD CURRENT (mA)
VIN = 16.5V
+125°C
+25°C
–40°C
1.790
0
08730-019
VIN = 13V
+125°C
+25°C
–40°C
08730-016
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
5.030
5.04
5.025
5.03
5.02
5.020
5.01
OUTPUT VOLTAGE (V)
5.015
5.010
5.005
5.000
4.995
4.990
4.985
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.980
4.975
4.970
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
VIN = 13V
+125°C
+25°C
–40°C
4.92
VIN = 13V
VIN = 16.5V
VIN = 20V
4.91
08730-017
+125°C
+25°C
–40°C
Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V
VIN = 16.5V
+125°C
+25°C
–40°C
4.90
0
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
LOAD CURRENT (mA)
Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT =5 V
Rev. 0 | Page 9 of 44
08730-020
OUTPUT VOLTAGE (V)
4000
1.820
0
OUTPUT VOLTAGE (V)
2000
VIN = 16.5V
+125°C
+25°C
–40°C
LOAD CURRENT (mA)
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V
1.818
1.816
1.814
1.812
1.810
1.808
1.806
1.804
1.802
1.800
1.798
1.796
1.794
1.792
1.790
1.788
1.786
1.784
1.782
1.780
1.778
1.776
1.774
1.772
1.770
VIN = 13V
+125°C
+25°C
–40°C
0.789
VIN = 13V
VIN = 16.5V
08730-118
+125°C
+25°C
–40°C
08730-115
0.794
ADP1870/ADP1871
601.0
900
SWITCHING FREQUENCY (kHz)
600.0
599.5
VREG = 5V, VIN = 13V
599.0
598.5
598.0
597.5
840
820
800
780
760
740
25.0
57.5
90.0
700
13.0
08730-121
–7.5
122.5
TEMPERATURE (°C)
+125°C
+25°C
–40°C
315
14.0
14.5
15.0
15.5
16.0
16.5
VIN (V)
Figure 22. Feedback Voltage vs. Temperature
325
13.5
08730-124
720
597.0
–40.0
Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,
VIN Range = 13 V to 16.5 V
280
NO LOAD
VIN = 13V
VIN = 20V
VIN = 16.5V
265
+125°C
+25°C
–40°C
305
FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
860
295
285
250
235
220
275
205
265
VIN (V)
190
08730-022
255
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
0
+125°C
+25°C
–40°C
4000
6000
8000
10,000
LOAD CURRENT (mA)
Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V
650
2000
08730-025
FEEDBACK VOLTAGE (V)
VREG = 5V, VIN = 30V
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
330
NO LOAD
VIN = 20V
VIN = 13V
VIN = 16.5V
320
600
+125°C
+25°C
–40°C
310
FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
+125°C
+25°C
–40°C
880
600.5
550
500
300
290
280
270
260
450
13.4
13.8
14.2
14.6
15.0
VIN (V)
15.4
15.8
16.2
Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V,
VIN Range = 13 V to 16.5 V
Rev. 0 | Page 10 of 44
240
0
1500
3000
4500
6000
7500
9000 10,500 12,000 13,500 15,00
LOAD CURRENT (mA)
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
08730-026
400
13.0
08730-123
250
ADP1870/ADP1871
VIN = 13V
VIN = 16.5V
334
+125°C
+25°C
–40°C
326
FREQUENCY (kHz)
FREQUENCY (kHz)
330
322
318
314
310
306
298
0
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800
LOAD CURRENT (mA)
08730-027
302
510
+125°C
+25°C
–40°C
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
LOAD CURRENT (mA)
Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V
850
+125°C
+25°C
–40°C
VIN = 13V
VIN = 16.5V
VIN = 13V
VIN = 16.5V
0
Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
540
740
733
726
719
712
705
698
691
684
677
670
663
656
649
642
635
628
621
08730-030
338
VIN = 13V
VIN = 16.5V
+125°C
+25°C
–40°C
775
FREQUENCY (kHz)
FREQUENCY (kHz)
480
450
420
390
700
625
550
360
0
1200
2400
3600
4800
6000
7200
8400
400
08730-028
300
9600 10,800 12,000
LOAD CURRENT (mA)
0
6000
8000
10,000
12,000
Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
675
1225
VIN = 13V
VIN = 16.5V
655
4000
LOAD CURRENT (mA)
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
VIN = 13V
VIN = 16.5V
1150
635
+125°C
+25°C
–40°C
FREQUENCY (kHz)
1075
615
595
575
555
535
1000
925
850
775
700
+125°C
+25°C
–40°C
495
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
625
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
550
0
1200
2400
3600
4800
6000
7200
8400
9600 10,800 12,000
LOAD CURRENT (mA)
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
Rev. 0 | Page 11 of 44
08730-032
515
08730-029
FREQUENCY (kHz)
2000
08730-031
475
330
ADP1870/ADP1871
1450
82
VIN = 13V
VIN = 16.5V
1400
+125°C
+25°C
–40°C
MAXIMUM DUTY CYCLE (%)
1300
1250
1200
1150
1100
78
76
74
72
70
68
66
1050
800
1600 2400 3200 4000 4800 5600 6400 7200 8000
LOAD CURRENT (mA)
62
5.5
08730-033
0
7.9
9.1
10.3
11.5
12.7
13.9
15.1
16.3
VIN (V)
Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V
Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN)
680
2.657
630
2.656
580
MINUMUM OFF-TIME (ns)
2.658
2.655
2.654
2.653
2.652
2.651
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
530
480
430
380
330
280
2.650
230
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
180
–40
08730-034
2.649
–40
6.7
08730-036
64
1000
–20
0
20
40
60
80
680
+125°C
+25°C
–40°C
90
120
Figure 38. Minimum Off-Time vs. Temperature
Figure 35. UVLO vs. Temperature
95
100
TEMPERATURE (°C)
08730-037
FREQUENCY (kHz)
1350
UVLO (V)
+125°C
+25°C
–40°C
80
+125°C
+25°C
–40°C
630
MINUMUM OFF-TIME (ns)
80
75
70
65
530
480
430
380
330
280
60
400
500
600
700
800
900
FREQUENCY (kHz)
1000
180
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage)
Figure 36. Maximum Duty Cycle vs. Frequency
Rev. 0 | Page 12 of 44
08730-038
55
300
230
08730-035
MAXIMUM DUTY CYCLE (%)
580
85
ADP1870/ADP1871
80
+125°C
+25°C
–40°C
RECTIFIER DROP (mV)
640
560
480
400
320
240
160
400
500
600
700
800
900
1000
FREQUENCY (kHz)
1200
1120
VIN = 5.5V
VIN = 13V
VIN = 16.5V
1MHz
300kHz
48
40
32
24
16
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 43. Lower-Side MOSFET Body Diode Conduction Time vs. VREG
TA = 25°C
OUTPUT VOLTAGE
1
1040
RECTIFIER DROP (mV)
56
8
2.7
Figure 40. Internal Rectifier Drop vs. Frequency
1280
+125°C
+25°C
–40°C
64
08730-039
80
300
300kHz
1MHz
72
08730-042
720
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
BODY DIODE CONDUCTION TIME (ns)
800
960
880
800
INDUCTOR CURRENT
720
2
640
560
SW NODE
480
400
3
320
240
LOW SIDE
160
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
640
300kHz
1MHz
CH2 5A Ω
CH4 5V
M400ns
T 35.8%
A CH2
3.90A
Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA
Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage)
Over VIN Variation
720
CH1 50mV BW
CH3 10V BW
08730-043
3.1
08730-040
80
2.7
4
+125°C
+25°C
–40°C
OUTPUT VOLTAGE
INDUCTOR CURRENT
480
2
400
320
SW NODE
240
3
160
LOW SIDE
80
2.7
3.1
3.5
3.9
4.3
4.7
5.1
VREG (V)
5.5
Figure 42. Internal Boost Rectifier Drop vs. VREG
CH1 50mV BW
CH3 10V BW
CH2 5A Ω
CH4 5V
M4.0µs
T 35.8%
A CH2
3.90A
Figure 45. PSM Waveform at Light Load, 500 mA
Rev. 0 | Page 13 of 44
08730-044
4
08730-041
RECTIFIER DROP (mV)
1
560
ADP1870/ADP1871
OUTPUT VOLTAGE
2
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
12A NEGATIVE STEP
1
SW NODE
1
3
SW NODE
LOW SIDE
3
CH4 100mV
B
W
M400ns
T 30.6%
A CH3
2.20V
CH1 10A Ω
CH3 20V
CH2 200mV
CH4 5V
B
W M20µs
A CH1
3.40A
T 48.2%
08730-048
CH1 5A Ω
CH3 10V
08730-045
4
Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
12 A (See Figure 93 Application Circuit)
Figure 46. CCM Operation at Heavy Load, 12 A
(See Figure 93 for Application Circuit)
OUTPUT VOLTAGE
2
4
OUTPUT VOLTAGE
12A STEP
12A STEP
LOW SIDE
1
1
SW NODE
3
2
SW NODE
LOW SIDE
4
B
W
M2ms
T 75.6%
A CH1
3.40A
CH1 10A Ω
CH3 20V
Figure 47. Load Transient Step—PSM Enabled, 12 A
(See Figure 93 Application Circuit)
CH2 5V
CH4 200mV
B
W
M2ms
T 15.6%
A CH1
6.20A
08730-049
CH2 200mV
CH4 5V
08730-046
3
CH1 10A Ω
CH3 20V
Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A
(See Figure 93 Application Circuit)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
2
4
12A POSITIVE STEP
12A POSITIVE STEP
SW NODE
1
LOW SIDE
1
3
2
SW NODE
LOW SIDE
4
B
W M20µs
T 30.6%
A CH1
3.40A
CH1 10A Ω
CH3 20V
Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
12 A, VOUT = 1.8 V (See Figure 93 Application Circuit)
CH2 5V
CH4 200mV
M20µs
B
W T 43.8%
A CH1
6.20A
08730-050
CH2 200mV
CH4 5V
08730-047
3
CH1 10A Ω
CH3 20V
Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A, VOUT = 1.8 V (See Figure 93 Application Circuit)
Rev. 0 | Page 14 of 44
ADP1870/ADP1871
OUTPUT VOLTAGE
2
OUTPUT VOLTAGE
1
INDUCTOR CURRENT
12A NEGATIVE STEP
2
1
SW NODE
LOW SIDE
4
3
SW NODE
LOW
SIDE
CH2 200mV
CH4 5V
B
W M10µs
A CH1
5.60A
T 23.8%
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A (See Figure 93 Application Circuit)
M2ms
T 32.8%
A CH1
720mV
08730-054
CH1 10A Ω
CH3 20V
3
08730-051
4
Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz
(See Figure 93 Application Circuit)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1
1
INDUCTOR CURRENT
2
INDUCTOR CURRENT
LOW SIDE
2
LOW SIDE
4
4
SW NODE
SW NODE
3
M4ms
T 49.4%
A CH1
920mV
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode
1
M4ms
T 41.6%
A CH1
720mV
08730-055
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
08730-052
3
Figure 56. Power-Down Waveform During Heavy Load
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1
INDUCTOR CURRENT
INDUCTOR CURRENT
2
2
SW NODE
SW NODE
3
3
LOW SIDE
LOW SIDE
4
CH2 10A Ω
CH4 5V
M10µs
T 36.2%
A CH2
8.20A
CH1 50mV BW
CH3 10V BW
CH2 5A Ω
CH4 5V
M2µs
T 35.8%
A CH2
3.90A
08730-056
CH3 10V
08730-053
4
CH1 5V BW
Figure 57. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
Figure 54. Magnified Waveform During Hiccup Mode
Rev. 0 | Page 15 of 44
ADP1870/ADP1871
18ns (tr,DRVL )
LOW SIDE
OUTPUT VOLTAGE
1
4
24ns (tpdh,DRVL )
HIGH SIDE
LOW SIDE
4
HS MINUS
SW
11ns (tf,DRVH )
SW NODE
SW NODE
3
2
3
M
INDUCTOR CURRENT
CH2 5A Ω
CH4 2V
M1ms
T 63.2%
A CH1
1.56V
08730-057
CH1 1V BW
CH3 10V BW
CH2 5V
CH3 5V
CH4 2V
MATH 2V 20ns
Figure 58. Soft Start and RES Detect Waveform
A CH2
4.20V
Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms
(CIN = 4.3 nF (Upper-/Lower-Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
TA = 25°C
VREG = 5.5V
VREG = 3.6V
VREG = 2.7V
570
TRANSCONDUCTANCE (µS)
LOW SIDE
M20ns
T 39.2%
4
HIGH SIDE
SW NODE
3
2
550
530
510
490
470
HS MINUS
SW
M40ns
T 29.0%
A CH2
4.20V
430
–40
08730-058
CH3 5V
MATH 2V 40ns
CH2 5V
CH4 2V
20
40
60
80
100
120
Figure 62. Transconductance (Gm) vs. Temperature
680
TA = 25°C
16ns (tf,DRVL )
0
TEMPERATURE (°C)
Figure 59. Output Drivers and SW Node Waveforms
LOW SIDE
–20
08730-061
450
M
+125°C
+25°C
–40°C
TRANSCONDUCTANCE (µS)
630
4
08730-060
TA = 25°C
2
22ns (tpdhDRVH )
HIGH SIDE
25ns (tr,DRVH)
SW NODE
580
530
480
430
3
2
CH2 5V
CH3 5V
CH4 2V
MATH 2V 40ns
M40ns
T 29.0%
A CH2
4.20V
330
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
VREG (V)
Figure 60. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms
(CIN = 4.3 nF (Upper-/Lower-Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
Rev. 0 | Page 16 of 44
Figure 63. Transconductance (Gm) vs. VREG
5.1
5.4
08730-062
380
HS MINUS
SW
08730-059
M
ADP1870/ADP1871
1.30
1.25
1.15
+125°C
1.10
1.05
+25°C
1.00
0.95
–40°C
0.90
0.85
0.80
0.75
0.70
2.7
3.1
3.5
3.9
4.3
4.7
VREG (V)
5.1
5.5
08730-163
QUIESCENT CURRENT (mA)
1.20
Figure 64. Quiescent Current vs. VREG
Rev. 0 | Page 17 of 44
ADP1870/ADP1871
ADP1870/ADP1871 BLOCK DIAGRAM
ADP1870/ADP1871
VREG
tON TIMER
VIN
C
PRECISION
ENABLE BLOCK
TO ENABLE
ALL BLOCKS
LDO
I
SW
INFORMATION
R (TRIMMED)
VREG
tON = 2RC(VOUT/VIN)
REF
SW FILTER
VREG
BST
BIAS BLOCK
AND REFERENCE
STATE
MACHINE
REF_ZERO
TON
BG_REF
ISS
SS
COMP
PSM
CSS
BG_REF
BG_REF
HI
INL_HICC
SW
SS_REF
ERROR
AMP
FB
HS
SW
8kΩ
BG_REF
BG_REF
0.6V
LEVEL
SHIFT
LO
VREG
LS
DRVL
PGND
PWM
IREV
COMP
LOWER
COMP
CLAMP
CS
AMP
REF_ZERO
ADC
RES DETECT AND
GAIN SET
CS GAIN SET
0.4V
08730-063
COMP/
EN
DRVH
300kΩ
GND
Figure 65. ADP1870/ADP1871 Block Diagram
Rev. 0 | Page 18 of 44
ADP1870/ADP1871
THEORY OF OPERATION
ADP1870/ADP1871, reducing the supply current of the devices
to approximately 140 μA. For more information, see Figure 67.
ADP1870/ADP1871
FB
VREG
SS
COMP/EN
STARTUP
CC
The ADP1870/ADP1871 have an internal regulator (VREG) for
biasing and supplying power for the integrated MOSFET drivers.
A bypass capacitor should be located directly across the VREG
(Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence
is the biasing of the current-sense amplifier, the current-sense
gain circuit (see the Programming Resistor (RES) Detect Circuit
section), the soft start circuit, and the error amplifier.
RC
SOFT START
The ADP1870/ADP1871 have digital soft start circuitry, which
involves a counter that initiates an incremental increase in current,
by 1 μA, via a current source on every cycle through a fixed internal
capacitor. The output tracks the ramping voltage by producing
PWM output pulses to the upper-side MOSFET. The purpose is to
limit the in-rush current from the high voltage input supply (VIN)
to the output (VOUT).
PRECISION ENABLE CIRCUITRY
The ADP1870/ADP1871 employ precision enable circuitry. The
enable threshold is 285 mV typical with 35 mV of hysteresis.
The devices are enabled when the COMP/EN pin is released,
allowing the error amplifier output to rise above the enable
threshold (see Figure 66). Grounding this pin disables the
0.6V
PRECISION
ENABLE
285mV
08730-064
TO ENABLE
ALL BLOCKS
Figure 66. Release COMP/EN Pin to Enable the ADP1870/ADP1871
COMP/EN
The current-sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing 0.4 V across the DRVL output
and PGND pin, which generates a current depending on the
resistor across DRVL and PGND in a process performed by the
RES detect circuit. The current through the resistor is used to set
the current-sense amplifier gain. This process takes approximately
800 μs, after which the drive signal pulses appear at the DRVL
and DRVH pins synchronously and the output voltage begins to
rise in a controlled manner through the soft start sequence.
The rise time of the output voltage is determined by the soft
start and error amplifier blocks (see the Soft Start section). At
the beginning of a soft start, the error amplifier charges the
external compensation capacitor, causing the COMP/EN pin to
rise above the enable threshold of 285 mV, thus enabling the
ADP1870/ADP1871.
CC2
ERROR
AMPLIFIER
>2.4V
2.4V
1.0V
HICCUP MODE INITIALIZED
MAXIMUM CURRENT (UPPER CLAMP)
ZERO CURRENT
USABLE RANGE ONLY AFTER SOFT START
PERIOD IF CONTUNUOUS CONDUCTION
MODE OF OPERATION IS SELECTED.
500mV
285mV
0V
LOWER CLAMP
PRECISION ENABLE THRESHOLD
35mV HYSTERESIS
08730-065
The ADP1870/ADP1871 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by utilizing valley
current-mode control architecture. This allows the ADP1870/
ADP1871 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.
Figure 67. COMP/EN Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part from
operating both the upper- and lower-side MOSFETs at extremely
low or undefined input voltage (VIN) ranges. Operation at an
undefined bias voltage may result in the incorrect propagation
of signals to the high-side power switches. This, in turn, results
in invalid output behavior that can cause damage to the output
devices, ultimately destroying the device tied at the output. The
UVLO level has been set at 2.65 V (nominal).
ON-BOARD LOW DROPOUT REGULATOR
The ADP1870 uses an on-board LDO to bias the internal digital
and analog circuitry. With proper bypass capacitors connected
to the VREG pin (output of internal LDO), this pin also provides
power for the internal MOSFET drivers. It is recommended to
float VREG if VIN is utilized for greater than 5.5 V operation.
The minimum voltage where bias is guaranteed to operate is
2.75 V at VREG.
For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended that
Rev. 0 | Page 19 of 44
ADP1870/ADP1871
VIN and VREG be tied together if the VIN pin is subjected to a
2.75 V rail.
SW
CS
AMP
PGND
Table 5. Power Input and LDO Output Configurations
Comments
Must use the LDO
LDO drop voltage is not
realized (that is, if VIN =
2.75 V, then VREG = 2.75
V)
LDO drop is realized
LDO drop is realized,
minimum VIN recommendation is 2.95 V
Float
Float
THERMAL SHUTDOWN
The thermal shutdown is a self-protection feature to prevent the
IC from damage due to a very high operating junction temperature.
If the junction temperature of the device exceeds 155°C, the part
enters the thermal shutdown state. In this state, the device shuts off
both the upper- and lower-side MOSFETs and disables the entire
controller immediately, thus reducing the power consumption of
the IC. The part resumes operation after the junction temperature
of the part cools to less than 140°C.
PROGRAMMING RESISTOR (RES) DETECT CIRCUIT
Upon startup, one of the first blocks to become active is the RES
detect circuit. This block powers up before soft start begins. It
forces a 0.4 V reference value at the DRVL output (see Figure 68)
and is programmed to identify four possible resistor values: 47 kΩ,
22 kΩ, open, and 100 kΩ.
The RES detect circuit digitizes the value of the resistor at the
DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current-sense amplifier (see Figure 69). Each configuration corresponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V,
24 V/V, respectively (see Table 6 and Table 7). This variable is used
for the valley current-limit setting, which sets up the appropriate
current-sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting and Compensation Network sections).
ADP1870/
ADP1871
CS GAIN SET
ADC
0.4V
DRVL
08730-067
<5.5 V
Ranges above
and below 5.5
V
VREG
Float
Connect to VIN
RES
Figure 69. RES Detect Circuit for Current-Sense Gain Programming
Table 6. Current-Sense Gain Programming
Resistor
47 kΩ
22 kΩ
Open
100 kΩ
ACS
3 V/V
6 V/V
12 V/V
24 V/V
VALLEY CURRENT-LIMIT SETTING
The architecture of the ADP1870/ADP1871 is based on valley
current-mode control. The current limit is determined by three
components: the RON of the lower-side MOSFET, the error amplifier output voltage swing (COMP), and the current-sense gain.
The COMP range is internally fixed at 1.4 V. The current-sense
gain is programmable via an external resistor at the DRVL pin (see
the Programming Resistor (RES) Detect Circuit section). The
RON of the lower-side MOSFET can vary over temperature and
usually has a positive TC (meaning that it increases with temperature); therefore, it is recommended to program the current-sense
gain resistor based on the rated RON of the MOSFET at 125°C.
Because the ADP1870/ADP1871 are based on valley current
control, the relationship between ICLIM and ILOAD is as follows:
K
I CLIM = I LOAD × ⎛⎜1 − I ⎞⎟
2 ⎠
⎝
where:
KI is the ratio between the inductor ripple current and the
desired average load current (see Figure 70).
ICLIM is the desired valley current limit.
ILOAD is the current load.
Establishing KI helps to determine the inductor value (see the
Inductor Selection section), but in most cases KI = 0.33.
Q1
DRVH
SW
Q2
DRVL
CS GAIN
PROGRAMMING
RIPPLE CURRENT =
08730-066
RRES
ILOAD
3
LOAD CURRENT
Figure 68. Programming Resistor Location
VALLEY CURRENT LIMIT
08730-068
VIN
>5.5 V
<5.5 V
Figure 70. Valley Current Limit to Average Current Relation
Rev. 0 | Page 20 of 44
ADP1870/ADP1871
I CLIM =
1.4 V
ACS × RON
where:
RON is the channel impedance of the lower-side MOSFET.
ACS is the current-sense gain multiplier (see Table 6 and Table 7).
Although the ADP1870/ADP1871 have only four discrete currentsense gain settings for a given RON variable, Table 7 and Figure 71
outline several available options for the valley current setpoint
based on various RON values.
The valley current limit is programmed as outlined in Table 7
and Figure 71. The inductor chosen must be rated to handle the
peak current, which is equal to the valley current from Table 7
plus the peak-to-peak inductor ripple current (see the Inductor
Selection section). In addition, the peak current value must be
used to compute the worst-case power dissipation in the
MOSFETs (see Figure 72).
49A
MAXIMUM DC LOAD
CURRENT
39.5A
INDUCTOR
CURRENT
Table 7. Valley Current Limit Program1
RON
(mΩ)
1.5
2
2.5
3
3.5
4.5
5
5.5
10
15
18
39.0
33.4
26.0
23.4
21.25
11.7
7.75
6.5
23.3
15.5
13.0
31.0
26.0
100 kΩ
ACS = 24 V/V
38.9
29.2
23.3
19.5
16.7
13
11.7
10.6
5.83
7.5
3.25
Refer to Figure 71 for more information and a graphical representation.
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
RES = 47kΩ
ACS = 3V/V
RES = NO RES
ACS = 12V/V
RES = 22kΩ
ACS = 6V/V
RES = 100kΩ
ACS = 24V/V
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
RON (mΩ)
COMP
OUTPUT
ΔI = 45% 32.25A
OF 32.25A
2.4V
VALLEY CURRENT-LIMIT
THRESHOLD (SET FOR 25A)
COMP
OUTPUT
SWING
0A
1V
Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current
HICCUP MODE DURING SHORT CIRCUIT
A current-limit violation occurs when the current across the
source and drain of the lower-side MOSFET exceeds the
current-limit setpoint. When 32 current-limit violations are
detected, the controller enters idle mode and turns off the
MOSFETs for 6 ms, allowing the converter to cool down. Then,
the controller reestablishes soft start and begins to cause the
output to ramp up again (see Figure 73). While the output
ramps up, COMP is monitored to determine if the violation is
still present. If it is still present, the idle event occurs again,
followed by the full-chip power-down sequence. This cycle
continues until the violation no longer exists. If the violation
disappears, the converter is allowed to switch normally,
maintaining regulation.
Figure 71. Valley Current-Limit Value vs. RON of the Lower-Side MOSFET
for Each Programming Resistor (RES)
REPEATED CURRENT-LIMIT
VIOLATION DETECTED
HS
A PREDETERMINED NUMBER SOFT START IS
OF PULSES IS COUNTED TO REINITIALIZED TO
ALLOW THE CONVERTER MONITOR IF THE
TO COOL DOWN
VIOLATION
STILL EXISTS
08730-071
CLIM
37A
30A
08730-069
VALLEY CURRENT LIMIT (A)
1
Valley Current Level
22 kΩ
Open
ACS = 6 V/V
ACS = 12 V/V
47 kΩ
ACS = 3 V/V
ΔI = 33%
OF 30A
ΔI = 65%
OF 37A
35A
08730-070
When the desired valley current limit (ICLIM) has been determined,
the current-sense gain can be calculated as follows:
ZERO
CURRENT
Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation
Rev. 0 | Page 21 of 44
ADP1870/ADP1871
SYNCHRONOUS RECTIFIER
The ADP1870/ADP1871 employ an internal lower-side MOSFET
driver to drive the external upper- and lower-side MOSFETs.
The synchronous rectifier not only improves overall conduction
efficiency, but also ensures proper charging to the bootstrap
capacitor located at the upper-side driver input. This is beneficial
during startup to provide sufficient drive signal to the external
upper-side MOSFET and to attain fast turn-on response, which is
essential for minimizing switching losses. The integrated upperand lower-side MOSFET drivers operate in complementary
fashion with built-in anticross conduction circuitry to prevent
unwanted shoot-through current that may potentially damage the
MOSFETs or reduce efficiency as a result of excessive power loss.
As soon as the forward current through the lower-side
MOSFET decreases to a level where
10 mV = IQ2 × RON(Q2)
the zero-cross comparator (or IREV comparator) emits a signal to
turn off the lower-side MOSFET. From this point, the slope of the
inductor current ramping down becomes steeper (see Figure 76)
as the body diode of the lower-side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.
ANOTHER tON EDGE IS
TRIGGERED WHEN VOUT
FALLS BELOW REGULATION
SW
tON
POWER SAVING MODE (PSM) VERSION (ADP1871)
HS AND LS
IN IDLE MODE
LS
ZERO-CROSS COMPARATOR
DETECTS 10mV OFFSET AND
TURNS OFF LS
ILOAD
0A
10mV = RON × ILOAD
HS
08730-074
The power saving mode version of the ADP1870 is the ADP1871.
The ADP1871 operates in the discontinuous conduction mode
(DCM) and pulse skips at light load to mid load currents. It
outputs pulses as necessary to maintain output regulation. Unlike
the continuous conduction mode (CCM), DCM operation
prevents negative current, thus allowing improved system
efficiency at light loads. Current in the reverse direction through
this pathway, however, results in power dissipation and therefore
a decrease in efficiency.
Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current
tON
The system remains in idle mode until the output voltage drops
below regulation. A PWM pulse is then produced, turning on the
upper-side MOSFET to maintain system regulation. The
ADP1871 does not have an internal clock, so it switches purely
as a hysteretic controller as described in this section.
HS AND LS ARE OFF
OR IN IDLE MODE
LS
tOFF
TIMER OPERATION
AS THE INDUCTOR
CURRENT APPROACHES
ZERO CURRENT, THE STATE
MACHINE TURNS OFF THE
LOWER-SIDE MOSFET.
08730-072
ILOAD
0A
Figure 74. Discontinuous Mode of Operation (DCM)
To minimize the chance of negative inductor current buildup,
an on-board zero-cross comparator turns off all upper- and
lower-side switching activities when the inductor current
approaches the zero current line, causing the system to enter
idle mode, where the upper- and lower-side MOSFETs are
turned off. To ensure idle mode entry, a 10 mV offset, connected
in series at the SW node, is implemented (see Figure 75).
ZERO-CROSS
COMPARATOR
08730-073
10mV
Q2
t ON = K ×
VOUT
VIN
where:
K is a constant that is trimmed using an RC timer product for
the 300 kHz, 600 kHz, and 1.0 MHz frequency options.
SW
IQ2
LS
The ADP1870/ADP1871 employ a constant on-time architecture,
which provides a variety of benefits, including improved load
and line transient response when compared with a constant
(fixed) frequency current-mode control loop of comparable
loop design. The constant on-time timer, or tON timer, senses
the high input voltage (VIN) and the output voltage (VOUT) using
SW waveform information to produce an adjustable one-shot
PWM pulse that varies the on-time of the upper-side MOSFET in
response to dynamic changes in input voltage, output voltage, and
load current conditions to maintain regulation. It then generates
an on-time (tON) pulse that is inversely proportional to VIN.
Figure 75. Zero-Cross Comparator with 10 mV of Offset
Rev. 0 | Page 22 of 44
ADP1870/ADP1871
VREG
tON
VIN
To illustrate this feature more clearly, this section describes
one such load transient event—a positive load step—in detail.
During load transient events, the high-side driver output pulse
width stays relatively consistent from cycle to cycle; however,
the off-time (DRVL on-time) dynamically adjusts according to
the instantaneous changes in the external conditions mentioned.
C
I
R (TRIMMED)
08730-075
SW
INFORMATION
Figure 77. Constant On-Time Time
The constant on-time (tON) is not strictly “constant” because it
varies with VIN and VOUT. However, this variation occurs in such
a way as to keep the switching frequency virtually independent
of VIN and VOUT.
The tON timer uses a feedforward technique, applied to the constant
on-time control loop, making it a pseudo-fixed frequency to a first
order. Second-order effects, such as dc losses in the external power
MOSFETs (see the Efficiency Consideration section), cause some
variation in frequency vs. load current and line voltage. These
effects are shown in Figure 23 to Figure 34. The variations in
frequency are much reduced compared with the variations
generated when the feedforward technique is not utilized.
The feedforward technique establishes the following relationship:
f SW =
1
K
where fSW is the controller switching frequency (300 kHz,
600 kHz, and 1.0 MHz).
The tON timer senses VIN and VOUT to minimize frequency
variation as previously explained. This provides a pseudo-fixed
frequency as explained in the Pseudo-Fixed Frequency section.
To allow headroom for VIN and VOUT sensing, adhere to the
following equations:
VREG ≥ VIN/8 + 1.5
VREG ≥ VOUT/4
For typical applications where VREG is 5 V, these equations are
not relevant; however, for lower VREG inputs, care may be
required.
When a positive load step occurs, the error amplifier (out of phase
of the output, VOUT) produces new voltage information at its output
(COMP). In addition, the current-sense amplifier senses new
inductor current information during this positive load transient
event. The error amplifier’s output voltage reaction is compared
with the new inductor current information that sets the start of
the next switching cycle. Because current information is produced
from valley current sensing, it is sensed at the down ramp of the
inductor current, whereas the voltage loop information is sensed
through the counter action upswing of the error amplifier’s
output (COMP).
The result is a convergence of these two signals (see Figure 78),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes VOUT to transient down, which causes COMP to
transient up and therefore shortens the off-time. This resulting
increase in frequency during a positive load transient helps to
quickly bring VOUT back up in value and within the regulation
window.
Similarly, a negative load step causes the off-time to lengthen in
response to VOUT rising. This effectively increases the inductor
demagnetizing phase, helping to bring VOUT within regulation.
In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.
Because the ADP1870/ADP1871 has the ability to respond rapidly
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed-frequency
equivalent. Therefore, using a pseudo-fixed frequency results in
significantly better load transient performance than using a
fixed frequency.
PSEUDO-FIXED FREQUENCY
Rev. 0 | Page 23 of 44
LOAD CURRENT
DEMAND
CS AMP
OUTPUT
ERROR AMP
OUTPUT
PWM OUTPUT
VALLEY
TRIP POINTS
fSW
>fSW
08730-076
The ADP1870/ADP1871 employ a constant on-time control
scheme. During steady state operation, the switching frequency
stays relatively constant, or pseudo-fixed. This is due to the oneshot tON timer that produces a high-side PWM pulse with a
“fixed” duration, given that external conditions such as input
voltage, output voltage, and load current are also at steady state.
During load transients, the frequency momentarily changes for
the duration of the transient event so that the output comes
back within regulation more quickly than if the frequency were
fixed or if it were to remain unchanged. After the transient
event is complete, the frequency returns to a pseudo-fixed
frequency value to a first order.
Figure 78. Load Transient Response Operation
ADP1870/ADP1871
APPLICATIONS INFORMATION
Table 8. Recommended Inductors
FEEDBACK RESISTOR DIVIDER
INDUCTOR SELECTION
L
(μH)
0.12
0.22
0.47
0.72
0.9
1.2
1.0
1.4
2.0
0.8
The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The required resistor divider network can be determined for a
given VOUT value because the internal band gap reference (VREF)
is fixed at 0.6 V. Selecting values for RT and RB determines the
minimum output load current of the converter. Therefore, for a
given value of RB, the RT value can be determined through the
following expression:
RT = R B ×
(VOUT − 0.6 V)
0.6 V
ΔI L = K I × I LOAD
I
≈ LOAD
3
The equation for the inductor value is given by
(V IN − VOUT ) VOUT
×
ΔI L × f SW
V IN
Dimensions
(mm)
10.2 × 7
10.2 × 7
13.2 × 12.8
10.5 × 10.2
13 × 12.8
10.5 × 10.2
10.5 × 10.2
14 × 12.8
13.2 × 12.8
12.5 × 12.5
Manufacturer
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
AIC Technology
Model
Number
744303012
744303022
744355147
744325072
744355090
744325120
7443552100
744318180
7443551200
CEP125U-R80
ΔVRR = (0.01) × VOUT
where:
VIN is the high voltage input.
VOUT is the desired output voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz, and
1.0 MHz).
When selecting the inductor, choose an inductor saturation
rating that is above the peak current level, and then calculate
the inductor current ripple (see the Valley Current-Limit
Setting section and Figure 79).
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
ΔI = 50%
ΔI = 40%
OUTPUT CAPACITOR SELECTION
The primary objective of the output capacitor is to facilitate the
reduction of the output voltage ripple; however, the output
capacitor also assists in the output voltage recovery during load
transient events. For a given load current step, the output
voltage ripple generated during this step event is inversely
proportional to the value chosen for the output capacitor. The
speed at which the output voltage settles during this recovery
period depends on where the crossover frequency (loop
bandwidth) is set. This crossover frequency is determined by
the output capacitor, the equivalent series resistance (ESR) of
the capacitor, and the compensation network.
To calculate the small-signal voltage ripple (output ripple
voltage) at the steady state operating point, use the following
equation:
ΔI = 33%
⎞
⎛
1
⎟
C OUT = ΔI L × ⎜⎜
⎟
[
]
8
f
V
(
I
ESR
)
×
×
Δ
−
Δ
×
RIPPLE
L
SW
⎠
⎝
where ESR is the equivalent series resistance of the output
capacitors.
6
8
10
12
14
16
18
20
22
VALLEY CURRENT LIMIT (A)
24
26
28
30
08730-077
PEAK INDUCTOR CURRENT (A)
ISAT
(A)
55
30
50
35
28
25
20
24
22
16.5
The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the
output capacitor value needed to achieve this tolerance can be
determined using the following equation. (Note that an
accuracy of 1.0% is possible only during steady state conditions,
not during load transients.)
where KI is typically 0.33.
L=
DCR
(mΩ)
0.33
0.33
0.67
1.3
1.6
1.8
3.3
3.2
2.6
2.5
To calculate the output load step, use the following equation:
COUT = 2 ×
Figure 79. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and
50% of Inductor Ripple Current
f SW
ΔI LOAD
× (ΔVDROOP − (ΔI LOAD × ESR))
where ΔVDROOP is the amount that VOUT is allowed to deviate for
a given positive load current step (ΔILOAD).
Rev. 0 | Page 24 of 44
ADP1870/ADP1871
Ceramic capacitors are known to have low ESR. However, the
trade-off of using X5R technology is that up to 80% of its capacitance might be lost due to derating as the voltage applied across
the capacitor is increased (see Figure 80). Although X7R series
capacitors can also be used, the available selection is limited to
only up to 22 μF.
Error Amplifier Output Impedance (ZCOMP)
Assuming that CC2 is significantly smaller than CCOMP, CC2 can
be omitted from the output impedance equation of the error
amplifier. The transfer function simplifies to
Z COMP =
R COMP ( f CROSS + f ZERO )
f CROSS
20
and
10
X7R (50V)
fCROSS =
–10
–20
1
× f SW
12
where fZERO, the zero frequency, is set to be 1/4th of the crossover
frequency for the ADP1870.
–30
–40
Error Amplifier Gain (GM)
–50
X5R (25V)
–60
The error amplifier gain (transconductance) is
–70
GM = 500 μA/V
X5R (16V)
–80
10µF TDK 25V, X7R, 1210 C3225X7R1E106M
22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L
47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L
–90
–100
0
5
10
15
20
25
Current-Sense Loop Gain (GCS)
30
DC VOLTAGE (VDC)
08730-078
CAPACITANCE CHARGE (%)
0
The current-sense loop gain is
G CS =
Figure 80. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors
Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. Because the ESR of electrolytic
capacitors is much higher than that of ceramic capacitors, when
using electrolytic capacitors, several MLCCs should be mounted
in parallel to reduce the overall series resistance.
1
(A/V)
ACS × RON
where:
ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
RON is the channel impedance of the lower-side MOSFET.
COMPENSATION NETWORK
Crossover Frequency
Due to their current-mode architecture, the ADP1870/ADP1871
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the converter’s overall loop
gain (H) at the unity gain frequency (fSW/10) when H = 1 V/V:
The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). For current-mode
converters, such as the ADP1870, it is recommended that the
user set the crossover frequency between 1/10th and 1/15th of the
switching frequency.
H = 1 V/V = G M × G CS ×
VOUT
× Z COMP × Z FILT
VREF
fCROSS =
Examining each variable at high frequency enables the unitygain transfer function to be simplified to provide expressions
for the RCOMP and CCOMP component values.
The relationship between CCOMP and fZERO (zero frequency) is as
follows:
f ZERO =
Output Filter Impedance (ZFILT)
Examining the filter’s transfer function at high frequencies
simplifies to
Z FILTER =
1
f SW
12
1
2π × R COMP × C COMP
)
The zero frequency is set to 1/4th of the crossover frequency.
Combining all of the above parameters results in
1
RCOMP =
sC OUT
at the crossover frequency (s = 2πfCROSS).
C COMP =
Rev. 0 | Page 25 of 44
2πf CROSS C OUT VOUT
f CROSS
×
×
f CROSS + f ZERO
G M GCS
VREF
1
2 × π × RCOMP × f ZERO
ADP1870/ADP1871
EFFICIENCY CONSIDERATIONS
800
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
720
•
•
•
VGS (TH): the MOSFET support voltage applied between the
gate and the source
RDS (ON): the MOSFET on resistance during channel
conduction
QG: the total gate charge
CN1: the input capacitance of the upper-side switch
CN2: the input capacitance of the lower-side switch
The following are the losses experienced through the external
component during normal switching operation:
•
•
•
•
•
Channel conduction loss (both of the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower-side MOSFET)
Inductor loss (copper and core loss)
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper-side MOSFET is directly proportional to the duty cycle (D) for each switching period, and
the power loss through the lower-side MOSFET is directly
proportional to 1 − D for each switching period. The selection
of MOSFETs is governed by the amount of maximum dc load
current that the converter is expected to deliver. In particular,
the selection of the lower-side MOSFET is dictated by the
maximum load current because a typical high current application
employs duty cycles of less than 50%. Therefore, the lower-side
MOSFET is in the on state for most of the switching period.
[
]
2
PN1,N2(CL) = D × R N1(ON) + (1 − D ) × R N2(ON) × I LOAD
400
320
+125°C
+25°C
–40°C
160
80
300
400
500
600
700
800
900
1000
SWITCHING FREQUENCY (kHz)
Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency
Switching Loss
The SW node transitions due to the switching activities of the
upper- and lower-side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times. This
loss can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:
tSW-TRANS = RGATE × CTOTAL
where:
CTOTAL is the CGD + CGS of the external MOSFET.
RGATE is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
PSW ( LOSS) =
t SW -TRANS
t SW
× I LOAD × V IN × 2
or
PSW ( LOSS) = f SW × R GATE × C TOTAL × I LOAD × V IN × 2
Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver
during operation and the QGATE parameter of the external MOSFETs.
]
PDR ( LOSS ) = VDR × ( f SW CupperFETVDR + I BIAS ) +
[VREG × ( f SW ClowerFETVREG + I BIAS )]
480
240
MOSFET Driver Loss
[
560
08730-079
•
640
RECTIFIER DROP (mV)
•
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
where:
CupperFET is the input gate capacitance of the upper-side MOSFET.
ClowerFET is the input gate capacitance of the lower-side MOSFET.
IBIAS is the dc current flowing into the upper- and lower-side drivers.
VDR is the driver bias voltage (that is, the low input voltage
(VREG) minus the rectifier drop (see Figure 81)).
VREG is the bias voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz, and
1.0 MHz)
Rev. 0 | Page 26 of 44
ADP1870/ADP1871
Diode Conduction Loss
The ADP1870/ADP1871 employ anticross conduction circuitry
that prevents the upper- and lower-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFETs change states and
continuing well into idle mode. The amount of loss through the
body diode of the lower-side MOSFET during the antioverlap
state is given by the following expression:
PBODY ( LOSS) =
t BODY ( LOSS)
t SW
× I LOAD × VF × 2
where:
tBODY(LOSS) is the body conduction time (refer to Figure 82 for
dead time periods).
tSW is the period per switching cycle.
VF is the forward drop of the body diode during conduction.
(Refer to the selected external MOSFET data sheet for more
information about the VF parameter.)
+125°C
+25°C
–40°C
1MHz
300kHz
72
64
2
+ Core Loss
PDCR( LOSS) = DCR × I LOAD
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their
physical geometries, is their large equivalent series resistance
(ESR) and large equivalent series inductance (ESL). Aluminum
electrolytic capacitors have such high ESR that they cause
undesired input voltage ripple magnitudes and are generally not
effective at high switching frequencies.
If bulk capacitors are to be used, it is recommended that mulilayered ceramic capacitors (MLCC) be used in parallel due to
their low ESR values. This dramatically reduces the input voltage
ripple amplitude as long as the MLCCs are mounted directly
across the drain of the upper-side MOSFET and the source
terminal of the lower-side MOSFET (see the Layout Considerations
section). Improper placement and mounting of these MLCCs
may cancel their effectiveness due to stray inductance and an
increase in trace impedance.
56
I CIN ,rms = I LOAD,max ×
48
40
32
24
16
8
2.7
3.4
4.1
VREG (V)
4.8
5.5
08730-080
BODY DIODE CONDUCTION TIME (ns)
80
application to achieve minimal loss and negligible electromagnetic
interference (EMI).
Figure 82. Body Diode Conduction Time vs. Low Voltage Input (VREG)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered
iron inductors have higher core losses. It is recommended that
shielded ferrite core material type inductors be used with the
ADP1870/ADP1871 for a high current, dc-to-dc switching
VOUT × (V IN − VOUT )
VOUT
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
VRIPPLE,max = VRIPP + (ILOAD,max × ESR)
where:
VRIPP is usually 1% of the minimum voltage input.
ILOAD,max is the maximum load current.
ESR is the equivalent series resistance rating of the input capacitor.
Inserting VRIPPLE,max into the charge balance equation to calculate
the minimum input capacitor requirement gives
C IN,min =
I LOAD,max
VRIPPLE,max
×
D(1 − D)
f SW
or
C IN,min =
I LOAD,max
4 f SW VRIPPLE,max
where D = 50%.
Rev. 0 | Page 27 of 44
ADP1870/ADP1871
THERMAL CONSIDERATIONS
The ADP1870/ADP1871 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current delivery and be subjected to
high ambient temperature surroundings, the selection of external
upper- and lower-side MOSFETs must be associated with careful
thermal consideration to not exceed the maximum allowable
junction temperature of 125°C. To avoid permanent or irreparable
damage if the junction temperature reaches or exceeds 155°C, the
part enters thermal shutdown, turning off both external MOSFETs,
and does not reenable until the junction temperature cools to
140°C (see the On-Board Low Dropout Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1870/ADP1871 employ an onboard LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
Table 9 lists the thermal impedance for the ADP1870/ADP1871,
which are available in a 10-lead MSOP.
Table 9. Thermal Impedance for 10-lead MSOP
Parameter
10-Lead MSOP θJA
2-Layer Board
4-Layer Board
Thermal Impedance
600kHz
300kHz
1MHz
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
VOUT = 0.8V
VOUT = 1.8V
VOUT = HIGH SETPOINT
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
TR = θJA × PDR(LOSS)
110
The bulk of the power dissipated is due to the gate capacitance
of the external MOSFETs and current running through the onboard LDO. The power loss equations for the MOSFET drivers
and internal low dropout regulator (see the MOSFET Driver
Loss section in the Efficiency Consideration section) are:
(3)
where:
CupperFET is the input gate capacitance of the upper-side MOSFET.
ClowerFET is the input gate capacitance of the lower-side MOSFET.
IBIAS is the dc current (2 mA) flowing into the upper- and lowerside drivers.
VDR is the driver bias voltage (the low input voltage (VREG)
minus the rectifier drop (see Figure 81)).
VREG is the LDO output/bias voltage.
(4)
where:
PDISS(LDO) is the power dissipated through the pass device in the
LDO block across VIN and VREG.
Ctotal is the CGD + CGS of the external MOSFET.
VREG is the LDO output voltage and bias voltage.
VIN is the high voltage input.
IBIAS is the dc input bias current.
PDR(LOSS) is the MOSFET driver loss.
100
90
80
70
60
50
40
30
20
7.0
8.5
10.0
11.5
13.0
VIN (V)
14.5
16.0
17.5
19.0
08730-182
10
0
5.5
(2)
where:
θJA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
PDR(LOSS) is the overall power dissipated by the IC.
PDISS ( LDO ) = PDR ( LOSS ) + (VIN − VREG ) × ( f SW × Ctotal × VREG + I BIAS )
120
(1)
where:
TA is the ambient temperature.
TJ is the maximum junction temperature.
TR is the rise in package temperature due to the power
dissipated from within.
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +
[VREG × (fSWClowerFET VREG + IBIAS)]
150
130
TJ = TR × TA
213.1°C/W
171.7°C/W
Figure 83 specifies the maximum allowable ambient temperature
that can surround the ADP1870/ADP1871 IC for a specified
high input voltage (VIN). Figure 83 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 10-lead MSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
140
The maximum junction temperature allowed for the ADP1870/
ADP1871 ICs is 125°C. This means that the sum of the ambient
temperature (TA) and the rise in package temperature (TR),
which is caused by the thermal impedance of the package and
the internal power dissipation, should not exceed 125°C, as
dictated by the following expression:
Figure 83. Ambient Temperature vs. VIN for 10-Lead MSOP (171°C/W),
4-Layer EVB, CIN = 4.3 nF (Upper-/Lower-Side MOSFET)
Rev. 0 | Page 28 of 44
ADP1870/ADP1871
For example, if the external MOSFET characteristics are θJA
(10-lead MSOP) = 171.2°C/W, fSW = 300 kHz, IBIAS = 2 mA,
CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V,
then the power loss is
[
(
P DR ( LOSS ) = V DR × f SW C upperFET V DR + I BIAS
+ [V REG × ( f SW C lowerFET V REG + I BIAS
= ( 4 . 62 × (300 × 10 × 3 . 3 × 10
3
−9
)]
)]
Inductor
Determine inductor ripple current amplitude as follows:
ΔI L ≈
I LOAD
=5A
3
so calculating for the inductor value
× 4 .62 + 0 . 002 ))
L=
+ (5 . 0 × (300 × 10 3 × 3 . 3 × 10 − 9 × 5 . 0 + 0 . 002 ))
= 57.12 mW
=
PDISS( LDO ) = (V IN − VREG ) × ( f SW × C total × VREG + I BIAS )
(V IN,MAX − VOUT )
ΔI L × f SW
(13.2 V − 1.8 V)
5 V × 300 × 10
= 1.03 μH
= (13 V − 5 V) × (300 × 10 3 × 3.3 × 10 −9 × 5 + 0.002)
= 55.6 mW
3
×
×
VOUT
V IN,MAX
1. 8 V
13.2 V
The inductor peak current is approximately
PDISS(TOTAL ) = PDISS( LDO ) + PDR( LOSS )
15 A + (5 A × 0.5) = 17.5 A
= 77.13 mW + 55.6 mW
= 132.73 mW
Therefore, an appropriate inductor selection is 1.0 μH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) from Table 8
with peak current handling of 20 A.
The rise in package temperature (for 10-lead MSOP) is
TR = θ JA × PDR( LOSS )
PDCR( LOSS) = DCR × I L2
= 171.2°C × 132.05 mW
= 0.003 × (15 A)2 = 675 mW
= 22.7°C
Current Limit Programming
Assuming a maximum ambient temperature environment of 85°C,
The valley current is approximately
TJ = TR × TA = 22.7°C + 85°C = 107.72°C
15 A − (5 A × 0.5) = 12.5 A
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1870/ADP1871 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing),
VIN = 12 V (typical), and fSW = 300 kHz.
Assume that a load step of 15 A occurs at the output and no more
than 5% is allowed for the output to deviate from the steady state
operating point. In this case, the ADP1870’s advantage is that
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
VRIPP = 120 mV
VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR)
= 120 mV − (15 A × 0.001) = 45 mV
I LOAD, MAX
4 f SW V MAX , RIPPLE
Choose a programmable resistor of RRES = 100 kΩ for a currentsense gain of 24 V/V.
Output Capacitor
Input Capacitor
C IN,min =
Assuming a lower-side MOSFET RON of 4.5 mΩ and 13 A as
the valley current limit from Table 7 and Figure 71 indicates, a
programming resistor (RES) of 100 kΩ corresponds to an ACS
of 24 V/V.
=
ΔVDROOP = 0.05 × 1.8 V = 90 mV
15 A
4 × 300 × 10 × 105 mV
3
Assuming that the overall ESR of the output capacitor ranges
from 5 mΩ to 10 mΩ,
= 120 μF
Choose five 22 μF ceramic capacitors. The overall ESR of five
22 μF ceramic capacitors is less than 1 mΩ.
C OUT = 2 ×
IRMS = ILOAD/2 = 7.5 A
= 2×
ΔI LOAD
f SW × (ΔVDROOP )
15 A
300 × 10 3 × (90 mV)
= 1.11 mF
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
Therefore, an appropriate inductor selection is five 270 μF
polymer capacitors with a combined ESR of 3.5 mΩ.
Rev. 0 | Page 29 of 44
ADP1870/ADP1871
Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate:
C OUT =
=
C COMP =
(L × I LOAD )
− ΔVOVSHT ) 2 − (VOUT )2 )
2πRCOMP f ZERO
1
2 × 3.14 × 100 × 103 × 6.25 × 103
= 250 pF
2
((VOUT
1
=
1× 10 −6 × (15 A) 2
Loss Calculations
(1.8 − 45 mV) 2 − (1.8) 2
Duty cycle = 1.8/12 V = 0.15
= 1.4 mF
Choose five 270 μF polymer capacitors.
RON (N2) = 5.4 mΩ
The rms current through the output capacitor is
tBODY(LOSS) = 20 ns (body conduction time)
1 1 (V IN , MAX − VOUT ) VOUT
I RMS = ×
×
L × f SW
V IN , MAX
2
3
VF = 0.84 V (MOSFET forward voltage)
1 1 (13.2 V − 1.8 V) 1.8 V
= ×
×
= 1.49 A
2
3 1 μF × 300 × 10 3 13.2 V
QN1,N2 = 17 nC (total MOSFET gate charge)
CIN = 3.3 nF (MOSFET gate input capacitance)
RGATE = 1.5 Ω (MOSFET gate input resistance)
[
= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2
= 1.215 W
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
Feedback Resistor Network Setup
PBODY ( LOSS ) =
It is recommended to use RB = 15 kΩ. Calculate RT as follows:
RT = 15 kΩ ×
(1.8 V − 0.6 V)
0.6 V
= 30 kΩ
Compensation Network
To calculate RCOMP, CCOMP, and CPAR, the transconductance
parameter and the current-sense gain variable are required. The
transconductance parameter (GM) is 500 μA/V, and the currentsense loop gain is
G CS =
]
2
PN1,N2(CL) = D × R N1(ON) + (1 − D ) × R N2(ON) × I LOAD
The power loss dissipated through the ESR of the output
capacitor is
t BODY ( LOSS )
× I LOAD × VF × 2
t SW
= 20 ns × 300 × 103 × 15 A × 0.84 × 2
= 151.2 mW
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
= 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2
= 534.6 mW
[
(
P DR ( LOSS ) = V DR × f SW C upperFET V DR + I BIAS
+ [V REG × ( f SW C lowerFET V REG + I BIAS
)]
)]
= ( 4 . 62 × (300 × 10 3 × 3 . 3 × 10 − 9 × 4 .62 + 0 . 002 ))
+ (5 . 0 × (300 × 10 3 × 3 . 3 × 10 − 9 × 5 . 0 + 0 . 002 ))
1
1
=
= 8.33 A/V
ACS RON 24 × 0.005
= 57.12 mW
PDISS( LDO ) = (V IN − VREG ) × ( f SW × C total × VREG + I BIAS )
where ACS and RON are taken from setting up the current limit
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
= (13 V − 5 V) × (300 × 10 3 × 3.3 × 10 −9 × 5 + 0.002)
The crossover frequency is 1/12th of the switching frequency:
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
300 kHz/12 = 25 kHz
2
= 0.003 × (15 A)2 = 675 mW
PDCR( LOSS) = DCR × I LOAD
The zero frequency is 1/4th of the crossover frequency:
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
25 kHz/4 = 6.25 kHz
RCOMP =
= 55.6 mW
2πf CROSS C OUT VOUT
f CROSS
×
×
f CROSS + f ZERO
G M G CS
VREF
25 × 10 3
2 × 3.141 × 25 × 10 3 × 1.11 × 10 −3 1.8
×
×
3
3
25 × 10 + 6.25 × 10
500 × 10 −6 × 8.3
0.6
= 100 kΩ
=
Rev. 0 | Page 30 of 44
PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO)
+ PCOUT + PCIN
= 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6
+ 3.15 mW + 675 mW + 56.25 mW
= 2.655 W
ADP1870/ADP1871
EXTERNAL COMPONENT RECOMMENDATIONS
The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 15 kΩ, RON = 5.4 mΩ
(BSC042N03MS G), VREG = 5 V (float), and a maximum load current of 14 A.
The ADP1871 models listed in Table 10 are the PSM versions of the device.
Table 10. External Component Values
Marking Code
SAP Model
ADP1870ARMZ-0.3-R7/
ADP1871ARMZ-0.3-R7
ADP1870ARMZ-0.6-R7/
ADP1871ARMZ-0.6-R7
ADP1870ARMZ-1.0-R7/
ADP1871ARMZ-1.0-R7
ADP1870
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDY
LDY
LDY
LDY
LDY
LDY
LDY
LDY
LDY
LDY
LDY
LDY
LDY
ADP1871
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDG
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDN
LDN
LDN
LDN
LDN
LDN
LDN
LDN
LDN
LDN
LDN
LDN
LDN
VOUT
(V)
0.8
1.2
1.8
2.5
3.3
5
7
1.2
1.8
2.5
3.3
5
7
0.8
1.2
1.8
2.5
1.2
1.8
2.5
3.3
5
1.2
1.8
2.5
3.3
5
7
0.8
1.2
1.8
2.5
1.2
1.8
2.5
3.3
5
1.2
1.8
2.5
3.3
VIN
(V)
13
13
13
13
13
13
13
16.5
16.5
16.5
16.5
16.5
16.5
5.5
5.5
5.5
5.5
13
13
13
13
13
16.5
16.5
16.5
16.5
16.5
16.5
5.5
5.5
5.5
5.5
13
13
13
13
13
16.5
16.5
16.5
16.5
CIN
(μF)
5 × 22 2
5 × 222
4 × 222
4 × 222
5 × 222
4 × 222
4 × 222
4 × 222
3 × 222
3 × 222
3 × 222
3 × 222
3 × 222
5 × 222
5 × 222
5 × 222
5 × 222
3 × 222
5 × 10 9
5 × 109
5 × 109
5 × 109
3 × 109
4 × 109
4 × 109
4 × 109
4 × 109
4 × 109
5 × 222
5 × 222
3 × 222
3 × 222
3 × 109
4 × 109
4 × 109
5 × 109
4 × 109
3 × 109
3 × 109
4 × 109
4 × 109
Rev. 0 | Page 31 of 44
COUT
(μF)
5 × 560 3
4 × 5603
4 × 270 4
3 × 2704
2 × 330 5
3305
222 + ( 4 × 47 6 )
4 × 5603
4 × 2704
4 × 2704
2 × 3305
2 × 150 7
222 + 4 × 476
4 × 5603
4 × 2704
3 × 2704
3 × 180 8
5 × 2704
3 × 3305
3 × 2704
2 × 2704
1507
4 × 2704
2 × 3305
3 × 2704
3305
4 × 476
3 × 476
4 × 2704
2 × 3305
3 × 1808
2704
3 × 3305
3 × 2704
2704
2704
3 × 476
4 × 2704
3 × 2704
3 × 1808
2704
L1
(μH)
0.72
1.0
1.0
1.53
2.0
3.27
3.44
1.0
1.0
1.67
2.00
3.84
4.44
0.22
0.47
0.47
0.47
0.47
0.47
0.90
1.00
1.76
0.47
0.72
0.90
1.0
2.0
2.0
0.22
0.22
0.22
0.22
0.22
0.47
0.47
0.72
1.0
0.47
0.47
0.72
0.72
RC
(kΩ)
47
47
47
47
47
34
34
47
47
47
47
34
34
47
47
47
47
47
47
47
47
34
47
47
47
47
34
34
47
47
47
47
47
47
47
47
34
47
47
47
47
CCOMP
(pF)
740
740
571
571
571
800
800
740
592
592
592
829
829
339
326
271
271
407
307
307
307
430
362
326
326
296
415
380
223
223
163
163
233
210
210
210
268
326
261
233
217
CPAR
(pF)
74
74
57
57
57
80
80
74
59
59
59
83
83
34
33
27
27
41
31
31
31
43
36
33
33
30
41
38
22
22
16
16
23
21
21
21
27
33
26
23
22
RTOP
(kΩ)
5.0
15.0
30.0
47.5
67.5
110.0
160.0
15.0
30.0
47.5
67.5
110.0
160.0
5.0
15.0
30.0
47.5
15.0
30.0
47.5
67.5
110.0
15.0
30.0
47.5
67.5
110.0
160.0
5.0
15.0
30.0
47.5
15.0
30.0
47.5
67.5
110.0
15.0
30.0
47.5
67.5
ADP1870/ADP1871
Marking Code
SAP Model
ADP1870
LDY
LDY
ADP1871
LDN
LDN
VOUT
(V)
5
7
VIN
(V)
16.5
16.5
CIN
(μF)
3 × 109
3 × 109
COUT
(μF)
3 × 476
222 + 476
L1
(μH)
1.0
1.0
RC
(kΩ)
34
34
CCOMP
(pF)
268
228
CPAR
(pF)
27
23
1
See the Inductor Selection section and Table 11.
22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).
3
560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).
4
270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).
5
330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).
6
47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).
7
150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).
8
180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).
9
10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.
2
Table 11. Recommended Inductors
L (μH)
0.12
0.22
0.47
0.72
0.9
1.2
1.0
1.4
2.0
0.8
DCR (mΩ)
0.33
0.33
0.67
1.3
1.6
1.8
3.3
3.2
2.6
2.5
ISAT (A)
55
30
50
35
28
25
20
24
22
16.5
Dimension (mm)
10.2 × 7
10.2 × 7
13.2 × 12.8
10.5 × 10.2
13 × 12.8
10.5 × 10.2
10.5 × 10.2
14 × 12.8
13.2 × 10.8
12.5 × 12.5
Manufacturer
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
AIC Technology
Model Number
744303012
744303022
744355147
744325072
744355090
744325120
7443552100
744318180
7443551200
CEP125U-R80
Table 12. Recommended MOSFETs
VGS = 4.5 V
Upper-Side MOSFET
(Q1/Q2)
Lower-Side MOSFET
(Q3/Q4)
RON
(mΩ)
5.4
ID
(A)
47
VDS
(V)
30
CIN
(nF)
3.2
QTOTAL
(nC)
20
Package
PG-TDSON8
Manufacturer
Infineon
Model Number
BSC042N03MS G
10.2
6.0
9
5.4
53
19
14
47
30
30
30
30
1.6
10
35
25
20
PG-TDSON8
SO-8
SO-8
PG-TDSON8
Infineon
Vishay
International Rectifier
Infineon
BSC080N03MS G
Si4842DY
IRF7811
BSC042N03MS G
10.2
6.0
82
19
30
30
1.6
10
35
PG-TDSON8
SO-8
Infineon
Vishay
BSC080N03MS G
Si4842DY
2.4
3.2
Rev. 0 | Page 32 of 44
RTOP
(kΩ)
110.0
160.0
ADP1870/ADP1871
LAYOUT CONSIDERATIONS
Figure 84 shows the schematic of a typical ADP1870/ADP1871
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and VOUT traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
The performance of a dc-to-dc converter depends highly on
how the voltage and current paths are configured on the printed
circuit board (PCB). Optimizing the placement of sensitive
analog and power components is essential to minimize output
ripple, maintain tight regulation specifications, and reduce
PWM jitter and electromagnetic interference.
HIGH VOLTAGE INPUT
VIN = 12V
JP3
C28
10µF
CF
57pF
VOUT
ADP1870/
ADP1871
1
VIN
2
COMP/EN
3
FB
DRVH 8
4
GND
PGND 7
5
VREG
DRVL 6
R1 30kΩ
C2
0.1µF
R2
15kΩ
C1
1µF
BST 10
C12
100nF
C3
22µF
Q1
C4
22µF
C5
22µF
C6
22µF
1.0µH
Q3
C8
N/A
C9
N/A
Q2
SW 9
R4
0Ω
C7
22µF
Q4
R6
2Ω
C13
1.5nF
VOUT = 1.8V, 15A
C20
270µF
C24
N/A
R5
100kΩ
+
+
C21
270µF
C25
N/A
+
+
C22
270µF
C26
N/A
+
+
C23
270µF
C27
N/A
+
+ C14 TO C19
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1µH, 3.3mΩ, 20A 7443552100
Figure 84. ADP1870 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
Rev. 0 | Page 33 of 44
08730-081
CC
571pF
RC
47kΩ
ADP1870/ADP1871
SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM THE NOISY
POWER SECTION.
SEPARATE ANALOG GROUND
PLANE FOR THE ANALOG
COMPONENTS (THAT IS,
COMPENSATION AND
FEEDBACK RESISTORS).
OUTPUT CAPACITORS
ARE MOUNTED ON THE
RIGHTMOST AREA OF
THE EVB, WRAPPING
BACK AROUND TO THE
MAIN POWER GROUND
PLANE, WHERE IT MEETS
WITH THE NEGATIVE
TERMINALS OF THE
INPUT CAPACITORS
BYPASS POWER CAPACITOR (C1)
FOR VREG BIAS DECOUPLING
AND HIGH FREQUENCY
CAPACITOR (C2) AS CLOSE AS
POSSIBLE TO THE IC.
08730-082
INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4.
Figure 85. Overall Layout of the ADP1870 High Current Evaluation Board
Rev. 0 | Page 34 of 44
08730-084
ADP1870/ADP1871
Figure 86. Layer 2 of Evaluation Board
Rev. 0 | Page 35 of 44
ADP1870/ADP1871
TOP RESISTOR
FEEDBACK TAP
08730-083
VOUT SENSE TAP LINE
EXTENDING BACK TO THE
TOP RESISTOR IN THE
FEEDBACK DIVIDER
NETWORK (SEE FIGURE 86
TO FIGURE 88). THIS
OVERLAPS WITH PGND
SENSE TAP LINE EXTENDING
BACK TO THE ANALOG
PLANE (SEE FIGURE 88,
LAYER 4 FOR PGND TAP).
Figure 87. Layer 3 of Evaluation Board
Rev. 0 | Page 36 of 44
ADP1870/ADP1871
BOTTOM RESISTOR
TAP TO THE ANALOG
GROUND PLANE
08730-085
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
OUTPUT BULK CAPACITORS.
THIS TRACK PLACEMENT
SHOULD BE DIRECTLY
BELOW THE VOUT SENSE
LINE FROM FIGURE 84.
Figure 88. Layer 4 (Bottom Layer) of Evaluation Board
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 4). This plane should be on only the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly
below this plane on Layer 2, Layer 3, or Layer 4. Connect the
negative terminals of all sensitive analog components to the
analog ground plane. Examples of such sensitive analog components include the resistor divider’s bottom resistor, the high
frequency bypass capacitor for biasing (0.1 μF), and the
compensation network.
Mount a 1 μF bypass capacitor directly across the VREG pin
(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 μF should
be tied across the VREG pin (Pin 5) and the GND pin (Pin 4).
POWER SECTION
As shown in Figure 85, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 89). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4
turns on. When Q3/Q4 turns on, the current direction continues to
be maintained (red arrow) as it circles from the bulk capacitor’s
power ground terminal to the output capacitors, through the
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at source
terminals of Q1/Q2 and drain terminal of Q3/Q4, cause large
dV/dt’s at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components because
this is where most sudden changes in flux density occur. When
possible, replicate this pad onto Layer 2 and Layer 3 for thermal
relief and eliminate any other voltage and current pathways directly
beneath the SW node plane. Populate the SW node plane with
vias, mainly around the exposed pad of the inductor terminal
and around the perimeter of the source of Q1/Q2 and the drain
of Q3/Q4. The output voltage power plane (VOUT) is at the rightmost end of the evaluation board. This plane should be replicated,
descending down to multiple layers with vias surrounding the
inductor terminal and the positive terminals of the output bulk
capacitors. Ensure that the negative terminals of the output
capacitors are placed close to the main power ground (PGND),
as previously mentioned. All of these points form a tight circle
Rev. 0 | Page 37 of 44
ADP1870/ADP1871
(component geometry permitting) that minimizes the area of
flux change as the event switches between D and 1 − D.
SW
LAYER 1: SENSE LINE FOR SW
(DRAIN OF LOWER MOSFET)
LAYER 1: SENSE LINE FOR PGND
(SOURCE OF LOWER MOSFET)
08730-087
VOUT
VIN
PGND
08730-086
Figure 90. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2)
Figure 89. Primary Current Pathways During the On State of the Upper-Side
MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)
DIFFERENTIAL SENSING
Because the ADP1870/ADP1871 operate in valley currentmode control, a differential voltage reading is taken across the
drain and source of the lower-side MOSFET. The drain of the
lower-side MOSFET should be connected as close as possible to
the SW pin (Pin 9) of the IC. Likewise, the source should be
connected as close as possible to the PGND pin (Pin 7) of the
IC. When possible, both of these track lines should be narrow
and away from any other active device or voltage/current path.
Differential sensing should also be applied between the
outermost output capacitor to the feedback resistor divider (see
Figure 87 and Figure 88). Connect the positive terminal of the
output capacitor to the top resistor (RT). Connect the negative
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current path.
Rev. 0 | Page 38 of 44
ADP1870/ADP1871
TYPICAL APPLICATIONS CIRCUITS
15 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 12V
JP3
C28
10µF
CC
571pF
RC
47kΩ
CF
57pF
VOUT
ADP1870/
ADP1871
1
VIN
2
COMP/EN
3
FB
DRVH 8
4
GND
PGND
5
VREG
DRVL 6
R1 30kΩ
R2
15kΩ
C2
0.1µF
BST 10
C12
100nF
C3
22µF
Q1
C4
22µF
C1
1µF
C6
22µF
1.0µH
R4
0Ω
Q3
C7
22µF
C8
N/A
C9
N/A
Q2
SW 9
7
C5
22µF
Q4
VOUT = 1.8V, 15A
C20
270µF
R6
2Ω
C13
1.5nF
C24
N/A
R5
100kΩ
+
+
C21
270µF
C25
N/A
+
+
C22
270µF
C26
N/A
+
+
C23
270µF
C27
N/A
+
+ C14 TO C19
N/A
08730-088
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1µH, 3.3mΩ, 20A 7443552100
Figure 91. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect)
5.5 V INPUT, 600 kHz APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 5.5V
JP3
C28
10µF
CF
57pF
VOUT
ADP1870/
ADP1871
1
VIN
2
COMP/EN
3
FB
DRVH 8
4
GND
PGND 7
5
VREG
DRVL 6
R1 30kΩ
C2
0.1µF
R2
15kΩ
C1
1µF
BST 10
C12
100nF
C3
22µF
Q1
C4
22µF
C5
22µF
C6
22µF
0.47µH
Q3
C8
N/A
C9
N/A
Q2
SW 9
R4
0Ω
C7
22µF
Q4
R6
2Ω
C13
1.5nF
VOUT = 2.5V, 15A
C20
180µF
C24
N/A
R5
100kΩ
+
+
C21
180µF
C25
N/A
+
+
C22
180µF
C26
N/A
+
+
C27
N/A
C23
N/A
+ C14 TO C19
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
180µF, SP-SERIES, 4V, 10mΩ EEFUE0G181XR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
0.47µH, 0.8mΩ, 50A 744355147
Figure 92. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)
Rev. 0 | Page 39 of 44
+
08730-089
CC
571pF
RC
47kΩ
ADP1870/ADP1871
300 kHz HIGH CURRENT APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 13V
JP3
C28
10µF
CF
53pF
VOUT
ADP1870/
ADP1871
1
VIN
2
COMP/EN
3
FB
DRVH 8
4
GND
PGND 7
5
VREG
DRVL 6
R1 30kΩ
C2
0.1µF
R2
15kΩ
C1
1µF
BST 10
C12
100nF
C3
22µF
Q1
C4
22µF
C5
22µF
C6
N/A
1.4µH
Q3
C8
N/A
C9
270µF
Q2
SW 9
R4
0Ω
C7
N/A
Q4
R6
2Ω
C13
1.5nF
VOUT = 1.8V, 12A
C20
270µF
C24
N/A
R5
100kΩ
+
+
C21
270µF
C25
N/A
+
+
C22
270µF
C26
N/A
+
+
C23
270µF
C27
N/A
+ C14 TO C19
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
SANYO OSCON:
270µF, 16SVPC270M, 14mΩ
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
0.72µH, 1.65mΩ, 35A 744325072
Figure 93. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
Rev. 0 | Page 40 of 44
+
08730-090
CC
528pF
RC
43kΩ
ADP1870/ADP1871
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 94. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP1870ARMZ-0.3-R7
ADP1870ARMZ-0.6-R7
ADP1870ARMZ-1.0-R7
ADP1871ARMZ-0.3-R7
ADP1871ARMZ-0.6-R7
ADP1871ARMZ-1.0-R7
ADP1870-0.3-EVALZ
ADP1870-0.6-EVALZ
ADP1870-1.0-EVALZ
ADP1871-0.3-EVALZ
ADP1871-0.6-EVALZ
ADP1871-1.0-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 41 of 44
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
LDW
LDX
LDY
LDG
LDM
LDN
ADP1870/ADP1871
NOTES
Rev. 0 | Page 42 of 44
ADP1870/ADP1871
NOTES
Rev. 0 | Page 43 of 44
ADP1870/ADP1871
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08730-0-3/10(0)
Rev. 0 | Page 44 of 44