Dual-Channel Isolators with Integrated DC/DC Converter ADuM5200/5201/5202 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAMS isoPower™ integrated isolated DC/DC converter Regulated 3V or 5V output 500mW output power Dual dc-to-25 Mbps (NRZ) signal isolation channels Schmitt Trigger Inputs SOIC 16-lead package with > 8mm creepage High temperature operation: 105°C High common-mode transient immunity: > 25 kV/μs Safety and regulatory approvals (pending) UL recognition 2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak APPLICATIONS RS-232/RS-422/RS-485 transceiver Industrial field bus isolation Power Supply start up and Gate Drive Isolated Sensor Interface Industrial PLC GENERAL DESCRIPTION The ADuM520x1 are dual-channel digital isolators with isoPower, an integrated, isolated DC/DC converter. Based on Analog Devices’ iCoupler® technology, the DC/DC converter provides up to 500 mW of regulated, isolated power at either 5.0V from a 5.0V input supply or 3.3V from a 3.3V or 5.0V supply. This eliminates the need for a separate isolated DC/DC converter in low-power isolated designs. Analog Devices’ chipscale transformer iCoupler technology is used both for the isolation of the logic signals as well as for the DC/DC converter. The result is a small form-factor total-isolation solution. ADuM520x units may be used in combination with ADuM540x and ADuM5000 with isoPower to achieve higher output power levels and greater channel counts. Figure 1ADuM520x Functional Diagrams 1 Protected by U.S. Patents 5,952,849, 6,873,065. and 7075 329 B2, Other patents pending. The ADuM520x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see Ordering Guide). Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Preliminary Technical Data ADuM5200/5201/5202 TABLE OF CONTENTS Applications....................................................................................... 1 Pin Configuration and Function Descriptions........................... 12 Revision History ............................................................................... 2 Typical Performance Characteristics ....................................... 15 Specifications..................................................................................... 3 Application Information................................................................ 17 Electrical Characteristics – 5V Primary Input Supply / 5V Secondary Isolated Supply .......................................................... 3 Theory of operation ................................................................... 18 Electrical Characteristics – 3.3V Primary Input Supply / 3.3V Secondary Isolated Supply .......................................................... 5 PC Board Layout ........................................................................ 18 Thermal Analysis ....................................................................... 18 Electrical Characteristics – 5V Primary Input Supply / 3.3V Secondary Isolated Supply .......................................................... 7 Propagation Delay-Related Parameters................................... 19 Package Characteristics ............................................................... 9 Power Consumption .................................................................. 20 Insulation and Safety-Related Specifications............................ 9 Insulation Lifetime ..................................................................... 21 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 10 Outline Dimensions ....................................................................... 23 Recommended Operating Conditions .................................... 10 DC Correctness and Magnetic Field Immunity........................... 19 Ordering Guide .......................................................................... 23 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 REVISION HISTORY Rev. PrA | Page 2 of 23 Preliminary Technical Data ADuM5200/5201/5202 SPECIFICATIONS ELECTRICAL CHARACTERISTICS – 5V PRIMARY INPUT SUPPLY / 5V SECONDARY ISOLATED SUPPLY1 4.5 V ≤ VDD1 ≤ 5.5 V, VSEL=VISO; all voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD = 5.0 V, VISO = 5.0 V, VSEL= VISO. Table 1. Parameter Setpoint Line Regulation Load Regulation Output Ripple Symbol VISO VISO(LINE) VISO(LOAD) VISO(RIP) Output Noise VISO(N) 200 mVP-P Switching Frequency PWM Frequency DC to 2 Mbps Data Rate2 Maximum Output Supply Current3 Efficiency At Max. Output Supply Current4 IDD1 Supply Current, No VISO load5 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load6 ADuM5200 ADuM5201 ADuM5202 Available VISO Supply Current7 ADuM5200 ADuM5201 ADuM5202 IDD1 Supply Current, Full VISO load8 fOSC fPWM 180 625 MHz kHz IDD1(Q) 34 19 mA % mA f ≤ 1 MHz, VISO=5V IISO = IISO(2,max), f ≤ 1 MHz IISO = 0mA, f ≤ 1 MHz IDD1(D) IDD1(D) IDD1(D) 34 38 41 mA mA mA IISO = 0mA, CL=15pF, f = 12.5 MHz IISO = 0mA, CL=15pF, f = 12.5 MHz IISO = 0mA, CL=15pF, f = 12.5 MHz IISO(LOAD) IISO(LOAD) IISO(LOAD) IDD1(Max) 94 92 90 290 mA mA mA mA CL=15pF, f = 12.5 MHz CL=15pF, f = 12.5 MHz CL=15pF, f = 12.5 MHz CL=0pF, f = 0 MHz, VDD = 5V IISO=100mA I/O Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages IISO(max) IIA, IIB VIH VIL VOAH, VOBH VOAH, VOBH Logic Low Output Voltages AC SPECIFICATIONS ADuM520xARWZ Minimum Pulse Width9 Maximum Data Rate10 Propagation Delay11 Pulse-Width Distortion, |tPLH − tPHL|11 Propagation Delay Skew12 Channel-to-Channel Matching13 ADuM520xCRWZ Minimum Pulse Width9 Maximum Data Rate14 Propagation Delay15 Min 4.7 Typ 5.0 1 1 75 Max 5.4 5 100 −10 0.7 VISO +0.01 VDD1 − 0.3, VISO − 0.3 VDD1 − 0.3, VISO − 0.3 30 +10 5.0 IOx = −20 μA, VIx = VIxH 4.8 V IOx = −4 mA, VIx = VIxH 0.1 0.4 V V IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels ns Mbps ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels 0.0 0.0 PW 1 tPHL, tPLH PWD tPSK tPSKCD/OD 55 PW 100 40 50 50 40 25 tPHL, tPLH Test Conditions IISO=0mA IISO=50mA, VDD1=4.5V to 5.5V IISO = 10mA to 90mA 20MHz Bandwidth, CBO=0.1μF ║ 10μF, IISO = 100mA 20MHz Bandwidth, CBO=0.1μF ║ 10μF, IISO = 100mA μA V V V 0.3 VISO VOAL, VOBL VOAL, VOBL Unit V mV/V % mVP-P 45 Rev. PrA | Page 3 of 23 60 ADuM5200/5201/5202 Parameter Pulse-Width Distortion, |tPLH − tPHL|11 Change vs. Temperature Propagation Delay Skew16 Channel-to-Channel Matching, Codirectional Channels17 Channel-to-Channel Matching, Opposing-Directional Channels17 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate Preliminary Technical Data Symbol PWD Min Typ Max 6 tPSK tPSKCD 15 6 Unit ns ps/°C ns ns tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V 5 tR/tF |CMH| 25 2.5 35 ns kV/μs |CML| 25 35 kV/μs 1.0 Mbps fr 1 Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels All voltages are relative to their respective ground. The contributions of supply current values for all four channels are combined at identical data rates. VISO supply current available for external use when all data rates are below 2Mbps. At data rates above 2Mbps data I/O channels will draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget. 4 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of its internal power consumption. 5 IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2Mbps, requiring no additional dynamic supply current. It reflects the minimum current operating condition. 6 IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. 7 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to Power Consumption section for calculation of available current at less than maximum data rate. 8 IDD1(MAX) is the input current under full dynamic and VISO load conditions. 9 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 10 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 11 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 12 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 13 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. 2 3 Rev. PrA| Page 4 of 23 Preliminary Technical Data ADuM5200/5201/5202 ELECTRICAL CHARACTERISTICS – 3.3V PRIMARY INPUT SUPPLY / 3.3V SECONDARY ISOLATED SUPPLY1 3.0 V ≤ VDD1 ≤ 3.6 V, VSEL=GNDISO; all voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD = 3.3 V, VISO = 3.3 V, VSEL= GNDISO. Table 2. Parameter Setpoint Line Regulation Load Regulation Output Ripple Symbol VISO VISO(LINE) VISO(LOAD) VISO(RIP) Output Noise VISO(N) 130 mVP-P Switching Frequency PWM Frequency DC to 2 Mbps Data Rate2 Maximum Output Supply Current3 Efficiency At Max. Output Supply Current4 IDD1 Supply Current, No VISO load5 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load6 ADuM5200 ADuM5201 ADuM5202 Available VISO Supply Current7 ADuM5200 ADuM5201 ADuM5202 IDD1 Supply Current, Full VISO load8 fOSC fPWM 180 625 MHz kHz IDD1(Q) 36 10 mA % mA f ≤ 1 MHz, VISO=3.15V IISO = IISO(2,max), f ≤ 1 MHz IISO = 0mA, f ≤ 1 MHz IDD1(D) IDD1(D) IDD1(D) 23 25 28 mA mA mA IISO = 0mA, CL=15pF, f = 12.5 MHz IISO = 0mA, CL=15pF, f = 12.5 MHz IISO = 0mA, CL=15pF, f = 12.5 MHz IISO(LOAD) IISO(LOAD) IISO(LOAD) IDD1(Max) 106 105 103 175 mA mA mA mA CL=15pF, f = 12.5 MHz CL=15pF, f = 12.5 MHz CL=15pF, f = 12.5 MHz CL=0pF, f = 0 MHz, VDD = 3.3V, IISO=60mA IISO(max) Input Currents Logic High Input Threshold IIA, IIB VIH Logic Low Input Threshold VIL Logic High Output Voltages VOAH, VOBH VOAH, VOBH Logic Low Output Voltages AC SPECIFICATIONS ADuM520xARWZ Minimum Pulse Width9 Maximum Data Rate10 Propagation Delay11 Pulse-Width Distortion, |tPLH − tPHL|11 Propagation Delay Skew12 Channel-to-Channel Matching13 ADuM520xCRWZ Min 3.13 Typ 3.3 1 1 50 Max 3.37 5 60 −10 +0.01 20 +10 μA V 0.3 × VISO, 0.3 × VIDD1 V 0.7 × VISO, 0.7 × VIDD1 VDD1 − 0.2, VISO − 0.2 VDD1 − 0.5, V1SO − 0.5 VOAL, VOBL VOAL, VOBL Test Conditions IISO=0mA IISO=37.5 mA, VDD1=3.0V to 3.6V IISO = 6mA to 54mA 20MHz Bandwidth, CBO=0.1μF ║ 10μF, IISO = 90mA 20MHz Bandwidth, CBO=0.1μF ║ 10μF, IISO = 90mA 5.0 V IOx = −20 μA, VIx = VIxH 4.8 V IOx = −4 mA, VIx = VIxH 0.1 0.4 V V IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels 0.0 0.0 PW 1 tPHL, tPLH PWD tPSK tPSKCD/OD Unit V mV/V % mVP-P 60 Rev. PrA | Page 5 of 23 100 40 50 50 ADuM5200/5201/5202 Parameter Minimum Pulse Width13 Maximum Data Rate14 Propagation Delay15 Pulse-Width Distortion, |tPLH − tPHL|11 Change vs. Temperature Propagation Delay Skew16 Channel-to-Channel Matching, Codirectional Channels17 Channel-to-Channel Matching, Opposing-Directional Channels17 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate Preliminary Technical Data Symbol PW Min Typ Max 40 tPSK tPSKCD 45 6 Unit ns Mbps ns ns ps/°C ns ns 45 60 6 tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V 25 tPHL, tPLH PWD 5 tR/tF |CMH| 25 2.5 35 ns kV/μs |CML| 25 35 kV/μs 1.0 Mbps fr 1 Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels All voltages are relative to their respective ground. The contributions of supply current values for all four channels are combined at identical data rates. VISO supply current available for external use when all data rates are below 2Mbps. At data rates above 2Mbps data I/O channels will draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget. 4 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of its internal power consumption. 5 IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2Mbps, requiring no additional dynamic supply current. It reflects the minimum current operating condition. 6 IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. 7 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to Power Consumption section for calculation of available current at less than maximum data rate. 8 IDD1(MAX) is the input current under full dynamic and VISO load conditions. 9 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 10 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 11 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 12 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 13 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. 2 3 Rev. PrA| Page 6 of 23 Preliminary Technical Data ADuM5200/5201/5202 ELECTRICAL CHARACTERISTICS – 5V PRIMARY INPUT SUPPLY / 3.3V SECONDARY ISOLATED SUPPLY1 4.5 V ≤ VDD1 ≤ 5.5 V, VSEL= GNDISO, all voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD = 5.0 V, VISO = 3.3 V, VSEL= GNDISO. Table 3. Parameter Setpoint Line Regulation Load Regulation Output Ripple Symbol VISO VISO(LINE) VISO(LOAD) VISO(RIP) Output Noise VISO(N) 130 mVP-P Switching Frequency PWM Frequency DC to 2 Mbps Data Rate2 Maximum Output Supply Current3 Efficiency At Max. Output Supply Current4 IDD1 Supply Current, No VISO load5 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load6 ADuM5200 ADuM5201 ADuM5202 Available VISO Supply Current7 ADuM5200 ADuM5201 ADuM5202 IDD1 Supply Current, Full VISO load8 fOSC fPWM 180 625 MHz kHz IDD1(Q) 30 9 mA % mA f ≤ 1 MHz, VISO=3.0V IISO = IISO(2,max), f ≤ 1 MHz IISO = 0mA, f ≤ 1 MHz IDD1(D) IDD1(D) IDD1(D) 22 25 27 mA mA mA IISO = 0mA, CL=15pF, f = 12.5 MHz IISO = 0mA, CL=15pF, f = 12.5 MHz IISO = 0mA, CL=15pF, f = 12.5 MHz IISO(LOAD) IISO(LOAD) IISO(LOAD) IDD1(Max) 96 95 93 230 mA mA mA mA CL=15pF, f = 12.5 MHz CL=15pF, f = 12.5 MHz CL=15pF, f = 12.5 MHz CL=0pF, f = 0 MHz, VDD = 5V, IISO=100mA Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages IISO(max) IIA, IIB VIH VIL VOAH, VOBH VOAH, VOBH Logic Low Output Voltages AC SPECIFICATIONS ADuM520xARWZ Minimum Pulse Width9 Maximum Data Rate10 Propagation Delay11 Pulse-Width Distortion, |tPLH − tPHL|11 Propagation Delay Skew12 Channel-to-Channel Matching13 ADuM520xCRWZ Minimum Pulse Width13 Maximum Data Rate14 Propagation Delay15 Min 3.0 Typ 3.3 1 1 50 Max 3.6 5 100 −10 0.7 VISO +0.01 VDD1 − 0.2, VISO − 0.2 VDD1 − 0.5, V1SO − 0.5 13 +10 5.0 IOx = −20 μA, VIx = VIxH 4.8 V IOx = −4 mA, VIx = VIxH 0.1 0.4 V V IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels ns Mbps ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels 0.0 0.0 PW 1 tPHL, tPLH PWD tPSK tPSKCD/OD 60 PW 100 40 50 50 40 25 tPHL, tPLH Test Conditions IISO=0mA IISO=50mA, VDD1=4.5V to 5.5V IISO = 10mA to 100mA 20MHz Bandwidth, CBO=0.1μF ║ 10μF, IISO = 90mA 20MHz Bandwidth, CBO=0.1μF ║ 10μF, IISO = 90mA μA V V V 0.3 VISO VOAL, VOBL VOAL, VOBL Unit V mV/V % mVP-P 45 Rev. PrA | Page 7 of 23 60 ADuM5200/5201/5202 Parameter Pulse-Width Distortion, |tPLH − tPHL|11 Change vs. Temperature Propagation Delay Skew16 Channel-to-Channel Matching, Codirectional Channels17 Channel-to-Channel Matching, Opposing-Directional Channels17 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate Preliminary Technical Data Symbol PWD Min Typ Max 6 tPSK tPSKCD 45 6 Unit ns ps/°C ns ns tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V 5 tR/tF |CMH| 25 2.5 35 ns kV/μs |CML| 25 35 kV/μs 1.0 Mbps fr 1 Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels All voltages are relative to their respective ground. The contributions of supply current values for all four channels are combined at identical data rates. VISO supply current available for external use when all data rates are below 2Mbps. At data rates above 2Mbps data I/O channels will draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget. 4 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of its internal power consumption. 5 IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2Mbps, requiring no additional dynamic supply current. It reflects the minimum current operating condition. 6 IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. 7 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to Power Consumption section for calculation of available current at less than maximum data rate. 8 IDD1(MAX) is the input current under full dynamic and VISO load conditions. 9 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 10 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 11 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 12 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 13 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. 2 3 Rev. PrA| Page 8 of 23 Preliminary Technical Data ADuM5200/5201/5202 PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input-to-Output)1 Capacitance (Input-to-Output)1 Input Capacitance2 IC Junction to Ambient Thermal Resistance Symbol RI-O CI-O CI θCA Thermal Shutdown Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSSD TSSD-HYS 1 2 3 Min Typ 1012 2.2 4.0 45 Max 150 20 Unit Ω pF pF °C/W °C °C Test Conditions f = 1 MHz Thermocouple located at center of package underside, test conducted on 4 layer board with thin traces3. TJ Rising Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. Input capacitance is from any input data pin to ground. Refer to the Power Considerations section for thermal model definitions Table 5. UL (Pending) Recognized under 1577 component recognition program1 Reinforced insulation, 2500 V rms isolation voltage File E214100 CSA (Pending) Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 300 V rms (424 V peak)maximum working voltage File 205078 VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 560 V peak File 2471900-4880-0001 1 In accordance with UL1577, each ADuM520x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM520x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 2500 L(I01) >8 min Unit Conditions V rms 1 minute duration mm Measured from input terminals to output terminals, shortest distance through air >8 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >175 V DIN IEC 112/VDE 0303 Part 1 IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Minimum External Tracking (Creepage) L(I02) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Rev. PrA | Page 9 of 23 ADuM5200/5201/5202 Preliminary Technical Data DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 7. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure ( see Figure 2) VIO = 500 V RECOMMENDED OPERATING CONDITIONS 600 Safe Operating VDD1 Current (mA) Symbol 500 Table 8. Parameter Operating Temperature Supply Voltages1 VDD @ VSEL=0V VDD @ VSEL=5V Minimum Load 400 300 200 100 Symbol TA Min −40 Max +105 Unit °C VDD VDD IISO(MIN) 3.0 4.5 10 5.5 5.5 V V mA 0 0 50 100 150 200 1 All voltages are relative to their respective ground. Am bient Tem pearture (°C) Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 Rev. PrA| Page 10 of 23 Preliminary Technical Data ADuM5200/5201/5202 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 9. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VDD, VISO)1 Input Voltage (VIA, VIB, VE1, VE2,RCSEL, VSEL)1, 2 Output Voltage (VOA, VOB)1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2(IOISO) Common-Mode Transients4 Rating −55°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −18 mA to +18 mA −22 mA to +22 mA −100 kV/μs to +100 kV/μs ESD CAUTION 1 All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 2 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings may cause latchup or permanent damage. 2 Table 10. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Max 424 Unit V peak Constraint 50-year minimum lifetime 600 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 600 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 11. Truth Table (Positive Logic) RCIN Input X X X X EXT-PWM L X X H RCSEL Output H H H H L L X X L VSEL Input1 H L H L X L X X X VDDI Input 5.0V 5.0V 3.3V 3.3V X X X X X VISO Output 5.0V 3.3V 5.0V 3.3V X 0V X X X VIX Input X X X X X X H L X VOX Output X X X X X X H L X Notes Master mode operation, Self Regulating Master mode operation, Self Regulating Master mode operation, Self Regulating Master mode operation, Self Regulating Slave mode operation, Regulation from another isoPower part. Low power mode, Converter disabled Data outputs valid for any active power configuration. Data outputs valid for any active power configuration WARNING! This combination of RCIN and RCSEL is prohibited. Damage will occur on the secondary due to exess output voltage at VISO. RCin must be either Low or a PWM signal from a master isoPower part.. Rev. PrA | Page 11 of 23 Preliminary Technical Data ADuM5200/5201/5202 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. ADuM5200 Pin Configuration Table 12. ADuM5200 Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage 3.0V to 5.5 V. 2,8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 RCIN Regulation Control Input, In slave power configuration (RCSEL=Low), this pin is connected to the RCOUT of a master isoPower device, or tied low to disable the converter. In Master/Stand alone mode(RCSEL=High) this pin has no function. This pin is weakly pulled to low. In Noisy environments it should be tied to low or to a PWM control source. Warning -This pin must not be tied high if RCSEL is low, this combination will cause excessive volatge on the secondary, damaging the ADuM5000 and possibly devices that it powers. 6 RCSEL Control input, Determines self regulation (CTL High) mode or Slave mode(CTL Low)allowing external regulation. This pin is weakly pulled to high. In noisy environments it should be tied either high or low. 7 NC No Internal Connection 9,15 GNDISO Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 VE2 Data Enable Input, When High or NC the Secondary outputs are active, when Low the outputs are in a high Z state.. 11 VSEL Output Voltage Selection: When VSEL = VISO then the Viso set point is 5.0V, When VSEL = GNDISO Then the VISO setpoint is 3.3V. In Slave regulation mode, this pin has no function. 12 NC No Internal Connection. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage Output for Secondary Isolaton electronics and External Loads, 3.3V (VSEL Low) or 5.0V (VSEL High), 5.0V output Functioanlity not guaranteed for a 3.3V primary supply input. Rev. PrA | Page 12 of 23 Preliminary Technical Data ADuM5200/5201/5202 Figure 4. ADuM5201 Pin Configuration Table 13. ADuM5201 Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage 3.0V to 5.5 V. 2,8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VOB Logic Output B. 5 RCIN Regulation Control Input, In slave power configuration (RCSEL=Low), this pin is connected to the RCOUT of a master isoPower device, or tied low to disable the converter. In Master/Stand alone mode(RCSEL=High) this pin has no function. This pin is weakly pulled to low. In Noisy environments it should be tied to low or to a PWM control source. Warning -This pin must not be tied high if RCSEL is low, this combination will cause excessive volatge on the secondary, damaging the ADuM5000 and possibly devices that it powers. 6 RCSEL Control input, Determines self regulation (CTL High) mode or Slave mode(CTL Low)allowing external regulation. This pin is weakly pulled to high. In noisy environments it should be tied either high or low. 7 VE1 Data Enable Input, When High or NC the Primary output is active, when Low the outputs are in a high Z state.. 9,15 GNDISO Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 VE2 Data Enable Input, When High or NC the Secondary output is active, when Low the outputs are in a high Z state.. 11 VSEL Output Voltage Selection: When VSEL = VISO then the Viso set point is 5.0V, When VSEL = GNDISO Then the VISO setpoint is 3.3V. In Slave regulation mode, this pin has no function. 12 NC No Internal Connection. 13 VIB Logic Input B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage Output for Secondary Isolaton electronics and External Loads, 3.3V (VSEL Low) or 5.0V (VSEL High), 5.0V output Functioanlity not guaranteed for a 3.3V primary supply input. Rev. PrA | Page 13 of 23 ADuM5200/5201/5202 Preliminary Technical Data Figure 5. ADuM5202 Pin Configuration Table 14. ADuM5202 Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage 3.0V to 5.5 V. 2,8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VOA Logic Output A. 4 VOB Logic Output B. 5 RCIN Regulation Control Input, In slave power configuration (RCSEL=Low), this pin is connected to the RCOUT of a master isoPower device, or tied low to disable the converter. In Master/Stand alone mode(RCSEL=High) this pin has no function. This pin is weakly pulled to low. In Noisy environments it should be tied to low or to a PWM control source. Warning -This pin must not be tied high if RCSEL is low, this combination will cause excessive volatge on the secondary, damaging the ADuM5000 and possibly devices that it powers. 6 RCSEL Control input, Determines self regulation (CTL High) mode or Slave mode(CTL Low)allowing external regulation. This pin is weakly pulled to high. In noisy environments it should be tied either high or low. 7 VE1 Data Enable Input, When High or NC the Primary output is active, when Low the outputs are in a high Z state.. 9,15 GNDISO Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 NC No Internal Connection 11 VSEL Output Voltage Selection: When VSEL = VISO then the Viso set point is 5.0V, When VSEL = GNDISO Then the VISO setpoint is 3.3V.. 12 NC No Internal Connection. 13 VIB Logic Input B. 14 VOA Logic Input A. 16 VISO Secondary Supply Voltage Output for Secondary Isolaton electronics and External Loads, 3.3V (VSEL Low) or 5.0V (VSEL High), 5.0V output Functioanlity not guaranteed for a 3.3V primary supply input. Rev. PrA| Page 14 of 23 Preliminary Technical Data ADuM5200/5201/5202 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.35 Efficiency 0.3 0.25 0.2 0.15 3.3V in / 3.3V out 0.1 5V in / 3.3V out 0.05 5V in / 5V out 0 0 0.02 0.04 0.06 0.08 0.1 0.12 Output Current (A) Figure 6. Typical Power Supply Efficiency at 5V/5V, 3.3V/3.3V and 5V/3.3V Figure 9. Typical VISO Transient Load Response 5V Output 10%-90% Load Step 0.12 Onput Current (A) 0.1 0.08 0.06 0.04 3.3V in / 3.3V out 0.02 5V in / 3.3V out 5V in / 5V out 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Input Current (A) Figure 10. Typical Transient Load Response 3V Output 10%-100% Load Step Figure 7. Typical Isolated Output Supply Current, IISO as a function of external load, no dynamic current draw at 5V/5V, 3.3V/3.3V and 5V/3.3V 4 Input Current (A) and Power (W) 3.5 3 2.5 2 Idd 1.5 Pow er 1 0.5 0 3 3.5 4 4.5 5 5.5 6 6.5 Input Voltage (V) Figure 8. Typical Short Circuit Input Current and Power vs. VDD supply voltage Rev. PrA | Page 15 of 23 ADuM5200/5201/5202 Preliminary Technical Data 20.00 5V in 5V out CURRENT (mA) 16.00 3.3V in 3.3V out 5V in 3.3V out 12.00 8.00 4.00 0.00 0 5 10 15 20 25 DATA RATE (Mbps) Figure 14 Typical ICH Supply Current per Reverse Data Channel (15 pF Output Load Figure 11. Typical Viso=5V Output Voltage Ripple at 90% Load 5.00 5V CURRENT (mA) 4.00 3.3V 3.00 2.00 1.00 0.00 0 5 10 15 20 25 DATA RATE (Mbps) Figure 15. Typical IISO(D) Dynamic Supply Current per Input Figure 12. Typical Viso=3.3V Output Voltage Ripple at 90% Load 20 3.00 5V in 5V out 5V 2.50 3.3V in 3.3V out 16 CURRENT (mA) 5V in 3.3V out 12 8 3.3V 2.00 1.50 1.00 0.50 4 0.00 0 0 0 5 10 15 20 25 5 10 15 20 25 DATA RATE (Mbps) D A T A R A T E ( M bps ) Figure 13. . Typical ICH Supply Current per Forward Data Channel (15 pF Output Load Figure 16. Typical IISO(D) Dynamic Supply Current per Output (15pF Output Load) Rev. PrA| Page 16 of 23 ADuM5200/5201/5202 TERMINOLOGY IDD1(Q) IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2 Mbps, requiring no additional dynamic supply current. IDDIO(Q) reflects the minimum current operating condition. IDD1(D) IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. IDD1(MAX) IDD1(MAX) is the input current under full dynamic and VISO load conditions. tPHL Propagation Delay tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH Propagation Delay tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Propagation Delay Skew (tPSK) tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Channel-to-Channel Matching Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. Minimum Pulse Width The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Maximum Data Rate The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. Rev. PrA | Page 17 of 23 ADuM5200/5201/5202 Preliminary Technical Data APPLICATION INFORMATION THEORY OF OPERATION The DC/DC converter section of the ADuM520x works on principles that are common to most modern power supply designs. It is implemented as a secondary side controller with isolated PWM feedback. VDD1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. Power is transferred to the secondary side where it is rectified to a DC voltage. The power is then regulated to either 3.3or 5V and supplied to the secondary side data section and to the VISO pin for external use. Active feedback is implemented by a digital feedback path. The output regulator creates a pulse width modulated signal which is coupled to the input side and switches the oscillator on and off regulating the power. Feedback allows for significantly higher power, efficiency, and synchronization of multiple supplies. The ADuM520x provides its Regulation Control output (RCout) signal that can be connected to other isoPower devices. This allows a single regulator to control multiple power modules without contention. When auxiliary power modules are present, the VSIO pins can be connected together to work as a single supply. Since there is only one feedback control path, the supplies will work together seamlessly. The ADuM520x can only be a source of Regulation Control, other devices There is hysteresis into the input VDD input voltage detect circuit. Once the DC/DC converter is active, the input voltage must be decreased below the turn on threshold to disable the converter. This feature ensures that the converter does not go into oscillation due to noisy input power. PC BOARD LAYOUT The ADuM520x digital isolator with a ½W isoPower integrated DC/DC converter requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (Figure 17). The power supply section of the ADuM520X uses a very high oscillator frequency to efficiently pass power through its chip scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance high frequency capacitor, ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0. 1 μF, and 6.6μF. It is strongly recommended that a very low inductance ceramic or equivalent capacitor be used for the smaller value. Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 4 mm. Installing the bypass capacitor with traces more than 4 mm in length may result in data corruption. A bypass between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both common ground pins are connected together close to the package. Figure 17. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, specified in Table 9 thereby leading to latch-up and/or permanent damage. The ADuM520x is a power device that dissipates about 1W of power when fully loaded and running at maximum speed. Since it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the PCB through the GND pins. If the device will be used at high ambient temperatures, care should be taken to provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 17 shows enlarged pads for pins 2, 8, 9, and 15. Multiple vias should be implemented from the pad to the ground plane. This will significantly reduce the temperatures inside of the chip. The dimensions of the expanded pads are left to discretion of the designer and the available board space. THERMAL ANALYSIS The ADuM520x parts consist of four internal die, attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis it is treated as a thermal unit with the highest junction temperature reflected in the θJA from Table 4. The value of θJA is based on measurements taken with the part mounted on a JEDEC standard 4 layer board with fine width traces and still air. Under normal operating conditions the ADuM520x will operate at full load across the full temperature range without derating the output current. However, following the recommendations in the PC Board Layout section will Rev. PrA | Page 18 of 23 ADuM5200/5201/5202 decrease the thermal resistance to the PCB allowing increased thermal margin it high ambient temperatures. β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high. Given the geometry of the receiving coil in the ADuM520x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19. 50% tPHL OUTPUT (VOX) 03786-018 tPLH 50% Figure 18. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 INPUT (VIX) 10 1 0.1 Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM520x components operating under the same conditions. 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 03786-019 0.01 Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM520x component. Figure 19. Maximum Allowable External Magnetic Flux Density DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Error! Reference source not found.) by the watchdog timer circuit. The limitation on the ADuM520x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM520x is examined because it represents the most susceptible mode of operation. For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM520x transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM520x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM520x to affect the component’s operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)∑πrn2; n = 1, 2, … , N where: Rev. PrA | Page 19 of 23 ADuM5200/5201/5202 Preliminary Technical Data direction, which means that the input on the secondary side of the part. Both figures assume a typical 15pF load. The following relationship allows the total IDD1 current to be calculated. DISTANCE = 1m 100 IDD1 = (IISO × VISO)/(E × VDD1) + ∑ ICHn; n = 1to 4 10 DISTANCE = 100mm Equation 1 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 03786-020 MAXIMUM ALLOWABLE CURRENT (kA) 1000 Where : IDD1 is the total supply input current. ICHn is the current drawn by a single channel determined from Figure 15 or Figure 16 depending on channel direction. IISO is the current drawn by the secondary side external loads. E is the power supply efficiency at 100mA load from Figure 6 at the VISO and VDD1 condition of interest. Figure 20. Maximum Allowable Current for Various Current-to-ADuM520x Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. POWER CONSUMPTION The VDD1 power supply input provides power to the iCoupler data channels as well as the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary I/O channels cannot be determined separately. All of these quiescent power demands have been combined into the IDD1(Q) current as shown in Figure 21. The total IDD1 supply current will be the sum of the quiescent operating current, dynamic current IDD1(D) demanded by the I/O channels, and any external IISO load. The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. IISO(LOAD) = IISO(MAX) - ∑ IISO(D)n; n = 1to 4 Equation 2 Where: IISO(LOAD) is the current available to supply an external secondary side load. IISO(MAX) is the maximum external secondary side load current available at VISO. IISO(D)n is the dynamic load current drawn from VISO by an input or output channel, as shown in Figure 15 and Figure 16. Data is presented assuming a typical 15pF load The preceding analysis assumes a 15pF capacitive load on each data output. If a capacitive load larger than 15pF, he additional current must be included in the analysis of IDD1 and IISO(LOAD) . To determine IDD1 in Equation 1, additional primary side dynamic output current IAOD is added directly to IDD1. Additional secondary side dynamic output current IAOD is added to IISO on a per channel basis. To determine IISO(LOAD) in Equation 2, additional secondary side output current IAOD is subtracted from IISO(MAX) on a per channel basis. For each output channel with CL greater than 15pF, the additional capacitive supply current is given by: IAOD = 0.5 × 10−3 × (CL-15) × VISO) × (2f − fr) f > 0.5 fr Equation 3 Figure 21 Power consumption within the ADuM520x Both Dynamic I/O current is consumed only when operating at channel at speeds higher than the rate fr. Since each channel will have a dynamic current that is determined by its data rate, Figure 15 shows the current for a channel in the forward direction, which means that the input on the primary side of the part. Figure 16 shows the current for a channel in the reverse Where: CL is the output load capacitance. (pF). VISO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input channel refresh rate (Mbps). Rev. PrA | Page 20 of 23 ADuM5200/5201/5202 POWER CONSIDERATIONS The ADuM520x Converter Primary side, Data input channels on the Primary side and Data input channels on the Secondary side are all protected from premature operation by Under Voltage Lock Out (UVLO) circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. Outputs are held in their default low state. This is to prevent transmission of undefined states during power up and power down operations. regulated by the master device allowing multiple isoPower parts to be combined in parallel while sharing the load equally. When the ADuM5000 is configured as a Stand alone unit, it generates its own PWM feedback signal to regulate itself and slave devices. The ADuM5000 can act as a master or a slave deice, the ADuM5400 can only be a master/stand alone device, and the ADuM5200 can only be a slave/Stand alone device. This means that the ADuM5000, ADuM5200, and ADuM5400 can only be used in certain master slave combinations as listed in Table 15. Slave ADuM5000 During application of power to VDD1, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time the data channels initialize to their default low output state until they receive data pulses from the secondary side. The primary side input channels sample the input and send pulse to the inactive secondary output. The secondary side converter begins to accept power from the primary and the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data, either a transition or a DC refresh pulse, is received from the corresponding primary side input. It could take up to 1μS after the secondary side is initialized for the state of the output to correlate with the primary side input. Secondary side inputs sample their state and transmit it to the Primary side. Outputs are valid one propagation delay after the secondary side becomes active. Because the rate of charge of the secondary side is dependant on loading conditions, input voltage and output voltage level selected, care should be taken in the design to allow the converter to stabilize before valid data is required. When power is removed from VDD1, the primary side converter and coupler shut down when UVLO is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side will hold the last state that they received from the primary until either the UVLO level is reached and the outputs are put in their default low state or the output detects a lack of activity from the input and the outputs are set to default before secondary power reaches UVLO. INCREASING AVAILABLE POWER The ADuM5200 devices are designed with capability of running in combination with other compatible isoPower devices. The RCIN and RCSEL pins allow the ADuM5200 to receive a PWM signal from another device through the RCIN pin and act as a slave to that control signal. The RCSEL pin chooses whether the part will act as a stand alone self regulated device or slave device. When the ADuM5200 is acting as a slave, its power is Master ADuM5200 ADuM5400 ADuM5000 Y Y N ADuM5200 N N N ADuM5400 Y Y N Table 15 Allowed combinations of isoPower Parts The allowed combinations of master and slave configured parts listed in Table 15 is sufficient to make any combination of power and channel count. Table 16 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power. Number of Data Channels 1 Unit Power 0 ADuM5000 Master 2 ADuM520x Master 4 ADuM540x Master 6 ADuM540x Master ADuM12xx 2 Unit Power ADuM5000 Master ADuM5000 Slave ADuM500x Master ADuM5200 Slave ADuM540x Master ADuM5200 Slave ADuM540x Master ADuM520x Slave 3 Unit Power ADuM5000 Master ADuM5000 Slave ADuM5000 Slave ADuM5000 Master ADuM5000 Slave ADuM520x Slave ADuM540x Master ADuM5000 Slave ADuM5000 Slave ADuM540x Master ADuM520x Slave ADuM5000 Slave Table 16 Configurations for Power and Data Channels INSULATION LIFETIME All insulation structures will eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependant on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM520x. ADI performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors Rev. PrA | Page 21 of 23 ADuM5200/5201/5202 Preliminary Technical Data for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. 0V Figure 22. Bipolar AC Waveform 05007-022 RATED PEAK VOLTAGE The insulation lifetime of the ADuM520x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 22, Figure 23, and Figure 24 illustrate these different isolation voltage waveforms. 0V Figure 23. Unipolar AC Waveform 05007-023 RATED PEAK VOLTAGE Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines ADI’s recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50 year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 231or Figure 24 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50 year lifetime voltage value listed in Table 10. 05007-021 RATED PEAK VOLTAGE 0V Figure 24. DC Waveform 1 The voltage presented in Figure 23 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0V. Rev. PrA | Page 22 of 23 ADuM5200/5201/5202 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1 1.27 (0.0500) BSC 0.75 (0.0295) × 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 8° 0.33 (0.0130) 0° 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimension shown in millimeters and (inches) ORDERING GUIDE Model ADuM5200ARWZ1,2 ADuM5200CRWZ1,2 ADuM5201ARWZ1,2 ADuM5201CRWZ1,2 ADuM5202ARWZ1,2 ADuM5202CRWZ 1,2 1 2 Number of Inputs, VDD1 Side 2 2 1 1 0 0 Number of Inputs, VDD2 Side 0 0 1 1 2 2 Maximum Data Rate (Mbps) 1 25 1 25 1 25 Maximum Propagation Delay, 5 V (ns) 100 70 100 70 100 70 Maximum Pulse Width Distortion (ns) 40 3 40 3 40 3 Temperature Range (°C) −40 to +105 −40 to +105 −40 to +105 −40 to +105 −40 to +105 −40 to +105 Package Option 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W Tape and reel are available. The additional “-RL7” suffice designates a 7” (1,000 units) tape and reel options. Z = Pb-free part. Rev. PrA | Page 23 of 23 PR07540-0-5/08(PrA)