CY28370 High-performance SiS645/650/660 Pentium 4 Clock Synthesizer Features Supports Intel Pentium 4-type CPUs 3.3V power supply Eight copies of PCI clocks One 48-MHz USB clock Two copies of ZCLK clocks One 48-MHz/24-MHz programmable SIO clock Two differential CPU clock pairs • • • • • • • SMBus support with readback capabilities Spread Spectrum EMI reduction Dial-a-Frequency™ features Dial-a-Ratio™ features Dial-a-DB™ features 48-pin SSOP package Watchdog function Pin Configuration[1] Block Diagram XIN XOUT REF(0:2) CPU(0:1)T CPU(0:1)C PLL1 CPU_STP# SDCLK IREF FS(0:4) MULT0 VDDR **FS0/REF0 **FS1/REF1 **FS2/REF2 VSSR XIN XOUT VSSZ ZCLK0 ZCLK1 VDDZ *SRESET#/PCI_STP# VDDP **FS3/PCI_F0 **FS4/PCI_F1 PCI0 PCI1 VSSP VDDP PCI2 PCI3 PCI4 PCI5 VSSP AGP(0:1) Power on Latch ZCLK(0:1) VTTPWRGD /2 PCI_STP# PCI(0:5) PCI_F(0:1) PLL2 48M 48M_24M# PD# WD Logic SDATA SCLK I2C Logic SRESET# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 &< • • • • • • • 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDSD SDCLK VSSSD CPU_STP#* CPU1T CPU1C VDDC VSSC CPU0T CPU0C IREF VSSA VDDA SCLK SDATA PD#/VTTPWRGD* VSSAGP AGP0 AGP1 VDDAGP VDD48M 48M 24_48M/MULT0* VSS48M 48 pin SSOP Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors. Cypress Semiconductor Corporation Document #: 38-07373 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 27, 2002 CY28370 Table 1. Frequency Table FS(4:0) CPU (MHz) SDRAM (MHz) ZCLK (MHz) AGP (MHz PCI (MHz) VCO (MHz) 00000 66.67 66.67 66.67 66.67 33.33 400.00 00001 100.00 133.33 66.67 66.67 33.33 400.00 00010 111.11 166.67 66.67 66.67 33.33 666.66 00011 100.00 200.00 66.67 66.67 33.33 400.00 00100 100.00 100.00 133.33 66.67 33.33 400.00 00101 133.90 133.90 133.90 66.95 33.48 669.50 00110 133.33 166.67 133.33 66.67 33.33 666.66 00111 133.33 200.00 133.33 66.67 33.33 400.00 01000 100.00 166.67 125.00 62.50 31.25 500.00 01001 100.00 133.33 133.33 66.67 33.33 400.00 01010 111.11 166.67 133.33 66.67 33.33 666.66 01011 100.00 200.00 133.33 66.67 33.33 400.00 01100 100.60 134.13 100.60 67.07 33.53 402.40 01101 133.33 133.33 100.00 66.67 33.33 400.00 01110 100.00 166.67 100.00 71.43 35.71 500.00 01111 133.33 166.67 111.11 66.67 33.33 666.66 10000 125.00 125.00 100.00 71.43 35.71 500.00 10001 150.00 150.00 120.00 66.67 33.33 600.00 10010 140.00 140.00 140.00 70.00 35.00 560.00 10011 166.67 166.67 133.33 66.67 33.33 666.66 10100 100.00 100.00 66.67 66.67 33.33 400.00 10101 133.33 133.33 95.24 66.67 33.33 666.66 10110 133.33 166.67 95.24 66.67 33.33 666.66 10111 133.33 200.00 100.00 66.67 33.33 400.00 11000 111.11 133.33 133.33 66.67 33.33 666.66 11001 125.00 166.67 166.67 62.50 31.25 500.00 11010 105.00 140.00 140.00 60.00 30.00 420.00 11011 120.00 150.00 150.00 66.67 33.33 600.00 11100 133.33 133.33 133.33 57.14 28.57 400.00 11101 100.00 133.33 133.33 50.00 25.00 400.00 11110 180.00 135.00 135.00 60.00 30.00 540.00 11111 160.00 213.33 128.00 64.00 32.00 640.00 Pin Description [2] Pin Name 6 XIN 7 XOUT PWR VDDR I/O Description I Oscillator Buffer Input. Connect to a crystal or to an external clock. O Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. 40,44 CPU(0:1)T VDDC O “True” host output clocks. See Table 1 for frequencies and functionality. 39,43 CPU(0:1)C VDDC O “Complementary” host output clocks. See Table 1 for frequencies and functionality. 16,17,20,23 PCI (0:5) VDDP O PCI Clock Outputs. See Table 1. 14 FS3/PCI_F0 VDDP I/O PD Document #: 38-07373 Rev. *B Power-on bidirectional input/output. At power-up, FS3 is the input. When VTTPWRGD transitions to a logic HIGH, FS3 state is latched and this pin becomes PCI_F0 Clock Output. See Table 1. Page 2 of 19 CY28370 Pin Description (continued)[2] Pin Name PWR I/O Description 15 FS4/PCI_F1 VDDP I/O PD Power-on bidirectional input/output. At power-up, FS4 is the input. When VTTPWRGD transitions to a logic HIGH, FS4 state is latched and this pin becomes PCI_F1 Clock Output. See Table 1. 2 FS0/REF0 VDDR I/O PD Power-on bidirectional input/output. At power-up, FS0 is the input. When VTTPWRGD transitions to a logic HIGH, FS0 state is latched and this pin becomes REF0, buffered Output copy of the device’s XIN clock. 3 FS1/REF1 VDDR I/O PD Power-on bidirectional input/output. At power-up, FS1 is the input. When VTTPWRGD is transited to logic LOW, FS1 state is latched and this pin becomes REF1, buffered Output copy of the device’s XIN clock. 4 FS2/REF2 VDDR I/O PD Power-on bidirectional input/output. At power-up, FS2 is the input. When VTTPWRGD is transited to logic LOW, FS2 state is latched and this pin becomes REF2, buffered Output copy of the device’s XIN clock. 38 IREF I 33 PD#/VTTPRGD I PU 27 26 48M VDD48M 24_48M/MULT0 VDD48M 9,10 ZCLK (0:1) 34 SDATA VDDZ O I/O PU Current reference programming input for CPU buffers. A resistor is connected between this pin and VSS. See Figure 2. Power-down Input/VTT Power Good Input. At power-up, VTTPWRGD is the input. When this input is transitions initially from LOW to HIGH, the FS (0:4) and MULT0 are latched. After the first LOW-to-HIGH transition, this pin become a PD# input with an internal pull-up. When PD# is asserted LOW, the device enters power-down mode. See power management function. Fixed 48-MHz USB Clock Output Power-on bidirectional input/output. At power-up, MULT0 is the input. When VTTPWRGD is transited to logic LOW, MULT0 state is latched and this pin becomes 24_48M, SIO programmable clock output. O HyperZip Clock Outputs. See Table 1. I/O Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. 35 SCLK I Serial Clock Input. Conforms to the SMBus specification. 12 SRESET# O PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an SRESET# open drain output, and the internal pulled up is not active. See system reset description. PCI_STP# I PU System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin becomes PCI Clock Disable Input. When PCI_STP# is asserted low, PCI (0:5) clocks are synchronously disabled in a low state. This pin does not affect PCI_F (0:1) if they are programmed to be free-running clocks via the device’s SMBus interface. CPU_STP# I PU CPU Clock Disable Input. When asserted low, CPU (0:1)T clocks are synchronously disabled in a high state and CPU (0:1)C clocks are synchronously disabled in a low state. 45 47 SDCLK VDDSD O SDRAM Clock Output. 30,31 AGP (0:1) VDDAGP O AGP clock outputs. See Table 1 for frequencies and functionality. 48 VDDSD 29 VDDAGP PWR 3.3V power supply for SDRAM clock outputs. PWR 3.3V power supply for AGP clock outputs. 11 VDDZ PWR 3.3V power supply for HyperZip clock outputs. 1 VDDR PWR 3.3V power supply for REF clock outputs. 13,19 VDDP PWR 3.3V power supply for PCI clock outputs. 42 VDDC PWR 3.3V power supply for CPU clock outputs. 28 VDD48M 36 VDDA PWR 3.3V analog power supply. 18,24 VSSP PWR GND for PCI clock outputs. 41 VSSC PWR GND for CPU clock outputs. Document #: 38-07373 Rev. *B PWR 3.3V power supply for 48-MHz/24-MHz clock outputs. Page 3 of 19 CY28370 Pin Description (continued)[2] Pin Name 8 VSSZ 25 VSS48M 5 VSSR 46 VSSSD 32 VSSAGP 37 VSSA PWR I/O Description PWR GND for HyperZip clock outputs. PWR GND for 48-MHz/24-MHz clock outputs. PWR GND for REF clock outputs. PWR GND for SDRAM clock outputs. PWR GND for AGP clock outputs. PWR GND for analog. Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the controller. For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The Block Write and Block Read protocol is outlined in Table 3 while Table 4 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 Description 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation (6:0) Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be “0000000” Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Block Read Protocol Bit 1 2:8 9 Write 9 10 Acknowledge from slave 10 11:18 19 20:27 28 29:36 37 38:45 46 Command Code – 8-bit “00000000” stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave 11:18 Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8-bit “00000000” stands for block operation 19 Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits Data byte 0 – 8 bits 28 Read Acknowledge from slave 29 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave .... Data Byte N/Slave Acknowledge... .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop 30:37 38 39:46 47 48:55 Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge Note: 2. PU = internal pull-up. PD = internal pull-down. T = three-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH => 2.0V. Document #: 38-07373 Rev. *B Page 4 of 19 CY28370 Table 3. Block Read and Block Write Protocol (continued) .... Data byte N from slave – 8 bits .... Not acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Description Start Byte Read Protocol Bit 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave Command Code – 8 bits “1xxxxxxx” stands for byte 11:18 operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 20:27 Byte Count – 8 bits 28 Acknowledge from slave 29 Stop Command Code – 8 bits “1xxxxxxx” stands for byte 11:18 operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not acknowledge 39 Stop Since SDR and DDR Zero Delay Buffers will share this same address this device starts from Byte 4. Byte 4: CPU Clock Register Bit @Pup Pin# Name Description 7 H/W Setting 14 FS3 For selecting frequencies in Table 1. 6 H/W Setting 4 FS2 For selecting frequencies in Table 1. 5 H/W Setting 3 FS1 For selecting frequencies in Table 1. 4 H/W Setting 2 FS0 For selecting frequencies inTable 1. 3 0 2 H/W Setting 1 1 0 0 If this bit is programmed to a “1,” it enables Writes to bits (7:4, 2) for selecting the frequency via software (SMBus). If this bit is programmed to a “0,” it enables only Reads of bits (7:4, 2) that reflect the hardware setting of FS(0:4). 15 FS4 SSCG For selecting frequencies in Table 1. Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. Master Output Control. 0 = running, 1 = three-state all outputs. Byte 5: CPU Clock Register (All bits are read-only) Bit 7 @Pup 0 Pin# Name Description Reserved 6 0 5 X 26 MULT0 Reserved 4 X 15 FS4 FS4 read back. This bit is read-only. 3 X 14 FS3 FS3 read back. This bit is read-only. 2 X 4 FS2 FS2 read back. This bit is read-only. 1 X 3 FS1 FS1 read back. This bit is read-only. 0 X 2 FS0 FS0 read back. This bit is read-only. Document #: 38-07373 Rev. *B MULT0 (pin 26) Value. This bit is read-only Page 5 of 19 CY28370 Byte 6: CPU Clock Register Bit @Pup Pin# Name Description 7 0 Function Test Bit, always program to 0. 6 0 Reserved 5 0 14 PCI_F0 PCI_STP# control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. 4 0 15 PCI_F1 PCI_STP# control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. 3 1 40,39 Controls CPU0T and CPU0C functionality when CPU_STP# is asserted LOW CPU0T/C 0 = Free Running, 1 + Stopped with CPU_STP# asserted LOW This is a Read and Write Control bit. 2 0 44,43 Controls CPU1T and CPU1C functionality when CPU_STP# is asserted LOW CPU1T/C 0 = Free Running, 1 Stopped with CPU_STP# asserted to LOW This and Read and Write Control bit. 1 1 40,39 CPU0T/C CPU0T, CPU0C Output Control, 1 = enabled, 0 = disabled. This is a Read and Write Control bit. 0 1 44,43 CPU1T/C CPU1T, CPU1C Output Control, 1 = enabled, 0 = disabled. This is a Read and Write Control bit. Byte 7: PCI Clock Register Bit @Pup Pin# Name Description 7 1 14 PCI_F0 PCI_F0 Output Control 1 = enabled, 0 = forced LOW. 6 1 15 PCI_F1 PCI_F1 Output Control 1 = enabled, 0 = forced LOW. 5 1 23 PCI5 PCI5 Output Control 1 = enabled, 0 = forced LOW. 4 1 22 PCI4 PCI4 Output Control 1 = enabled, 0 = forced LOW. 3 1 21 PCI3 PCI3 Output Control 1 = enabled, 0 = forced LOW. 2 1 20 PCI2 PCI2 Output Control 1 = enabled, 0 = forced LOW. 1 1 17 PCI1 PCI1 Output Control 1 = enabled, 0 = forced LOW. 0 1 16 PCI0 PCI0 Output Control 1 = enabled, 0 = forced LOW. Byte 8: Silicon Signature Register Bit @Pup 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Description Vendor ID 1000 = Cypress Revision ID Byte 9: Peripheral Control Register Bit @Pup Pin# Name 33 PD# Description 7 1 PD# Enable. 0 = enable, 1 = disable. 6 0 5 1 27 48M 4 1 26 48M_24M 48M_24M Output Control 1 = enabled, 0 = forced LOW. 3 0 26 48M_24M 48M_24M, 0 = pin28 output is 24 MHz, 1 = pin28 output is 48 MHz. 2 0 SS2 SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread). 1 0 SS1 SS1 Spread Spectrum control bit. See Table 9. 0 0 SS0 SS0 Spread Spectrum control bit. See Table 9. 39,40,43, PD# output 0 = when PD# is asserted LOW, CPU(0:1)T stop in a HIGH state, CPU(0:1)C stop in a 44 control LOW state. 1 = when PD# is asserted LOW, CPU(0:1)T and CPU(0:1)C stop in H-Z. Document #: 38-07373 Rev. *B 48M Output Control 1 = enabled, 0 = forced LOW. Page 6 of 19 CY28370 Byte 10: Peripheral Control Register Bit @Pup Pin# Name Description 7 1 47 SDCLK 6 1 4 REF2 REF2 Output Control 1 = enabled, 0 = forced LOW. 5 1 3 REF1 REF1 Output Control 1 = enabled, 0 = forced LOW. 4 1 2 REF0 REF0 Output Control 1 = enabled, 0 = forced LOW. 3 1 10 ZCLK1 ZCLK1 Output Enable 1 = enabled, 0 = disabled. 2 1 9 ZCLK0 ZCLK0 Output Enabled 1 = enabled, 0 = disabled. SDCLK Output Enable 1 = enabled, 0 = disabled. 1 1 30 AGP1 AGP1 Output Enabled 1 = enabled, 0 = disabled. 0 1 31 AGP0 AGP0 Output Enabled 1 = enabled, 0 = disabled. Byte 11: Dial-a-Skew™ and Dial-a-Ratio™ Control Register Bit @Pup Name Description 7 0 6 0 DARSD2 Programming these bits allows modifying the frequency ratio of the SDCLK clock relative to the DARSD1 VCO. See Table 5. 5 0 DARSD0 4 0 3 0 DARAG2 Programming these bits allows modifying the frequency ratio of the AGP(1:0), PCI(5:0) and DARAG1 PCIF(0:1) clocks relative to the VCO. See Table 6. 2 0 DARAG0 1 0 DASSD1 Programming these bits allows shifting skew between CPU and SDCLK signals. See Table 7. 0 0 DASSD0 Table 5. Dial-a-Ratio SDCLK DARSD(2:0) VC0/SDCLK Ratio 000 Frequency Selection Default 001 2 010 3 011 4 100 5 101 6 110 8 111 9 Table 6. Dial-a-Ratio AGP(0:1)[3] DARAG(2:0) VC0/AGP Ratio 000 Frequency Selection Default 001 6 010 7 011 8 100 9 101 10 110 10 111 10 Notes: 3. The ratio of AGP to PCI is retained at 2:1. 4. See Figure 2 for CPU measurement point. See Figure 3 for SDCLK measurement point. Document #: 38-07373 Rev. *B Page 7 of 19 CY28370 Table 7. Dial-a-Skew SDCLK CPU DASSD(1:0) SDCLK-CPU Skew 00 0 ps (Default)[4] 01 +150 ps (CPU lag)* 10 +300 ps (CPU lag)* 11 +450 ps (CPU lag)* Byte 12: Watchdog Time Stamp Register Bit @Pup Name 7 1 SRESET#/PCI_STP#. 1 = Pin 12 is the input pin as PCI_STP# signal. 0 = Pin 12 is the output pin as SRESET# signal. 6 0 Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = selects frequency of existing H/W setting1 = selects frequency of the second to last S/W setting. (the software setting prior to the one that caused a system reboot). 5 0 WDTEST. For WD-Test, ALWAYS program to ’0.’ 4 0 WD Alarm. This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears the WD time stamps (WD3:0). 3 0 WD3 2 0 WD2 1 0 WD1 0 0 WD0 Description This bits selects the Watchdog Time Stamp Value. See Table 8. Table 8. Watchdog Time Stamp Table WD(3:0) Function 0000 Off 0001 1 second 0010 2 seconds 0011 3 seconds 0100 4 seconds 0101 5 seconds 0110 6 seconds 0111 7 seconds 1000 8 seconds 1001 9 seconds 1010 10 seconds 1011 11 seconds 1100 12 seconds 1101 13 seconds 1110 14 seconds 1111 15 seconds Byte 13: Dial-a-Frequency™ Control Register N (All bits are read and write functional)[5] Bit 7 @Pup 0 Reserved Description 6 0 N6, MSB 5 0 N5 4 0 N4 3 0 N3 Note: 5. Byte 13 and Byte 14 should be written together in every case. Document #: 38-07373 Rev. *B Page 8 of 19 CY28370 Byte 13: Dial-a-Frequency™ Control Register N (All bits are read and write functional)[5] (continued) Bit 2 @Pup 0 Description N2 1 0 N3 0 0 N0, LSB Byte 14: Dial-a-Frequency Control Register R (All bits are read and write functional)[5] Bit @Pup 7 0 Reserved Description 6 0 R5 MSB 5 0 R4 4 0 R3 3 0 R2 2 0 R1 1 0 R0, LSB 0 0 R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from the DAF registers into R and N. Dial-a-Frequency Feature SMBus Dial-a-Frequency feature is available in this device via Byte13 and Byte14. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (FS4, FS0). P value may be determined from the following table. FS(4:0) P 00111, 01101, 10111, 11100, 11110 127995867 00001, 00011, 00100, 01001, 01011, 01100, 10000, 10001, 10010, 10011, 10100, 11001, 11010, 11101, 11111 95996900 00101, 00110, 01000, 00111, 01110, 01111, 10101, 10110, 10010, 11011 76797520 0000, 00010, 01010, 11000 63997933 Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by Table 9. Spread Spectrum a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. See the SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down –0.50 0 0 1 Down –0.75 0 1 0 Down –1.00 0 1 1 Down –1.50 1 0 0 Center +0.25, –0.25 1 0 1 Center +0.37, –0.37 1 1 0 Center +0.50, –0.50 1 1 1 Center +0.75, –0.75 Document #: 38-07373 Rev. *B Page 9 of 19 CY28370 System Self Recovery Clock Management This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. The watchdog timer is triggered whenever a frequency change or output divided change occurs. The system BIOS first needs to enable the watchdog time out value through I2C and then change the target frequency. After waiting for the clock to reach its final frequency, the BIOS should then disable a watchdog timer. If the system is not operating then the watchdog times out and generates a reset pulse, the width of which is programmed in the Watchdog Timer Register. RESET W ATCHDOG TIMER Set WD(0:3) Bits = 0 INITIALIZE W ATCHDOG TIMER Set Frequency Revert Bit Set WD(0:3) = (# of Sec ) x 2 SET SOFTW ARE FSEL Set SW Freq_Sel = 1 Set FS(0:4) SET DIAL-A-FREQUENCY Load M and N Registers Set Pro_Freq_EN = 1 SET DIAL-A-RATIO Select a different divider ratio Wait for 6msec For Clock Output to Ramp to Target Frequency N Hang? CLEAR W D Set WD(0:3) Bits = 0 Exit Y W ATCHDOG TIMEOUT Frequency Revert Bit = 1 Set Frequency to FS_SW Frequency Revert Bit = 0 Set Frequency to FS_HW_Latched Set SRESET# = 0 for 6 msec Reset Figure 1. Watchdog Flowchart Table 10. Group Timing Relationship and Tolerances Offset Tolerance (or Range) Conditions Notes CPU to SDCLK Typical 0 ns ± 2 ns CPU leads 6 CPU to AGP Typical 2 ns 1–4 ns CPU leads 6 CPU to ZCLK Typical 2 ns 1–4 ns CPU leads 6 CPU to PCI Typical 2 ns 1–4 ns CPU leads 6 Note: 6. See Figure 2 for CPU clock measurement point. SeeFigure 3 for SDCLK, AGP, ZCLK, and PCI Outputs measurement point. Document #: 38-07373 Rev. *B Page 10 of 19 CY28370 Table 11. CPU Clock Current Select Function Mult0 Reference R, Iref – VDD (3*Rr) Output Current VOH @ Z 0 50 Ohms (not used) Board Target Trace/Term Z Rr = 221 1%, Iref = 5.00 mA IOH = 4*Iref 1.0V @ 50 1 50 Ohms Rr = 475 1%, Iref = 2.32 mA IOH = 6*Iref 0.7V @ 50 Table 12. Maximum Lumped Capacitive Output Loads Clock PCI(0:5), PCI_F(0:1) Max. Load Units 30 pF AGP(0:1), SDCLK 30 pF ZCLK 10 pF 48M_24, 48M Clock 20 pF REF(0:2) 30 pF CPU(0:1)T, CPU(0:1)C 2 pF For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. T PCB 33Ω Measurem ent Point CPUT 49.9Ω 2pF MULTSEL 33Ω T PCB Measurem ent Point CPUC 49.9Ω 2pF IREF 475Ω Figure 2. 0.7V Configuration O u tp u t u n d e r T e s t P ro b e 3 .3 V s ig n a ls Load C ap tD C - - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V Tr Tf Figure 3. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement) Document #: 38-07373 Rev. *B Page 11 of 19 CY28370 CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# Assertion When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPU clock edges. The final state of the stopped CPU signals is CPU = HIGH and CPU0# = LOW. There is no change to the output drive current values during the stopped state. The CPU is driven HIGH with a current value equal to (Mult 0 “select”) × (Iref), and the CPU# signal will not be driven. Due to external pull-down circuitry CPU# will be LOW during this stopped state. CPU_STP# CPUT CPUC Figure 4. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CPU_STP# CPUT CPUC CPUT CPUC Figure 5. CPU_STP# Deassertion Waveform Document #: 38-07373 Rev. *B Page 12 of 19 CY28370 PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see Figure 6). The PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free-running. t setup PCI_STP# PCI_F(0:2) 33M PCI(0:6) 33M Figure 6. PCI_STP# Assertion Waveform PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level. t setup PCI_STP# PCI_F(0:2) PCI(0:6) Figure 7. PCI_STP# Deassertion Waveform[7] PD# (Power-down) Clarification PD#–Assertion (Transition from logic “l” to logic “0”) The PD# (power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low “stopped” state. When PD# is sampled LOW by two consecutive rising edges of CPUC clock, all clock outputs (except CPUT) clocks must be held LOW on their next HIGH to LOW transition. CPUT clocks must be hold with CPUT clock pin driven HIGH with a value of 2x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# Deassertion (transition from logic “0” to logic “l”) The power-up latency between PD# rising to a valid logic “1” level and the starting of all clocks is less than 3.0 ms. Note: 7. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin 34 and the other is SMBus Byte 0 Bit 3. These two inputs are logically ANDed. If either the external pin or the internal SMBus register bit is set low, the stoppable PCI clocks will be stopped in a logic LOW state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW, thereby indicating that the device’s stoppable PCI clocks are not running. Document #: 38-07373 Rev. *B Page 13 of 19 CY28370 CPU_STP# CPU(0:1)T CPU(0:1)C CPU Internal CPU# Internal Figure 8. Power-down Assertion/Deassertion Timing Waveforms–Nonbuffered Mode VID (0:3), SEL (0,1) VTTPWRGD PWRGD 0.2-0.3mS Delay VDD Clock Gen Clock State Clock Outputs Clock VCO State 0 Wait for VTT_GD# Sample Sels State 1 State 2 Off State 3 On (Note A) On Off TP W = H RG igh D Figure 9. VTTPWRGD Timing Diagram[8] VT S1 D ela y 0 .2 5m S S2 S a m ple Inpu ts F S (3 :0 ) W a it for 1 .1 46 m s E nab le O u tp uts V D D A = 2.0V S0 P ow er O ff S3 V D D 3.3 = O ff N orm a l O pe ratio n Figure 10. Clock Generator Power-up/Run State Diagram Note: 8. Device is not affected, VTTPWRGD is ignored. Document #: 38-07373 Rev. *B Page 14 of 19 CY28370 Maximum Ratings[9] Input Voltage Relative to VSS:.............................. VSS – 0.3V Operating Temperature:.................................... 0°C to +70°C Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Maximum Power Supply:................................................ 3.5V Storage Temperature: ................................–65°C to + 150°C AC Parameters 100 MHz Parameter Description Crystal TDC Xin Duty Cycle TPeriod Xin Period 133 MHz Min. Max. Min. Max. Unit Notes 47.5 52.5 47.5 52.5 % 10,17 69.841 71.0 69.841 71.0 ns 10,11,13,1 7 VHIGH Xin High Voltage 0.7Vdd Vdd 0.7Vdd Vdd Volts VLOW Xin Low Voltage 0 0.3Vdd 0 0.3Vdd Volts Tr / Tf Xin Rise and Fall Times 10.0 10.0 ns TCCJ Xin Cycle to Cycle Jitter 500 500 ps 11,14,17 CPU at 0.7V Timing TSKEW Any CPU to CPU Clock Skew 150 150 ps 14, 20, 24 TCCJ CPU Cycle to Cycle Jitter 150 150 ps 14, 20, 24 TDC CPU and CPUC Duty Cycle 45 55 45 55 % 14, 20, 24 TPeriod CPU and CPUC Period 9.8 10.2 7.35 7.65 ns 14, 20, 24 CPU and CPUC Rise and Fall Times 175 700 175 700 ps Tr / Tf Rise/Fall Matching 20% 20% 14, 15 15, 23, 24 DeltaTr Rise Time Variation 125 125 ps 15, 24 DeltaTf Fall Time Variation 125 125 ps 15, 24 Vcross Crossing Point Voltage at 0.7V Swing 280 430 280 430 mV 15,20, 24 AGP TDC AGP Duty Cycle 45 55 45 55 % 11, 13 TPeriod AGP Period 15.0 15.3 15.0 15.3 ns 11, 13 THIGH AGP High Time 5.25 – 5.25 ns 21 TLOW AGP Low Time 5.05 – 5.05 Tr / Tf AGP Rise and Fall Times 0.5 1.6 0.5 Tskew Unbuffered Any AGP to Any AGP Clock Skew TCCJ AGP Cycle to Cycle Jitter ZCLK TDC ZCLK(0:1) Duty Cycle 45 55 45 55 % 11, 13 Tr / Tf ZCLK(0:1) Rise and Fall Times 0.5 1.6 0.5 1.6 ns 11, 12 ns 22 1.6 ns 11, 12 175 175 ps 11, 13 250 250 ps 11, 13 TSKEW Any ZCLK(0:1) to Any ZCLK(0:1) Skew 175 175 ps 11, 13 TCCJ ZCLK(0:1) Cycle to Cycle Jitter 250 250 ps 11,13 PCI TDC PCI_F(0:1) PCI (0:5) Duty Cycle TPeriod PCI_F(0:1) PCI (0:5) Period 45 55 30.0 45 55 30.0 % 11, 13 nS 10,11,13 THIGH PCI_F(0:1) PCI (0:5) High Time 12.0 12.0 nS 21 TLOW PCI_F(0:1) PCI (0:5) Low Time 12.0 12.0 nS 22 Tr / Tf PCI_F(0:1) PCI (0:5) Rise and Fall Times 0.5 2.0 nS 11, 12 TSKEW Any PCI Clock to Any PCI Clock Skew 500 500 pS 11, 13 TCCJ PCI_F(0:1) PCI (0:5) Cycle to Cycle Jitter 250 250 ps 11, 13 Document #: 38-07373 Rev. *B 2.0 0.5 Page 15 of 19 CY28370 AC Parameters (continued) 100 MHz Parameter Description Min. 133 MHz Max. Min. Max. Unit Notes SDCLK TDC SDCLK Duty Cycle 45 55 45 55 % 11, 13 TPeriod SDCLK Period 7.4 15 7.4 15 ns 11, 13 THIGH SDCLK High Time 3.0 1.87 ns 21 TLOW SDCLK Low Time 2.8 1.67 ns 22 Tr / Tf SDCLK Rise and Fall Times 0.4 1.6 0.4 1.6 ns 11, 12 TCCJ SDCLK Cycle to Cycle Jitter – 250 – 250 ps 11, 12 48M TDC 48M Duty Cycle TPeriod 48M Period Tr / Tf 48M Rise and Fall Times TCCJ 48M Cycle to Cycle Jitter 24M TDC 24 MHz Duty Cycle TPeriod 24 MHz Period Tr / Tf 24 MHz Rise and Fall Times TCCJ 24 MHz Cycle to Cycle Jitter REF TDC REF Duty Cycle TPeriod REF Period Tr / Tf REF Rise and Fall Times TCCJ REF Cycle to Cycle Jitter 45 55 45 55 % 11, 13 20.829 20.834 20.829 20.834 ns 11, 13 2.0 1.0 2.0 ns 11, 12 350 ps 11, 13 1.0 350 45 55 45 55 % 11, 13 41.66 41.67 41.66 41.67 ns 11, 13 4.0 1.0 4.0 ns 11, 12 500 ps 11, 13 1.0 500 45 55 45 55 % 11, 13 69.8413 71.0 69.8413 71.0 ns 11, 13 4.0 1.0 1.0 1000 4.0 ns 11, 12 1000 ps 11, 13 Enable/Disable and Set-up tpZL, tpZH Output Enable Delay (all outputs) 1.0 10.0 1.0 10.0 ns tpLZ, tpZH 1.0 10.0 1.0 10.0 ns 1.5 ms Output Disable Delay (all outputs) tstable All Clock Stabilization from power-up tss Stopclock Set-up Time tsh Stopclock Hold Time 1.5 10.0 10.0 ns 0 0 ns 16 DC Characteristics Current Accuracy Load Min. Max. Iout VDD = nominal (3.30V) M0 = 0 or 1 and Rr shown in table Conditions Configuration Nominal test load for given configuration –7% Inom[25] +7% Inom Iout VDD = 3.30 ±5% Nominal test load for given configuration –12% Inom +12% Inom All combinations of M0 or 1 and Rr shown in table Document #: 38-07373 Rev. *B Page 16 of 19 CY28370 Current Accuracy Notes: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required. 10. This parameter is measured as an average over 1-us duration with a crystal center frequency of 14.318 MHz. 11. All outputs loaded per Table 1. 12. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data sheet). 13. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement setup section of this data sheet). 14. This measurement is applicable with Spread On or Spread OFF. 15. Measured from VOL = 0.175 to VOH = 0.525V. 16. CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge. 17. When Xin is driven from an external clock source. 18. When Crystal meets minimum 40 ohm device series resistance specification. 19. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 20. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0V. 21. THIGH is measured at 2.4V for all non host outputs. 22. TLOW is measured at 0.4V for all non host outputs. 23. Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall). 24. For CPU load. See Figure 2. 25. Inom refers to the expected current based on the configuration of the device. DC Component Parameters (VDD = 3.3V ± 5%, TA = 0°C to 70°C Parameter Idd3.3V Description Dynamic Supply Current Conditions Min. Typ. All frequencies at maximum values[26] Max. Unit 300 mA Ipd3.3V Power-down Supply Current PD# Asserted Note 27 mA Cin Input Pin Capacitance 5 pF Cout Output Pin Capacitance 6 pF Lpin Pin Inductance 7 nH Cxtal Crystal Pin Capacitance 42 pF Measured from the Xin or Xout pin to Ground 30 36 Notes: Ordering Information Part Number Package Type Product Flow CY28370OC 48-pin Shrunk Small Outline Package (SSOP) Commercial, 0° to 70°C CY28370OCT 48-pin Shrunk Small Outline Package (SSOP)–Tape and Reel Commercial, 0° to 70°C Document #: 38-07373 Rev. *B Page 17 of 19 CY28370 Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 51-85061-C Pentium 4 is a registered trademark of Intel Corporation. Dial-a-Frequency, Dial-a-Ratio, and Dial-a-dB are trademarks of Cypress Semiconductor. Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names mentioned in this document are the trademarks of their respective holders. Notes: 26. All outputs loaded as per maximum capacitive load table. 27. Absolute value = (programmed CPU Iref) +10 mA. Document #: 38-07373 Rev. *B Page 18 of 19 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28370 Document History Page Document Title: CY28370 High-performance SiS645/650/660 Pentium 4 Clock Synthesizer Document Number: 38-07373 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 112789 05/07/02 DMG New Data Sheet *A 118704 10/15/02 RGL Add SiS660 to the current title *B 122913 12/27/02 RBI Add power up requirements to maximum ratings information. Document #: 38-07373 Rev. *B Page 19 of 19