Circuit Note CN-0294 Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0294. Devices Connected/Referenced Fractional-N PLL Synthesizer with ADF4351 Integrated VCO Clock Fanout Buffer with 8 LVPECL ADCLK948 Outputs Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION AND BENEFITS Circuit Evaluation Boards ADF4351 Evaluation Board (EVAL-ADF4351EB1Z) ADCLK948 Evaluation Board (ADCLK948/PCBZ) Design and Integration Files Schematics, Layout Files, Bill of Materials Many systems require low jitter multiple system clocks for mixed signal processing and timing. The circuit shown in Figure 1 interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to the ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of the ADF4351. 3.3V LVPECL ADCLK948 3.3V Q0 Q0 1µF Q1 3.3V VVCO VDD 16 17 VVCO 28 4 10 26 Q1 6 Q2 32 Q2 DVDD AVDD CE PDB RF VP SDV DD 1nF 1nF FREF IN 29 REF IN RFOUTB+ 14 51Ω Q3 VVCO RFOUTB– 15 1 CLK 2 DATA ZBIAS ZBIAS SPI-COMPATIBLE SERIAL BUS 3 LE 1nF ADF4351 VREF0 3.3V 100Ω Q3 100Ω Q4 VT0 Q4 RFOUTA+ 12 CLK0 Q5 RFOUTA– 13 22 RSET REFERENCE 1nF 4.7kΩ 100Ω VTUNE 20 180Ω CPOUT 7 100Ω CLK0 VT1 Q5 CLK1 Q6 CLK1 Q6 330nF 22nF SW 5 CPGND SDGND AGND AGNDVCO 8 31 9 11 18 21 DGND 10nF 82Ω Q7 IN_SEL Q7 27 REFERENCE 10989-001 VREF1 Figure 1. ADF4351 PLL Connected to ADCLK948 Fanout Buffer (Simplified Schematic: All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. CN-0294 Circuit Note Modern digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. Extra buffering may be required to guarantee accurate distribution to other circuit components without loss of integrity. The interface between the ADF4351clock source ADCLK948 clock fanout buffer is described, and measurements show that the additive jitter associated with the clock fanout buffer is 75 fs rms. CIRCUIT DESCRIPTION The ADF4351 is a wideband PLL and VCO consisting of three separate multiband VCOs. Each VCO covers a range of approximately 700 MHz (with some overlap between the frequencies of the VCO). This permits a fundamental VCO frequency range of between 2.2 GHz to 4.4 GHz. Frequencies lower than 2.2 GHz can be generated using internal dividers within the ADF4351. Equipment Needed The following equipment is needed: • • • • • • • • For clock generation, the ADF4351 PLL and VCO must be enabled, and the desired output frequency must be programmed. The output frequency of the ADF4351 is available at the opencollector outputs at the RFOUT pins, which require a shunt inductor (or resistor), plus a dc blocking capacitor. The ADCLK948 is a SiGe low jitter clock fanout buffer that is ideally suited for use with the ADF4351, because its maximum input frequency (4.5 GHz) is just above that of the ADF4351 (4.4 GHz). Broadband rms additive jitter is 75 fs. The EVAL-ADF4351EB1Z evaluation board kit with programming software The ADCLK948PCBZ evaluation board A 3.3 V power supply Two cables to connect the 3.3 V supply to the ADCLK948PCBZ Two short equal length SMA coaxial cables A high speed oscilloscope (2 GHz bandwidth) or an equivalent The R&S FSUP26 spectrum analyzer or an equivalent A PC with Windows® XP, Windows, Vista (32-bit), or Windows 7 (32-bit) The SMA coaxial cable is required to connect the RFOUTA+ and RFOUTA− pins of the EVAL-ADF4351EB1Z to CLK0 and CLK0 pins of the ADCLK948PCBZ. Functional Block Diagram For this experiment, the ADCLK948PCBZ and the EVALADF4351EB1Z are used. The boards are connected via a SMA cable to the ADCLK948PCBZ, as shown in Figure 1. POWER SUPPLY It is necessary to add a dc common-mode bias level of 1.65 V to the CLK inputs of the ADCLK948 to mimic LVPECL logic levels. This is accomplished by the use of a resistor bias network. Omission of the dc bias circuit results in degraded signal integrity at the ADCLK948 outputs. 3.3V COM T7 RFOUTA+ ADF4351 EVALUATION BOARD (EVAL-ADF4351EB1Z) CLK0 J4 RFOUTA− CLK0 ADCLK948/PCBZ EVALUATION BOARD J2 COMMON VARIATIONS OUT2 USB Other possible clock fanout buffers in the same family as the ADCLK948 are the ADCLK946 (6 LVPECL outputs), ADCLK950 (10 LVPECL outputs), and the ADCLK954 (12 LVPECL outputs). PC OUT2 HIGH-SPEED OSCILLOSCOPE R&S RTO1024 10989-002 Other possible synthesizers with integrated VCOs are the ADF4350 fractional N (137 MHz to 4400 MHz) and the ADF4360 integer N series. Figure 2. ADF4351 Logic Level Measurement Setup Getting Started CIRCUIT EVALUATION AND TEST The circuit is evaluated using the EVAL-ADF4351EB1Z board for a clock source, with some minor modifications. The EVALADF4351EB1Z board uses the standard ADF4351 programming software contained on the CD that accompanies the evaluation board. The ADCLK948/PCBZ is also required and can be used out of the box without modification. The UG-435 user guide details the installation and use of the EVAL-ADF4351EB1Z evaluation software. UG-435 also contains board setup instructions and the board schematic, layout, and bill of materials. Necessary modifications to the board are the insertion of 100 Ω resistors after the dc blocking capacitor. The resistors are connected to 3.3 V and to GND. This should be done to both the RFOUTA+ and RFOUTA− pins to provide a common-mode voltage of 1.65 V (above the minimum required 1.5 V). This may necessitate scraping off the solder mask near these transmission lines. The UG-068 user guide contains similar information relevant to the operation of the ADCLK948/PCBZ evaluation board Rev. 0 | Page 2 of 5 Circuit Note CN-0294 Logic Level Measurement 3. In this example, the Rohde & Schwarz RTO1024 oscilloscope is used together with two RT-ZS30 active probes to accurately measure the high speed logic levels. Install the ADF435x software to PC by doing the following: 10989-003 2. Connect the EVAL-ADF4351EB1Z to the PC, follow the hardware driver instructions as per UG-435. Program the ADF4351 PLL as per the screenshot of the ADF435x software (see Figure 3). In this example, an RF frequency of 1 GHz is chosen. Figure 3. ADF4351 Software Settings 10989-004 1. 4. Using two equal length short SMA cables, connect the RFOUTA+ and RFOUTA− SMA connectors from the EVALADF4351EB1Z board to the CLK0/CLK0 SMA connectors of the ADCLK948/PCBZ board. Connect the differential output OUT2/OUT2 of the ADCLK948/PCBZ to the high speed oscilloscope. See Figure 4 for typical waveforms for a 1 GHz output. Figure 4. ADCLK948 Oscilloscope Output for 1 GHz Logic Signal, Horizontal Axis: 200 ps/DIV, Vertical Axis: 200 mV/DIV Rev. 0 | Page 3 of 5 CN-0294 Circuit Note Phase Noise and Jitter Measurement 3. 4. 3.3V COM T7 RFOUTA+ CLK0 J4 ADF4351 EVALUATION BOARD (EVAL-ADF4351EB1Z) RFOUTA− ADCLK948/PCBZ EVALUATION BOARD CLK0 J2 Figure 6 shows the phase noise at the output of the ADF4351, and the rms jitter is 325.7 fs. Figure 7 shows the phase noise at the ADCLK948 output. The rms jitter is 330.4 fs. OUT2 OUT2 USB 50Ω TERM The additive jitter of the ADCLK948 can be calculated as √(330.42 − 325.72) = 55.5 fs rms. The specified value from the ADCLK948 data sheet is 75 fs rms. PC SPECTRUM ANALYZER (R&S FSUP26) Figure 5. ADF4351 Phase Noise and Jitter Measurement Setup R&S FSUP 26 Signal Source Analyzer Settings LOCKED Residual Noise [T1 w/o spurs] Signal Frequency: 999.999524 MHz Int PHN (1.0 k .. 30.0 M) –56.8 dBc Signal Level: –3.86 dBm Residual PM Cross Corr Mode Harmonic 1 Residual FM 2.939 kHz Internal Ref Tuned Internal Phase Det RMS Jitter 0.3257 ps Phase Detector +20 dB 0.117 ° Phase Noise [dBc/Hz] Marker 1 [T1] Marker 2 [T1] Marker 3 [T1] Marker 4 [T1] RF Atten 1 kHz 10 kHz 100 kHz 1 MHz –101.53 dBc/Hz –104.91 dBc/Hz –113.11 dBc/Hz –142.41 dBc/Hz 5 dB Top –70 dBc/Hz Spur Power (dBc) LoopBW 300Hz –80 –80 –90 –90 A 1 CLRWR SMTH 1% 2 CLRWR 1 –100 2 –100 3 –110 –110 –120 –120 –130 –130 4 –140 1kHz –140 –150 –150 –160 –160 10kHz 100kHz 1MHz 10MHz FREQUENCY OFFSET Figure 6. ADF4351 Output Phase Noise Measurement Showing 325.7 fs rms Jitter Rev. 0 | Page 4 of 5 SPR OFF TH 0dB 30MHz 10989-005 2. POWER SUPPLY Repeat Step 1 to Step 4 from the Logic Level Measurement section. Terminate the unused CLK2 output of the ADCLK948/PCBZ with a 50 Ω load (see Figure 5). Connect the CLK2 output via a SMA cable to the signal source analyzer (see Figure 5). Measure the jitter performance of the signal. 10989-006 1. Circuit Note CN-0294 R&S FSUP 26 Signal Source Analyzer Settings LOCKED Phase Detector +20 dB Residual Noise [T1 w/o spurs] Signal Frequency: 999.999516 MHz Int PHN (1.0 k .. 30.0 M) –56.7 dBc Signal Level: –3.86 dBm Residual PM 0.119 ° Cross Corr Mode Harmonic 1 Residual FM 4.091 kHz Internal Ref Tuned Internal Phase Det RMS Jitter 0.3304 ps Phase Noise [dBc/Hz] Marker 1 [T1] Marker 2 [T1] Marker 3 [T1] Marker 4 [T1] RF Atten 1 kHz 10 kHz 100 kHz 1 MHz –101.38 dBc/Hz –104.99 dBc/Hz –113.61 dBc/Hz 5 dB Top –80 dBc/Hz –142.17 dBc/Hz Spur Power (dBc) LoopBW 300Hz –90 –90 –100 –100 A 1 2 3 –110 2 CLRWR –110 –120 –120 –130 –130 4 –140 1kHz –140 –150 –150 –160 –160 10kHz 100kHz 1MHz 10MHz SPR OFF TH 0dB 30MHz FREQUENCY OFFSET 10989-007 1 CLRWR SMTH 1% Figure 7. ADCLK948 Output Phase Noise Measurement Showing 330.4 fs rms Jitter LEARN MORE Data Sheets and Evaluation Boards CN0232 Design Support Package: http://www.analog.com/CN0232-DesignSupport ADF4351 Evaluation Board (EVAL-ADF4351EB1Z) ADCLK948 Evaluation Board (ADCLK948/PCBZ) UG-435 User Guide for the EVAL-ADF4350EB1Z board ADF4351 Data Sheet UG-068, User Guide for the ADCLK948/PCBZ board ADCLK948 Data Sheet MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of “AGND” and “DGND”, Analog Devices. REVISION HISTORY MT-086 Tutorial, Fundamentals of Phase Locked Loops (PLLs), Analog Devices. 9/12—Revision 0: Initial Version MT-101 Tutorial, Decoupling Techniques, Analog Devices. ADIsimPLL Design Tool (Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so. ©2012 Analog Devices, Inc. All rights reserved. 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