PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs AD9573 FEATURES GENERAL DESCRIPTION Fully integrated VCO/PLL core 0.54 ps rms jitter from 12 kHz to 20 MHz Input crystal frequency of 25 MHz Preset divide ratios for 100 MHz, 33.33 MHz LVDS/LVCMOS output format Integrated loop filter Space saving 4.4 mm × 5.0 mm TSSOP 0.235 W power dissipation 3.3 V operation The AD9573 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for PCI-e applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize line card performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. APPLICATIONS Line cards, switches, and routers CPU/PCIe applications Low jitter, low phase noise clock generation By connecting an external 25 MHz crystal, output frequencies of 100 MHz and 33.33 MHz can be locked to the input reference. The output divider and feedback divider ratios are preprogrammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space. The AD9573 is available in a 16-lead 4.4 mm × 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM VDD × 5 VCO LVDS DIVIDERS 3RD ORDER LPF XTAL OSC PFD/CP LDO 100MHz LVCMOS 33.33MHz GND × 5 OE 07500-001 AD9573 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9573 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Terminology .......................................................................................8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications..................................................................................... 3 Outputs ...........................................................................................9 PLL Characteristics ...................................................................... 3 Phase Frequency Detector (PFD) and Charge Pump ..........9 Clock Output Jitter ....................................................................... 3 Power Supply..................................................................................9 Clock Outputs ............................................................................... 3 LVDS Clock Distribution .......................................................... 10 Timing Characteristics ................................................................ 4 CMOS Clock Distribution ........................................................ 10 Control Pins .................................................................................. 4 Power .............................................................................................. 4 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 10 Crystal Oscillator .......................................................................... 4 Outline Dimensions ....................................................................... 11 Timing Diagrams.......................................................................... 4 Ordering Guide .......................................................................... 11 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 REVISION HISTORY 7/09—Revision 0: Initial Version Rev. 0 | Page 2 of 12 AD9573 SPECIFICATIONS Typical (typ) is given for VDD = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VDD and TA (−40°C to +85°C) variation. PLL CHARACTERISTICS Table 1. Parameter NOISE CHARACTERISTICS PLL Noise (100 MHz Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (33.33 MHz Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 5 MHz Spurious Content PLL Figure of Merit Min Typ Max Unit −121 −128 −131 −144 −150 −151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −131 −137 −140 −150 −151 −70 −217.5 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc/Hz Test Conditions/Comments CLOCK OUTPUT JITTER Table 2. Parameter LVDS OUTPUT ABSOLUTE TIME JITTER RMS Jitter (100 MHz Output) Min Typ Max Unit Test Conditions/Comments fsec 12 kHz to 20 MHz Max Unit Test Conditions/Comments Termination = 100 Ω differential 100 700 25 1.375 25 24 55 MHz mV mV V mV mA % 33.33 MHz V V % 540 CLOCK OUTPUTS Table 3. Parameter LVDS CLOCK OUTPUT Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Duty Cycle LVCMOS CLOCK OUTPUT Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Duty Cycle Min Typ 500 640 1.125 1.25 14 45 VS − 0.1 45 0.1 55 Rev. 0 | Page 3 of 12 Output shorted to GND Sourcing 1.0 mA current Sinking 1.0 mA current AD9573 TIMING CHARACTERISTICS Table 4. Parameter LVDS Output Rise Time, tRL Output Fall Time, tFL LVCMOS Output Rise Time, tRC Output Fall Time, tFC Min Typ Max Unit 140 140 200 200 260 260 ps ps 0.25 0.25 0.60 0.80 2.5 2.5 ns ns Test Conditions/Comments Termination = 100 Ω differential; CLOAD = 0 pF 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = open 20% to 80%; CLOAD = 5 pF 80% to 20%; CLOAD = 5 pF Min Typ Max Unit Test Conditions/Comments 0.8 120 1.0 V V μA μA CONTROL PINS Table 5. Parameter INPUT CHARACTERISTICS OE Pin Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current OE has a 50 kΩ pull-down resistor. 2.5 POWER Table 6. Parameter Power Supply Power Dissipation Min 3.0 Typ 3.3 235 Max 3.6 285 Unit V mW Test Conditions/Comments Min Typ Max Unit Test Conditions/Comments Parallel resonant/fundamental mode CRYSTAL OSCILLATOR Table 7. Parameter CRYSTAL SPECIFICATION Frequency ESR Load Capacitance Phase Noise Stability 25 MHz Ω pF dBc/Hz ppm 40 18 −138 −30 +30 @ 1 kHz offset TIMING DIAGRAMS DIFFERENTIAL SIGNAL SINGLE-ENDED 80% 80% VOD 50% CMOS 5pF LOAD 20% tFL tRC Figure 2. LVDS Timing, Differential tFC Figure 3. LVCMOS Timing Rev. 0 | Page 4 of 12 07500-004 tRL 07500-003 20% AD9573 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter VDD, VDDA, VDDX, and VDD33 to GND XO1, XO2 to GND 100M, 100M, 33M to GND Junction Temperature1 Storage Temperature Range Lead Temperature (10 sec) 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7. Rating −0.3 V to +3.6 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V 150°C −65°C to +150°C 300°C Table 9. Thermal Resistance Package Type 16-Lead TSSOP See Table 9 for θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA 90.3 ESD CAUTION AD9573 0.1µF VS VS GNDA 2 VDDA GND 15 3 VDDX 100M 14 Cx OE Cx 0.1µF 50Ω 0.1µF 4 XO1 100M 13 5 XO2 VDD 12 VS 0.1µF 0.1µF VS 16 1 1nF 6 GNDX VDD33 11 7 GNDA 33M 10 8 VDDA GND33 9 RT = 100Ω VS 07500-002 CRYSTAL: KYOCERA CX-49G Cx = 33pF 50Ω Figure 4. Typical Application Rev. 0 | Page 5 of 12 Unit °C/W AD9573 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDDA 2 15 GND VDDX 3 AD9573 14 100M TOP VIEW (Not to Scale) 13 100M XO1 4 XO2 5 12 VDD GNDX 6 11 VDD33 GNDA 7 10 33M VDDA 8 9 GND33 07500-005 16 OE GNDA 1 Figure 5. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1, 7 2, 8 3 4, 5 6 9 10 11 12 13 14 15 16 Mnemonic GNDA VDDA VDDX XO1, XO2 GNDX GND33 33M VDD33 VDD 100M 100M GND OE Description Analog Ground. Analog Power Supply (3.3 V). Crystal Oscillator Power Supply. External 25 MHz Crystal. Crystal Oscillator Ground. Ground for LVCMOS Output. LVCMOS Output at 33.33 MHz. Power Supply for LVCMOS Output. Power Supply for LVDS Output. Complementary LVDS Output at 100 MHz. LVDS Output at 100 MHz. Ground for LVDS Output. Output Enable (Active Low). Places both outputs in a high impedance state when high. This pin has a 50 kΩ internal pull-down resistor. Rev. 0 | Page 6 of 12 AD9573 TYPICAL PERFORMANCE CHARACTERISTICS –115 –120 PHASE NOISE (dBc/Hz) –125 –130 –135 –140 –145 –130 –140 –150 –155 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M Figure 6. 100 MHz Phase Noise –160 1k 10k 100k 1M FREQUENCY OFFSET (Hz) Figure 7. 33.33 MHz Phase Noise Rev. 0 | Page 7 of 12 10M 100M 07500-007 –150 07500-006 PHASE NOISE (dBc/Hz) –120 AD9573 TERMINOLOGY Phase Jitter Time Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as gaussian (normal) in distribution. Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Phase Noise When the total power contained within some interval of offset frequencies (for example, 12 kHz to 20 MHz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. 0 | Page 8 of 12 AD9573 THEORY OF OPERATION VDDA GNDA XTAL OSC VDD, GND, VDD33 GND33 VDDA GNDA CMOS 33.33MHz PHASE FREQUENCY DETECTOR DIVIDE BY 4 DIVIDE BY 3 33M LDO OE CHARGE PUMP 100M DIVIDE BY 25 100M LVDS 100MHz AD9573 07500-011 2.5GHz VCO VLDO Figure 8. Detailed Block Diagram Figure 8 shows a block diagram of the AD9573. The chip features a PLL core, which is configured to generate the specific clock frequencies required for PCI-express, without any user programming. This PLL is based on proven Analog Devices synthesizer technology, noted for its exceptional phase noise performance. The AD9573 is highly integrated and includes the loop filter, a regulator for supply noise immunity, all the necessary dividers, output buffers, and a crystal oscillator. A user need only supply a 25 MHz external crystal to implement an entire PCIe clocking solution, which does not require any processor intervention. Table 12. Output Enable Pin Function OE State Output State Enabled High impedance 0 1 Phase Frequency Detector (PFD) and Charge Pump The PFD takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and frequency difference between them. Figure 10 shows a simplified schematic. 3.3V OUTPUTS HIGH Table 11 provides a summary of the outputs available. REFCLK Table 11. Output Formats Format LVDS LVCMOS CLR1 Copies 1 1 CP The simplified equivalent circuit of the LVDS output is shown in Figure 9. The 100 MHz output is described as LVDS because it uses an LVDS driver topology. However, the levels are HCSL compatible, and therefore do not meet the LVDS standard. The output current has been increased to provide a larger output swing than standard LVDS. HIGH CLR2 DOWN D2 Q2 FEEDBACK DIVIDER GND Figure 10. PFD Simplified Schematic and Timing (in Lock) POWER SUPPLY 6.5mA The AD9573 requires a 3.3 V ± 10% power supply for VDD. The tables in the Specifications section give the performance expected from the AD9573 with the power supply voltage within this range. The absolute maximum range of (−0.3 V) − (+3.6 V), with respect to GND, must never be exceeded on the VDD or VDDA pins. OUT 07500-012 OUTB 6.5mA CHARGE PUMP 07500-013 Frequency 100 MHz 33.33 MHz D1 Q1 UP Figure 9. LVDS Output Simplified Equivalent Circuit Both outputs can be placed in a high impedance state by connecting the OE pin according to Table 12. This pin has a 50 kΩ pull-down resistor. Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF). The AD9573 should be decoupled with adequate capacitors (0.1 μF) at all power pins as close as possible to these power pins. The layout of the AD9573 Rev. 0 | Page 9 of 12 AD9573 LVDS CLOCK DISTRIBUTION Low voltage differential signaling (LVDS) is the differential output for the AD9573. LVDS uses a current mode output stage with a factory programmed current level. The normal value (default) for this current is 6.5 mA, which yields a 650 mV output swing across a 100 Ω resistor. The typical termination circuit for the LVDS outputs is shown in Figure 11. 100Ω LVDS LVDS 50Ω 07500-014 50Ω Figure 11. LVDS Output Termination An alternative method of terminating the output to preserve output swing but also minimize reflections is shown in Figure 12. LVDS 200Ω 200Ω 50Ω LVDS CMOS 10Ω 60.4Ω 1.0 INCH MICROSTRIP 5pF GND Figure 13. Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option. The CMOS output of the AD9573 does not supply enough current to provide a full voltage swing with a low impedance resistive, far end termination, as shown in Figure 14. The far end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. 07500-015 50Ω outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and preserve signal integrity. 07500-016 evaluation board shows a good example (see the Ordering Guide for information about the evaluation board). VPULLUP = 3.3V Figure 12. Alternative LVDS Output Termination CMOS CMOS CLOCK DISTRIBUTION 10Ω 50Ω 100Ω The AD9573 provides a 33.33 MHz clock output, which is a dedicated CMOS level. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be followed. Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS 3pF 07500-017 100Ω Figure 14. CMOS Output with Far-End Termination POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply decoupling and grounding to ensure optimum performance. Rev. 0 | Page 10 of 12 AD9573 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 15. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD9573ARUZ 1 AD9573-EVALZ1 1 Temperature Range −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 11 of 12 Package Option RU-16 AD9573 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07500-0-7/09(0) Rev. 0 | Page 12 of 12