ISO2-CMOS MT91L60 3 Volt Multi-Featured Codec (MFC) Advance Information Features ISSUE 1 • Single 2.7-3.6 volt supply operation • Programmable µ-Law/A-Law Codec and Filters • Programmable ITU-T (G.711)/sign-magnitude coding • Programmable transmit, receive and side-tone gains • Fully differential interface to handset transducers - including 300 ohm receiver driver • Flexible digital interface including ST-BUS/SSI • Serial microport • Single 3 volt supply • Low power operation • ITU-T G.714 compliant • Multiple power down modes May 1995 Ordering Information MT91L60AE 24 Pin Plastic DIP MT91L60AS 20 Pin SOIC -40°C to +85°C Description The MT91L60 3V Multi-featured Codec incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, reference voltage and bias source. The device supports both A-Law and µ-Law requirements. The MT91L60 is a true 3V device employing a fully differential architecture to ensure wide dynamic range. Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard micro-controllers. Applications • Battery operated equipment • Digital telephone sets • Cellular radio sets • Local area communications stations • Pair Gain Systems • Line cards VSSD VDD VSSA The MT91L60 is fabricated in Mitel's ISO2-CMOS technology ensuring low power consumption and high reliability. FILTER/CODEC GAIN AAAA AAAA AAAAAAAA AAAAAAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA ENCODER 7dB AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA DECODER -7dB AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA VBias VRef MM+ Transducer Interface HSPKR + HSPKR - Din Dout STB/F0i Timing Flexible Digital Interface ST-BUS C&D Channels CLOCKin Serial Microport PWRST IC CS DATA1 DATA2 A/µ/IRQ SCLK Figure 1 - Functional Block Diagram 7-107 MT91L60 Advance Information 20 PIN SOIC VBias VRef PWRST IC A/µ/IRQ VSSD CS SCLK DATA1 DATA2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 M+ MVSSA HSPKR + HSPKR VDD CLOCKin STB/F0i Din Dout 24 PIN PDIP VBias VRef NC PWRST IC A/µ/IRQ VSSD CS NC SCLK DATA1 DATA2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin NC STB/F0i Din Dout Figure 2 - Pin Connections Pin Description Pin # SOIC DIP Name Description 1 1 VBias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µF capacitor to VSSA. 2 2 VRef Reference Voltage for Codec (Output). Used internally. Connect 0.1 µF capacitor to VSSA. 3 4 PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). 4 5 IC 5 6 A/µ/IRQ 6 7 VSSD 7 8 CS 8 10 SCLK 9 11 DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/ National mode of operation, this pin becomes the data transmit pin only and data receive is performed on the DATA 2 pin. Input CMOS level compatible. 10 12 DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for data receive. In Intel mode, serial data transmit and receive are performed on the DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible. 7-108 Internal Connection. Tie externally to VSS for normal operation. A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs the companding law used by the filter/Codec; µ-Law when tied to VSS and A-Law when tied to VDD. Logically OR’ed with A/µ register bit. IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt output signalling valid access to the D-Channel registers in ST-BUS mode. Digital Ground. Nominally 0 volts. Chip Select (Input). This input signal is used to select the device for microport data transfers. Active low. CMOS level compatible. Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level compatible. MT91L60 Advance Information Pin Description (continued) Pin # SOIC DIP Name Description 11 13 Dout Data Output. A high impedance three-state digital output for 8 bit wide channel data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with the rising edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. 12 14 Din Data Input. A digital input for 8 bit wide channel data received from the Layer 1 transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible. 13 15 STB/F0i 14 17 CLOCKin Clock (Input). (CMOS level compatible). The clock provided to this input pin is used for the internal device functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin. 15 18 16 19 HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced). 17 20 HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced). 18 22 VSSA 19 23 M- Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone. 20 24 M+ Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. 3,9, 16,21 NC No Connect. (DIP Package only). VDD Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS mode. CMOS level compatible input. Positive Power Supply (Input). Nominally 3 volts. Analog Ground (Input). Nominally 0 volts. 7-109 MT91L60 Overview The 3V Multi-featured Codec (MFC) features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard handset transmitter and receiver (Transducer Interface). The receiver amplifier is capable of driving a 300 ohm load. Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller port compatible with Intel MCS-51®, Motorola SPI® and National Semiconductor Microwire® specifications. These parameters include: gain control, power down, mute, B-Channel select (ST-BUS mode), C&D channel control/access, law control, digital interface programming and loopback. Optionally the device may be used in a controllerless mode utilizing the power-on default settings. Functional Description Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/ Alternate Digit Inversion or true-sign/Inverted Magnitude coding, respectively. Optionally, sign- magnitude coding may also be selected for proprietary applications. The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and side-tone gains for the MT91L60. In the event of PWRST, the MT91L60 defaults such that the side-tone path is off, all programmable gains are set to 0dB and ITU-T µ-Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI and driver sections are powered up. (See Microport section.) The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a Advance Information wide dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer Interface section to provide full chip realization of these capabilities for the handset functions. A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (V Bias ), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog ground at all times. Likewise, although VRef may only be used internally, a 0.1µF capacitor from the V Ref pin to ground is required at all times. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the V Ref and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Side-tone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control bits located in Gain Control Register 2 (address 01h). Transmit and receive filter gains are controlled by the TxFG0-TxFG2 and RxFG0-RxFG2 control bits, respectively. These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0 dB to +7 dB and receive filter gain from 0dB to -7 dB, both in 1 dB increments. Side-tone filter gain is controlled by the STG0-STG2 control bits located in Gain Control Register 2 (address 01h). Side-tone gain is adjustable from -9.96 dB to +9.96 dB in 3.32 dB increments. Intel® and MCS-51® are registered trademarks of Intel Corporation Motorola® and SPI® are registered trademarks of Motorola Corporation National® and Microwire® are trademarks of National Semiconductor Corporation 7-110 MT91L60 Advance Information Companding law selection for the Filter/Codec is provided by the A/µ companding control bit while the coding scheme is controlled by the Smag/ITU-T control bit. The A/µ control bit is logically OR’ed with the A/µ pin providing access in both controller and controllerless modes. Both A/µ and Smag/ITU-T reside in Control Register 2 (address 04h). Table 1 illustrates these choices. ITU-T (G.711) Code Sign/ Magnitude µ-Law A-Law + Full Scale 1111 1111 1000 0000 1010 1010 + Zero 1000 0000 1111 1111 1101 0101 -Zero (quiet code) 0000 0000 0111 1111 0101 0101 - Full Scale 0111 1111 0000 0000 0010 1010 Control of this gain is provided by the TxINC control bit (Gain Control register 1, address 00h). • The handset speaker outputs (receiver), pins HSPKR+/HSPKR-. This internally compensated fully differential output driver is capable of driving the load shown in Figure 4. The nominal handset receive path gain may be adjusted to either 0 dB, -6 dB or -12 dB. Control of this gain is provided by the RxINC control bit (Gain Control register 1, address 00h). This gain adjustment is in addition to the programmable gain provided by the receive filter. HSPKR + 75 Ω Table 1 Transducer Interfaces Standard handset transducer interfaces are provided by the MT91L60. These are: 75 Ω • The handset microphone inputs (transmitter), pins M+/M-. The nominal transmit amplifier gain may be adjusted to either 6.0 dB or 15.3 dB. Serial Port 150 ohm load (speaker) MT91L60 HSPKR - Figure 4 - Handset Speaker Driver Filter/Codec and Transducer Interface Default Bypass Din -6.0 dB or 0 dB Receiver Driver -6 dB Side-tone -9.96 to +9. 96 dB (3.32 dB steps) HSPKR + 75Ω HSPKR - Handset Receiver (150Ω) 75Ω Default Side-tone off PCM Receive Filter Gain 0 to -7 dB (1 dB steps) -11 dB PCM Dout Transmit Filter Transmit Filter Gain Gain 00 to to +7 +7dBdB (1 dB steps) (1 dB steps) Transmit Gain -0.37 dB or 8.93 dB Transmit Gain 6.37 dB INTERNAL TO DEVICE M+ M- Transmitter Microphone EXTERNAL TO DEVICE Figure 3 - Audio Gain Partitioning 7-111 MT91L60 Microport The serial microport, compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0,CPHA=0) and National Semiconductor Microwire specifications provides access to all MT91L60 internal read and write registers. This microport consists of a transmit/ receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an open-drain interrupt output (IRQ). Advance Information these two schemes for normal data bytes. However, to ensure decoding of the R/W and address information, the Command/Address byte is defined differently for Intel operation than it is for Motorola/ National operation. Refer to the relative timing diagrams of Figures 5 and 6. Receive data is sampled on the rising edge of SCLK while transmit data is made available concurrent with the falling edge of SCLK. Flexible Digital Interface The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The device then automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual port Motorola controller configuration usually supports full-duplex communication, only half-duplex communication is possible in the MT91L60. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT91L60. During a valid read transfer from the MT91L60 data simultaneously clocked out by the micro is ignored by the MT91L60. A serial link is required to transport data between the MT91L60 and an external digital transmission device. The MT91L60 utilizes the ST-BUS architecture defined by Mitel Semiconductor but also supports a strobed data interface found on many standard Codec devices. This interface is commonly referred to as Synchronous Serial Interface (SSI). The combination of ST-BUS and SSI provides a Flexible Digital Interface (FDI) capable of supporting all Mitel basic rate transmission devices as well as many other 2B+D transceivers. The required mode of operation is selected via the CSL2-0 control bits (Control Register 2, address 04h). Pin definitions alter dependent upon the operational mode selected, as described in the following subsections as well as in the Pin Description tables. Quiet Code All data transfers through the microport are two-byte transfers requiring the transmission of a Command/ Address byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT91L60 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT91L60 and the microcontroller. At the end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which will remain tri-stated as long as CS is high. Intel processors utilize least significant bit first transmission while Motorola/National processors employ most significant bit first transmission. The MT91L60 microport automatically accommodates 7-112 The FDI can be made to send quiet code to the decoder and receive filter path by setting the RxMute bit high. Likewise, the FDI will send quiet code in the transmit path when the TxMute bit is high. Both of these control bits reside in Control Register 1 at address 03h. When either of these bits are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition. ST-BUS Mode The ST-BUS consists of output (DSTo) and input (DSTi) serial data streams, in FDI these are named Dout and Din respectively, a synchronous clock input signal CLOCKin (C4i), and a framing pulse input (F0i). These signals are direct connections to the corresponding pins of Mitel basic rate devices. The CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS operation. MT91L60 Advance Information The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s bandwidth. A frame pulse (a 244 nSec low going pulse) is used to parse the continuous serial data streams into the 32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. A valid frame begins when F0i is COMMAND/ADDRESS ➄ ➀ logic low coincident with a falling edge of C4i. Refer to Figure 11 for detailed ST-BUS timing. C4i has a frequency (4096 kHz) which is twice the data rate. This clock is used to sample the data at the 3/4 bit-cell position on DSTi and to make data available on DSTo at the start of the bit-cell. C4i is also used to clock the MT91L60 internal functions (i.e., Filter/ DATA INPUT/OUTPUT ➃ COMMAND/ADDRESS: ➀ DATA 1 RECEIVE D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DATA 1 TRANSMIT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCLK ② ➃ CS ➂ ➀ ➂ Delays due to internal processor timing which are transparent. ② The MT91L60:-latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. ➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. ➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 ➄ The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 3 bits - Addressing Data X X A2 A1 X X 4 bits - Unused D0 A0 R/W Figure 5 - Serial Port Relative Timing for Intel Mode 0 COMMAND/ADDRESS ➄ ➀ DATA INPUT/OUTPUT ➃ COMMAND/ADDRESS: ➀ DATA 2 RECEIVE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DATA 1 TRANSMIT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK ② ➃ CS ➂ ➂ ➀ Delays due to internal processor timing which are transparent . ② The MT91L60:-latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. ➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. ➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 ➄ The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 3 bits - Addressing Data A2 4 bits - Unused X X R/W X A1 D0 A0 X Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire 7-113 MT91L60 Advance Information 125 µs F0i DSTi, DSTo CHANNEL 0 D-channel LSB first for DChannel CHANNEL 1 C-channel CHANNEL 2 B1-channel CHANNEL 3 B2-channel CHANNELS 4-31 Not Used MSB first for C, B1- & B2Channels Figure 7 - ST-BUS Channel Assignment Codec, Digital gain and tone generation) and to provide the channel timing requirements. The MT91L60 uses only the first four channels of the 32 channel frame. These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 7 (ST-BUS channel assignments). The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (Control Register 2, address 04h). ISDN basic rate service (2B+D) defines a 16 kb/s signalling (D) Channel. The MT91L60 supports transparent access to this signalling channel. ST-BUS basic rate transmission devices, which may not employ a microport, provide access to their internal control/status registers through the ST-BUS Control (C) Channel. The MT91L60 supports microport access to this C-Channel. DEN - D-Channel In ST-BUS mode access to the D-Channel (transmit and receive) data is provided through an 8-bit read/ write register (address 06h). D-Channel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame for 16 kb/s operation (1 bit/ frame for 8 kb/s operation). Since the ST-BUS is asynchronous, with respect to the microport, valid access to this register is controlled through the use of an interrupt (IRQ) output. D-Channel access is enabled via the (DEn) bit. DEn: When 1, ST-BUS D-channel data (1 or 2 bits/frame depending on the state of the D8 bit) is shifted into/ out of the D-channel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel timeslot and IRQ outputs are tri-stated (default). 7-114 D8: When 1, D-Channel data is shifted at the rate of 1 bit/ frame (8 kb/s). When 0, D-Channel data is shifted at the rate of 2 bits/frame (16 kb/s default). 16 kb/s D-Channel operation is the default mode which allows the microprocessor access to a full byte of D-Channel information every fourth ST-BUS frame. By arbitrarily assigning ST-BUS frame n as the reference frame, during which the microprocessor D-Channel read and write operations are performed, then: (a) A microport read of address 04 hex will result in a byte of data being extracted which is composed of four di-bits (designated by roman numerals I,II,III,IV). These di-bits are composed of the two D-Channel bits received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 8a: di-bit I is mapped from frame n-3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from frame n. The D-Channel read register is not preset to any particular value on power-up (PWRST) or software reset (RST). (b) A microport write to Address 04 hex will result in a byte of data being loaded which is composed of four di-bits (designated by roman numerals I, II, III, IV). These di-bits are destined for the two D-Channel bits transmitted during each of frames n+1, n+2, n+3, n+4. Referring to Fig. 8a: di-bit I is mapped to frame n+1, di-bit II is mapped to frame n+2, di bit III is mapped to frame n+3 and di bit IV is mapped to frame n+4. If no new data is written to address 04 hex , the current D-channel register contents will be continuously re-transmitted. The D-Channel write register is preset to all ones on power-up (PWRST) or software reset (RST). MT91L60 Advance Information IRQ Microport Read/Write Access FP n-3 n-2 n-1 n n+1 n+2 n+3 n+4* DSTo/ DSTi Di-bit Group Receive D0 D-Channel I II D1 D2 D3 No preset value D4 III IV D5 D6 D7 Di-bit Group Transmit D0 D-Channel I D1 D2 II D3 D4 III D5 D6 IV D7 Power-up reset to 1111 1111 * note that frame n+4 is equivalent to frame n of the next cycle. Figure 8a - D-Channel 16 kb/s Operation FP C4i C2 DSTo/ DSTi D0 tir =500 nsec max Rpullup= 10 k D1 tif =500 nsec max IRQ 8 kb/s operation 16 kb/s operation Reset coincident with Read/Write of Address 04 Hex or next FP, whichever occurs first Microport Read/Write Access Figure 8b - IRQ Timing Diagram FP Microport Read/Write Access IRQ n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 n+6 n+5 n+7 n+8 D-Channel Di-bit Group Receive D-Channel I D0 II D1 III D2 IV D3 No preset value V D4 VI D5 VII D6 VIII D7 Di-bit Group Transmit D-Channel I D0 II D1 III D2 IV D3 V D4 VI D5 VII D6 VIII D7 Power-up reset to 1111 1111 Figure 8c - D-Channel 8 kb/s Operation 7-115 MT91L60 An interrupt output is provided (IRQ) to synchronize microprocessor access to the D-Channel register during valid ST-BUS periods only. IRQ will occur every fourth (eighth in 8 kb/s mode) ST-BUS frame at the beginning of the third (second in 8 kb/s mode) ST-BUS bit cell period. The interrupt will be removed following a microprocessor Read or Write of Address 04 hex or upon encountering the following frames’s FP input, whichever occurs first. To ensure D-Channel data integrity, microport read/write access to Address 04 hex must occur before the following frame pulse. See Figure 8b for timing. 8 kb/s operation expands the interrupt to every eight frames and processes data one-bit-per-frame. D-Channel register data is mapped according to Figure 8c. CEn - C-Channel Channel 1 conveys the control/status information for the Layer 1 transceiver. C-Channel data is transferred MSB first on the ST-BUS by the MT91L60. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and order of bit transfer. When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most significant bit first, on DSTo. On power-up reset (PWRST) or software reset (Rst, address 03h) all C-Channel bits default to logic high. Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state. When low, data transmission is halted and this timeslot is tri-stated on DSTo. B1-Channel and B2-Channel Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Filter/Codec and transducer audio paths is selected on an independent basis for the transmit and receive paths. TxBSel and RxBSel (Control Register 1, address 03h) are used for this purpose. If no valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR control bits, Control Register 1 address 03h). Advance Information SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), and a framing strobe input (STB). The frame strobe must be synchronous with, and eight cycles of, the bit clock. A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 12 & 13. In SSI mode the MT91L60 supports only B-Channel operation. The internal C and D Channel registers used in ST-BUS mode are not functional for SSI operation. The control bits TxBSel and RxBSel, as described in the ST-BUS section, are ignored since the B-Channel timeslot is defined by the input STB strobe. Hence, in SSI mode transmit and receive B-Channel data are always in the channel defined by the STB input. The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This is an active high signal with an 8 kHz repetition rate. SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is 512 kHz or greater then it is used directly by the internal MT91L60 functions allowing synchronous operation. If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal MT91L60 functions. Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT91L60 will re-align its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control bits CSL2, CSL1 and CSL0 in Control Register 2 (address 04h) are used to program the bit rates. For synchronous operation data is sampled, from Din, on the falling edge of BCL during the time slot defined by the STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input. Dout is tri-stated at all times when STB is not true. If STB is valid but PDFDI and PDDR are not true, then quiet code will be transmitted on Dout during the valid strobe period. There is no frame delay through the FDI circuit for synchronous operation. For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output jitter on Dout is larger. This is due to 7-116 MT91L60 Advance Information the resynchronization circuitry activity and will not affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the FDI circuit for asynchronous operation. Refer to the specifications of Figures 12 & 13 for both synchronous and asynchronous SSI timing. After Power-up reset (PWRST) or software reset (Rst) all control bits assume their default states; µ-Law functionality, usually 0 dB programmable gains as well as the device powered up in SSI mode 2048 kb/s operation with Dout tri-stated while there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active, during the defined channel. PWRST/Software Reset (Rst) While the MT91L60 is held in PWRST no device control or functionality is possible. While in software reset (Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing Rst logic low or by setting the PWRST pin. To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control Register 1, address 03h) or put PWRST pin low. 3V Multi-featured Codec Register Map 00 RxINC RxFG2 RxFG 1 RxFG 0 TxINC TxFG2 TxFG 1 TxFG 0 Gain Control Register 1 01 - - - - - STG 2 STG 1 STG 0 Gain Control Register 2 02 - - - - - - - DrGain Path Control 03 PDFDI PDDR RST - T xMute R xMute T xBsel R xBsel Control Register 1 04 CEN DEN D8 A/µ Smag/ ITU-T CSL 2 CSL 1 CSL 0 Control Register 2 05 C7 C6 C5 C4 C3 C2 C1 C0 C-Channel Register 06 D7 D6 D5 D4 D3 D2 D1 D0 D-Channel Register 07 - - - - PCM/ ANALOG loopen - - Loop Back 7-117 MT91L60 Advance Information Register Summary Gain Control Register 1 ADDRESS = 00h WRITE/READ VERIFY Power Reset Value 1000 0000 RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 7 6 Receive Gain Setting (dB) 5 4 3 RxFG2 RxFG1 RxFG 0 2 1 0 Transmit Gain Setting (dB) TxFG 2 TxFG 1 TxFG 0 0 0 0 (default) 0 0 0 0 -1 0 0 1 1 0 0 1 -2 0 1 0 2 0 1 0 -3 0 1 1 3 0 1 1 -4 1 0 0 4 1 0 0 -5 1 0 1 5 1 0 1 -6 1 1 0 6 1 1 0 -7 1 1 1 7 1 1 1 (default) 0 RxFGn = Receive Filter Gain bit n TxFGn = Transmit Filter Gain bit n RxINC: When high, the receiver driver nominal gain is set to 0 dB. When low, this gain is -6.0 dB. TxINC: When high, the transmit amplifier nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB. Gain Control Register 2 ADDRESS = 01h WRITE/READ VERIFY - - - - - STG2 STG1 STG0 7 6 5 4 3 2 1 0 Side-tone Gain Setting (dB) (default) OFF -9.96 -6.64 -3.32 0 3.32 6.64 9.96 STG 2 STG 1 STG 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 STGn = Side-tone Gain bit n Note: Bits marked "-" are reserved bits and should be written with logic "0" 7-118 Power Reset Value XXXX X000 MT91L60 Advance Information Path Control ADDRESS = 02h WRITE/READ VERIFY 7 DrGain - - - - - - DrGain 6 5 4 3 2 1 0 Power Reset Value XX00 0000 When high, the receiver driver gain is set to -6 dB, with sidetone. When low, the receiver driver gain is set to 0 dB, with no sidetone. Control Register 1 ADDRESS = 03h WRITE/READ VERIFY PDFDI PDDR 7 PDFDI PDDR Rst TxMute RxMute TxBsel RxBsel 6 Rst _ 5 4 TxMute RxMute TxBsel RxBsel 3 2 1 Power Reset Value 1100 0000 0 When high, the FDI PLA and the Filter/Codec are powered down (default). When low, the FDI is active. When high, the ear driver and Filter/Codec are powered down A (default). In addition, in ST-BUS mode, the selected output channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The output will be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver and Filter/Codec are active if PDFDI is low. When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the microport is not affected. A software reset can be removed only by writing this bit low or by a PWRST. When low, the reset condition is removed. When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When low the full transmit path functions normally (default). When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a mute state. When low the full receive path functions normally (default). When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in ST-BUS mode. Not used in SSI mode. When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in ST-BUS mode. Not used in SSI mode. Note: Bits marked "-" are reserved bits and should be written with logic "0" 7-119 MT91L60 Advance Information Control Register 2 CEn ADDRESS = 04h WRITE/READ VERIFY DEn D8 A/µ 6 5 4 7 CEn Smag/ ITU-T 3 CSL2 CSL1 2 1 Power Reset Value 0000 0010 0 When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation and is ignored for SSI operation. When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0 on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation. DEn D8 A/µ When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default). When high, A-Law encoding/decoding is selected for the MT91L60. When low, µ-Law encoding/decoding is selected. When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate digit inversion (A-Law). Smag/ITU-T CSL2 CSL1 CSL0 External bit Clock Rate (kHz) 1 1 1 1 0 0 1 0 0 0 0 0 0 CLOCKin (kHz) Mode not applicable 4096 ST-BUS 128 4096 SSI 1 256 4096 SSI 0 512 512 SSI 0 1 1536 1536 SSI 1 0 2048 2048 SSI (default) 1 1 4096 4096 SSI Note: Bits marked "-" are reserved bits and should be written with logic "0" 7-120 CSL0 MT91L60 Advance Information C-Channel Register ADDRESS = 05h WRITE/READ C7 C6 C5 C4 C3 C2 C1 C0 7 6 5 4 3 2 1 0 Power Reset Value 1111 1111- write XXXX XXXX - read Micro-port access to the ST-BUS C-Channel information read and write D-Channel Register D7-D0 ADDRESS = 06h WRITE/READ D7 D6 7 6 D5 D4 5 4 D3 D2 D1 D0 3 2 1 0 Power Reset Value 1111 1111- write XXXX XXXX - read Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h). Received D-Channel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are accessible only when IRQ indicates valid access. ADDRESS = 07h WRITE/READ VERIFY Loopback Register - - - - 7 6 5 4 PCM/ ANALOG 3 loopen - - 2 1 0 Power Reset Value XXXX 0000 PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low. For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on Din is looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to HSPKR ± ) still functions. When low, the device is configured for analog-to-analog operation. An analog input signal at M± is looped back to the SPKR± outputs through the A/D and D/A circuits as well as through the normal transmit A/D path (from M± to Dout). loopen When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit. When low, loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored. Note: Bits marked "-" are reserved bits and should be written with logic "0" 7-121 MT91L60 Advance Information Absolute Maximum Ratings Parameter Symbol Min Max Units VDD - VSS - 0.3 7 V VI/VO VSS - 0.3 VDD + 0.3 V ± 20 mA + 150 °C 750 mW 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) II/IO 4 Storage Temperature TS 5 Power Dissipation (package) PD Recommended Operating Conditions Characteristics Voltages are with respect to VSS unless otherwise stated Sym Min Typ Max Units 2.7 3 3.6 V VDD V 1 Supply Voltage VDD 2 CMOS Input Voltage (high) VIHC 3 CMOS Input Voltage (low) VILC VSS 4 Operating Temperature TA - 40 * Excluding PWRST which is a Schmitt Trigger Input. 7-122 - 65 V + 85 °C Test Conditions MT91L60 Advance Information DC Electrical Characteristics† - Voltages are with respect to ground (VSS) Characteristics Sym Typ‡ Min unless otherwise stated. Max Units Test Conditions 1 Input HIGH Voltage CMOS inputs VIHC 2.1 V 2 Input LOW Voltage CMOS inputs VILC .9 V 3 VBias Voltage Output VBias VDD/2 V 4 Input Leakage Current IIZ 0.1 5 Positive Going Threshold Voltage (PWRST only) Negative Going Threshold Voltage (PWRST only) VT+ 2 V VT- 1 V 6 Output HIGH Current IOH -2 mA VOH = 2V 7 Output LOW Current IOL 2 mA VOL = 0.4V 8 Output Leakage Current IOZ 0.01 µA VOUT = VDD and VSS 9 Output Capacitance Co 15 pF 10 Input Capacitance Ci 10 pF 10 10 Max. Load = 10kΩ µA VIN=VDD to VSS † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Clockin Tolerance Characteristics (ST-BUS Mode) Characteristics 1 C4i Frequency Min Typ‡ Max Units 4095.6 4096 4096.4 kHz Test Conditions (i.e., 100 ppm) † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 7-123 MT91L60 Advance Information AC Characteristics† for A/D (Transmit) Path - 0dBm0 = 1.026Vrms for µ-Law and 1.066Vrms for A-Law, at the Codec. (VBias=1.5 volts.) Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M ± to Dout Sym Min ALi3.17 ALi3.14 GAX1 GAX2 Tolerance at all other transmit filter settings (1 to 7dB) Typ‡ Max Units 4.2 4.4 4.2 4.6 Vp-p Vp-p 6.0 15.3 dB dB ±0.2 dB µ-Law A-Law Both at Codec Transmit filter gain=0dB setting. TxINC = 0* TxINC = 1* @1020 Hz 3 Gain tracking vs. input level ITU-T G.714 Method 2 GTX -0.3 -0.6 -1.6 4 Signal to total Distortion vs. input level. ITU-T G.714 Method 2 DQX 35 29 24 5 Transmit Idle Channel Noise NCX NPX 6 Gain relative to gain at 1020Hz <50Hz 60Hz 200Hz 300 - 3000 Hz 3000 - 3400 Hz 4000 Hz >4600 Hz GRX 7 Absolute Delay DAX 360 µs at frequency of minimum delay 8 Group Delay relative to DAX DDX 750 380 130 750 µs µs µs µs 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz 9 Power Supply Rejection f=1020 Hz f=0.3 to 3 kHz f=3 to 4 kHz f=4 to 50 kHz 0.3 0.6 1.6 Test Conditions 15 -70 -0.25 -0.9 PSSR PSSR1 PSSR2 PSSR3 37 40 35 40 dB dB dB 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 dB dB dB 0 to -30 dBm0 -40 dBm0 -45 dBm0 16.5 -69 dBrnC0 dBm0p -25 -30 0.0 0.25 0.25 -12.5 -25 dB dB dB dB dB dB dB dB dB dB dB µ-Law A-Law ±100mV peak signal on VDD µ-law PSSR1-3 not production tested † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note: TxINC, refer to Control Register 1, address 00h. 7-124 MT91L60 Advance Information AC Characteristics† for D/A (Receive) Path - 0dBm0 = 1.026Vrms for µ-Law and 1.066Vrms for A-Law, at the Codec. (VBias=1.5 volts.) Sym 1 Analog output at the Codec full scale ALo3.17 ALo3.14 4.183 4.331 Vp-p Vp-p 2 Absolute half-channel gain. GAR1 GAR2 GAR3 GAR4 0 -6 -6 -12 dB dB dB dB ±0.2 dB Din to HSPKR± Min Typ‡ Characteristics Tolerance at all other receive filter settings (-1 to -7dB) Max Test Conditions µ-Law A-Law DrGain=0, RxINC =1* DrGain=0, RxINC =0* DrGain=1, RxINC =1* DrGain=1, RxINC =0* @ 1020 Hz 3 Gain tracking vs. input level ITU-T G.714 Method 2 GTR -0.3 -0.6 -1.6 4 Signal to total distortion vs. input level. ITU-T G.714 Method 2 GQR 35 29 24 5 Receive Idle Channel Noise NCR NPR 6 Gain relative to gain at 1020Hz 200Hz 300 - 3000 Hz 3000 - 3400 Hz 4000 Hz >4600 Hz GRR 7 Absolute Delay DAR 240 µs at frequency of min. delay 8 Group Delay relative to DAR DDR 750 380 130 750 µs µs µs µs 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz 9 Crosstalk CTRT CTTR dB dB G.714.16 ITU-T D/A to A/D A/D to D/A 0.3 0.6 1.6 Units 13 -78.5 -0.25 -0.90 dB dB dB 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 dB dB dB 0 to -30 dBm0 -40 dBm0 -45 dBm0 15.5 -77 dBrnC0 dBm0p 0.25 0.25 0.25 -12.5 -25 dB dB dB dB dB -74 -80 µ-Law A-Law † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h. 7-125 MT91L60 Advance Information AC Electrical Characteristics† for Side-tone Path Characteristics 1 Absolute path gain gain adjust = 0dB Sym Min GAS1 GAS2 Typ‡ Max -16.63 -10.63 Units dB dB Test Conditions RxINC = 0* RxINC = 1* M± inputs to HSPKR± outputs 1000 Hz at STG2=1 † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h. Electrical Characteristics† for Analog Outputs Characteristics Sym Min Typ‡ 260 300 ohms 300 pF each pin: % 300 ohms load across HSPKR± (tol-15%), VO≤693mVRMS, RxINC=1*, Rx gain=0dB 1 EarpIece load impedance EZL 2 Allowable earpiece capacitive load ECL 3 Earpiece harmonic distortion ED Max 0.5 Units Test Conditions across HSPKR± † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h. 7-126 HSPKR+, HSPKR-