PHILIPS TDA1547

INTEGRATED CIRCUITS
DATA SHEET
TDA1547
Dual top-performance bitstream
DAC
Product specification
File under Integrated Circuits, IC01
September 1991
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
FEATURES
• Top-grade audio performance
– very low harmonic distortion
– high signal-to-noise ratio
– wide dynamic range of approximately 108 dB
(not A-weighted)
• High crosstalk immunity
• Bitstream concept
third-order noise shaper. The excellent performance of the
SAA7350 and TDA1547 bitstream conversion system is
obtained by separating the noise shaping circuit and the
one-bit conversion circuit over two IC's, thereby reducing
the crosstalk between the digital and analog parts. The
TDA1547 one-bit converter is processed in BIMOS. In the
digital logic and drivers bipolar transistors are used to
optimize speed and to reduce digital noise generation. In
the analog part the bipolar transistors are used to obtain
high performance of the operational amplifiers. Special
layout precautions have been taken to achieve a high
crosstalk immunity. The layout of the TDA1547 has fully
separated left and right channels and supply voltage lines
between the digital and analog sections.
– high over-sampling rate up to 192 fs
– pulse-density modulation
– inherently monotonic
– no zero-crossing distortion
GENERAL DESCRIPTION
The TDA1547 is a dedicated one-bit digital-to-analog
converter to facilitate a high fidelity sound reproduction of
digital audio. The TDA1547 is extremely suitable for use in
high quality audio systems such as Compact Disc and
DAT players, or in digital amplifiers and digital signal
processing systems. The TDA1547 is used in combination
with the SAA7350 bitstream circuit, which includes the
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
TDA1547(1)
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
32
SDIL
plastic
SOT232A
Note
1. SOT-232-1; 1996 August 23.
September 1991
2
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
handbook, halfpage
DGND
1
32
VSUB
VDDD
2
31
VSSD
IN R
3
30 IN L
n.c.
4
29 n.c.
CLK R
5
28 CLK L
VDDD R
6
27
V DDD L
VSSD R
7
26
V SSD L
Vref R
8
25
V ref L
AGND DAC R
9
24
AGND DAC L
– DAC R 10
23
– DAC L
+ DAC R 11
22
+ DAC L
AGND R 12
21
AGND L
TDA1547
n.c. 13
20 n.c.
+ OUT R 14
19 + OUT L
– OUT R 15
18
– OUT L
V SSA 16
17
V DDA
MCD294
Fig.1 Pinning diagram.
September 1991
3
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
PINNING
SYMBOL
PIN
DESCRIPTION
DGND
1
0 V digital supply
VDDD
2
5 V digital supply for both channels
IN R
3
serial one-bit data input for the right channel
n.c.
4
pin not connected; should preferably be connected to digital ground
CLK R
5
clock input for the right channel
VDDD R
6
5 V digital supply for the right channel; this voltage determines the internal logic HIGH level
in the right channel
VSSD R
7
−3.5 V digital supply for the right channel; this voltage determines the internal logic LOW
level in the right channel
Vref R
8
−4 V reference voltage for the right channel switched capacitor DAC
AGND DAC R
9
0 V reference voltage for the right channel switched capacitor DAC; this pin should be
connected to analog ground
−DAC R
10
output from the right negative switched capacitor DAC; feedback connection for the right
negative operational amplifier
+DAC R
11
output from the right positive switched capacitor DAC; feedback connection for the right
positive operational amplifier
AGND R
12
0 V reference voltage for both right channel operational amplifiers
n.c.
13
pin not connected; should preferably be connected to analog ground
+OUT R
14
+ output of the switched capacitor operational amplifier
−OUT R
15
− output of the switched capacitor operational amplifier
VSSA
16
−5 V analog supply
VDDA
17
5 V analog supply
−OUT L
18
− output of the switched capacitor operational amplifier
+OUT L
19
+ output of the switched capacitor operational amplifier
n.c.
20
pin not connected; should preferably be connected to analog ground
AGND L
21
0 V reference voltage for both left channel operational amplifiers
+DAC L
22
output from the left positive switched capacitor DAC; feedback connection for the left
positive operational amplifier
−DAC L
23
output from the left negative switched capacitor DAC; feedback connection for left negative
operational amplifier
AGND DAC L
24
0 V reference voltage for the left channel switched capacitor DAC; this pin should be
connected to analog ground
Vref L
25
−4 V reference voltage for the left channel switched capacitor DAC
VSSD L
26
−3.5 V digital supply for the left channel; this voltage determines the internal logic LOW level
in the left channel
VDDD L
27
5 V digital supply for the left channel; this voltage determines the internal logic HIGH level in
the left channel
September 1991
4
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
SYMBOL
TDA1547
PIN
DESCRIPTION
CLK L
28
clock input for the left channel
n.c.
29
pin not connected; should preferably be connected to digital ground
IN L
30
serial one-bit data input for the left channel
VSSD
31
−5 V digital supply for both channels
VSUB
32
−5 V substrate voltage
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Supply voltages
VDDD L. R
positive digital supply voltage for one
channel; pins 27 and 6
4.5
5.0
5.5
V
VDDD
digital supply voltage for both channels;
pin 2
4.5
5.0
5.5
V
VSSD L. R
negative digital supply voltage for one
channel; pins 26 and 7
−4.0
−3.5
−3.0
V
VSSD
negative digital supply voltage for both
channels; pin 31
−5.5
−5.0
−4.5
V
VDDA
positive analog supply voltage; pin 17
4.5
5.0
6
V
VSSA
negative analog supply voltage; pin 16
−6.0
−5.0
−4.5
V
IDDD L. R
positive digital supply current for one
channel; pins 27 and 6
−
0.1
−
mA
IDDD
digital supply current for both channels;
pin 2
−
29.0
−
mA
ISSD L. R
negative digital supply current for one
channel; pins 26 and 7
−
−0.1
−
mA
ISSD
negative supply current for both channels;
pin 31
−
−28.0
−
mA
IDDA
positive analog supply current; pin 17
−
51.0
−
mA
Supply current
ISSA
negative analog supply current; pin 16
−
−51.0
−
mA
Ptot
total power dissipation
−
800
−
mW
VOUT(RMS)
output voltage (RMS value)
0.85
1.0
1.15
V
September 1991
fCLK = 8.46 MHz;
notes 1 and 2
5
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
SYMBOL
TDA1547
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Supply current
(THD + N)/S
1 kHz; notes 2 and 3 −
THD + Noise; 0 dB
−101
−96
dB
−
0.0009 0.0016 %
f = 20 Hz to 20 kHz;
−
−101
(THD + N)/S
THD + Noise; 0 dB
notes 2 and 4
−
0.0009 -
%
(THD + N)/S
THD + Noise; −20 dB
f = 1 kHz;
notes 2 and 3
−
−88
−84
dB
(THD + N)/S
THD + Noise; −60 dB
f = 1 kHz;
notes 2 and 3
−
−48
−44
dB
S/N
signal-to-noise ratio
pattern 0101..;
notes 2 and 5
109
111
−
dB
S/N
signal-to-noise ratio; “A”-weighting
pattern 0101..;
notes 2 and 5
−
113
−
dB
fCLK
maximum clock frequency
−
−
10
MHz
α
channel separation
101
115
−
dB
Tamb
operating ambient temperature
−20
−
70
°C
f = 1 kHz
-
dB
Notes to the quick reference data
1. Output level tracks linearly with both the clock frequency and the reference voltage (Vref L or Vref R).
2. Device measured in differential mode with external components as shown in Fig.5.
3. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 1 kHz digital
sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
4. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 20 Hz to 20 kHz
digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
5. The specified signal-to-noise ratio includes noise introduced by the application components as shown in Fig.5.
FUNCTIONAL DESCRIPTION
Both channels are completely separated to reach the desired high crosstalk suppression level.
Each channel consists of the following functional parts:
− One-bit input, which latches the incoming data to the system clock.
− Switch driver circuit, which generates the non-overlapping clock- and data-signals that control the DAC switched
capacitor networks.
− Switched capacitor network, this forms the actual DAC function, it supplies charge packets to the low-pass filter,
under control of the incoming one-bit code.
− Two high performance operational amplifiers, that perform the charge packet to voltage conversion and deliver a
differential output signal. The first pole of the low-pass filter is built around them.
THERMAL RESISTANCE
SYMBOL
Rth j-a
September 1991
PARAMETER
from junction to ambient
MAX.
60
6
UNIT
K/W
September 1991
7
(0 V)
DGND
1
2
(+5 V)
V DDD
TDA1547
n.c.
4
ONE-BIT
INPUT
data
input right
3
29
n.c.
ONE-BIT
INPUT
30
32
31
data
input left
VSUB
(– 5 V)
VSSD
(– 5 V)
clock
input right
5
28
clock
input left
(+5 V)
VDDD R
6
7
9
10
23
11
22
12
21
(0 V)
AGND R
positive DAC
output
negative DAC
output
(0 V)
AGND DAC R
(– 4 V)
Vref R
8
SWITCHED
CAPACITOR
NETWORK
SWITCHED
CAPACITOR
NETWORK
24
AGND L
(0 V)
positive DAC
output
negative DAC
output
AGND DAC L
(0 V)
25
Vref L
(– 4 )
Fig.2 Block diagram.
(– 3.5 V)
VSSD R
SWITCH
DRIVERS
26
(– 3.5 V)
VSSD L
SWITCH
DRIVERS
27
(+5 V)
V DDD L
n.c.
13
20
n.c.
positive
output
14
19
negative
output
15
18
(– 5 V)
VSSA
MCD293
16
RIGHT
CHANNEL
LEFT
CHANNEL
17
(+5 V)
VDDA
negative output
positive output
Dual top-performance bitstream DAC
handbook, full pagewidth
Philips Semiconductors
Product specification
TDA1547
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX.
UNIT
VSUB
negative substrate voltage; pin 32
−7.0
−
V
VDDD L. R
positive digital supply voltage; pins 27 and 6
−
5.5
V
VDDD
positive digital supply voltage; pin 2
−
5.5
V
VSSD L. R
negative digital supply voltage; pins 26 and 7
−4.0
−
V
VSSD
negative digital supply voltage; pin 31
−5.5
−
V
VDDA
positive analog supply voltage; pin 17
−
6.0
V
VSSA
negative analog supply voltage; pin 16
−6.0
−
V
VDDD L. R −
VSSD L. R
supply voltage difference between pins 27, 6
and pins 26, 7
−
9.0
V
Ptot
total power dissipation
−
1300
mW
Vref L. R
input reference voltage; pins 25 and 8
−6.0
V
VCLK L. R
input voltage clock; pins 28 and 5
−0.5
VDDD+0.5 V
VI L
input voltage channel; pin 30
−0.5
VDDD+0.5 V
VI R
input voltage channel; pin 3
−0.5
VDDD+0.5 V
note 1
Tamb = 70 °C
Tamb
operating ambient temperature
−20
70
°C
Tstg
storage temperature
−40
150
°C
TXTAL
maximum crystal temperature
−
150
°C
VES
electrostatic handling
−
2000
V
note 2
Notes to the limiting values
1. The substrate voltage must be lower than or equal to the lowest supply voltage.
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
September 1991
8
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
CHARACTERISTICS
VDDD, VDDD L. R, VDDA = +5 V; VSSD, VSSA = −5 V, VSSD L. R = −3.5 V; Vref L. R = −4 V; Tamb = 25 °C; fCLK = 8.46 MHz;
unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supply
VSUB
negative substrate voltage; pin 32
−7.0
−
−4.5
V
VDDD L. R
positive digital supply voltage for one
channel; pins 27 and 6
4.5
5.0
5.5
V
VDDD
digital supply voltage for both channels;
pin 2
4.5
5.0
5.5
V
VSSD L. R
negative digital supply voltage for one
channel; pins 26 and 7
−4.0
−3.5
−3.0
V
VSSD
negative digital supply voltage for both
channels; pin 31
−5.5
−5.0
−4.5
V
VDDA
positive analog supply voltage; pin 17
4.5
5.0
6.0
V
VSSA
negative analog supply voltage; pin 16
−6.0
−5.0
−4.5
V
VDDD L. R −
VSSD L, R
supply voltage difference between
pins 27, 6 and pins 26, 7
−
−
9.0
V
VSSD L. R - VSSD
supply voltage difference between pins
26, 7 and pin 31
1.3
−
−
V
IDDD L. R
positive digital supply current for one
channel; pins 27 and 6
−
0.1
−
mA
IDDD
digital supply current for both channels;
pin 2
29.0
46
mA
ISSD L. R
negative digital supply current for one
channel; pins 26 and 7
−
−0.1
−
mA
ISSD
negative supply current for both
channels; pin 31
−45
−28.0
−
mA
−IDDA
positive analog supply current; pin 17
−
51.0
63
mA
ISSA
negative analog supply current; pin 16
−51.0
−
mA
PSSR1
power supply rejection ratio
VDDD L, R; note 6 50
−
−
dB
PSSR2
power supply rejection ratio
VDDD; note 6
50
−
−
dB
PSSR3
power supply rejection ratio
VSSD L, R; note 6
60
−
−
dB
PSSR4
power supply rejection ratio
VSSD; note 6
50
−
−
dB
PSSR5
power supply rejection ratio
VDDA; note 6
60
−
−
dB
PSSR6
power supply rejection ratio
VSSA; note 6
60
−
−
dB
Ptot
total power dissipation
−
800
−
mW
VIL
input voltage LOW
−
−
0.5
V
VIH
input voltage HIGH
4.5
−
−
V
IIL
input current LOW
−10
−
10
µA
note 1
−63.0
Clock - Input
September 1991
Vi = 0.5 V
9
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
SYMBOL
PARAMETER
TDA1547
CONDITIONS
MIN
TYP
MAX
UNIT
−10
−
clock input capacitance
−
5
−
pF
clock input frequency
−
−
10
MHz
IIH
input current HIGH
Ci
fCLK
Vi = 4.5 V
10
µA
Channel left/right inputs
VIL
input voltage LOW
−
−
0.5
V
VIH
input voltage HIGH
−
4.5
-
V
IIL
input current LOW
Vi = 0.5 V
−10
−
10
µA
IIH
input current HIGH
Vi = 4.5 V
Ci
channel input capacitance; pins 3, 30
Vref
reference input voltage; pins 8, 25
VOUT(RMS)
(THD + N)/S
−10
−
10
µA
−
5
−
pF
note 2
−
−4 ±0.4
−
V
output voltage (RMS value);
pins 14, 19; pins 15, 18
notes 2 and 3
0.85
1.0
1.15
V
THD + Noise; 0 dB
f = 1 kHz;
−
−101
−96
dB
notes 3 and 4
−
0.0009
0.0016
%
Audio outputs
(THD + N)/S
THD + Noise; 0 dB
20 Hz - 20 kHz;
−
−101
−
dB
notes 3 and 5
−
0.0009
−
%
(THD + N)/S
THD + Noise; −20 dB
f = 1 kHz;
notes 3 and 4
−
−88
−84
dB
(THD + N)/S
THD + Noise; −60 dB
f = 1 kHz;
notes 3 and 4
−
−48
−44
dB
S/N
signal-to-noise ratio
pattern 0101;
notes 3 and 7
109
111
−
dB
S/N
signal-to-noise ratio; “A”-weighting
pattern 0101;
notes 3 and 7
−
113
−
dB
α
channel separation
f = 1 kHz
101
115
−
dB
Timing
tr
rise time clock input
CL = 20 pF
−
5
10
ns
tf
fall time clock input
CL = 20 pF
−
5
10
ns
tCLK L
clock input LOW time
45
−
−
ns
tCLK H
clock input HIGH time
45
−
−
ns
tr
channel input rise time
CL = 20 pF
−
10
15
ns
tf
channel input fall time
CL = 20 pF
−
10
15
ns
tHD
channel input hold time
25
−
−
ns
tSU
channel input set-up time
0
−
−
ns
September 1991
10
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
Notes to the characteristics
1. The substrate voltage must be lower than or to equal than the lowest supply voltage.
2. Output level tracks linearly with both the clock frequency and the reference voltage (Vref L or Vref R).
3. Device measured in differential mode with external components as shown in Fig.5.
4. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 1 kHz digital
sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
5. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 20 Hz to 20 kHz
digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
6. Power supply rejection ratio measured with fripple = 1 kHz and vripple = 100 mV.
7. The specified signal-to-noise ratio includes noise introduced by the application components as shown in Fig.5.
TIMING
tr
handbook, full pagewidth
t CLK H
t CLK L
tf
VIH
V DDD – 1.0 V
CLK
1.0 V
t SU
V IL
t HD
VIH
VDDD – 1.0 V
DATA INPUT
CHANNEL L,
CHANNEL R
DATA STABLE
V IL
V IL
1.0 V
MCD295
Fig.3 Timing waveform.
September 1991
11
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
APPLICATION INFORMATION
system clock
f = 16.9 MHz
system clock
f = 16.9 MHz
L channel
DIGITAL
FILTER
16-bit
audio data,
f = 44.1 kHz
s
SAA7350
20-bit,
f s = 352.8 kHz
TDA1547
1-bit,
f s = 8.47 MHz
R channel
8 x upsampling digital
filter, Astop > 110 dB
24 x upsampling by
zero-order hold,
3rd order noise shaping,
1-bit end quantization
1-bit high-performance
DAC converter
3rd order analog
postfilter, f o = 55 kHz
Butterworth response
MCD296
Fig.4 CD-range bitstream reconstruction system (192 fs over-sampling).
September 1991
12
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
handbook, full pagewidth
bitclock
SCKI
SONY or NPC 8 x Fs
simultaneous mode
20-bit input format
10
wordclock
WSI
9
data left
SDI1
8
DIGITAL FILTER
INTERFACE INPUTS
data right
SDI2
7
IDF1 = LOW
5
IDF2 = HIGH
4
IDF3 = HIGH
3
DOL
42
1-BIT DAC
INTERFACE
OUTPUTS
43
X SYS 2
CLK
stereo 1-bit data
to
TDA1547
DOR
44
INPUT DATA
MODE SELECT
SAA7350
10 Ω
1
32
2
31
3
30
10 Ω
C
(IN R)
DOR
CLK R
10 Ω
+5V
(digital)
C
29
28
5
DOL
6
27
7
26
CLK L
10 Ω
1.5 kΩ
C
8
560 Ω
3.3
kΩ
220
µF
C
SWITCHED
CAPACITOR
NETWORK
SWITCHED
CAPACITOR
NETWORK
C
–5V
(digital)
3.3 kΩ
25
C
9
24
10
23
11
22
12
21
to analog
output stage
220
µF
3.3
kΩ
560 Ω
–5V
(analog)
to analog
output stage
13
20
14
19
15
18
4.7 Ω
4.7 Ω
16
– 5 V (analog)
TDA1547
C
+ 5 V (analog)
17
C
RIGHT CHANNEL
LEFT CHANNEL
Fig.5 Application diagram.
September 1991
+5V
(digital)
C
1.5 kΩ
3.3 kΩ
–5V
(analog)
LOGIC
AND
DRIVERS
LOGIC
AND
DRIVERS
–5V
(digital)
C
(IN L)
4
–5V
(digital)
C
10 Ω
+5V
(digital)
–5V
(digital)
13
C = 100 nF (chip capacitor)
MCD297
September 1991
14
1-BIT
DAC RIGHT
1-BIT
DAC LEFT
820
pF
10
23
820
pF
11
22
12
21
19
220 pF
13 kΩ
220 pF
13 kΩ
14
TDA1547
13 kΩ
220 pF
13 kΩ
15
18
3.3 kΩ
10 kΩ
56 pF
3.3 kΩ
1 kΩ
1 kΩ
33 nF
470 Ω
33 nF
470 Ω
de-emphasis
3.3 nF
1.62 kΩ
de-emphasis
3.3 nF
1.62 kΩ
2.61 kΩ
2.2 nF
100 µH
2.61 kΩ
2.2 nF
100 µH
560 pF
560 pF
100 µF
100 µF
1.5 kΩ
47 Ω
1.5 kΩ
47 Ω
kill
MCD298
audio
output
right
kill
audio
output
left
Dual top-performance bitstream DAC
Fig.6 Post-filter for 192 fs application (f0 = 55 kHz).
3.3 kΩ
10 kΩ
3.3 kΩ
10 kΩ
10 kΩ
56 pF
handbook, full pagewidth
220 pF
Philips Semiconductors
Product specification
TDA1547
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
MCD299
– 80
handbook, full pagewidth
(THD +
N) / S
(dB)
0.01
(THD +
N) / S
(%)
– 100
0.001
level =0 dB
– 120
10 Hz
1 kHz
100 Hz
10 kHz
f signal
Fig.7 (THD + N)/S as a function of signal frequency.
Note: Graph constructed from average measurements values of a small amount of engineering samples.
No guarantee for typical values is implied.
MCD300
– 110
handbook, halfpage
(THD + N) / S
(dB)
– 90
– 70
– 50
– 30
– 10
– 100
– 80
– 60
– 40
– 20
0
signal level (dB)
Fig.8 (THD + N)/S as a function of test signal level.
Note: Graph constructed from average measurement values of a small amount of engineering samples.
No guarantee for typical values is implied.
September 1991
15
0.0001
100 kHz
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
MCD301
handbook, full pagewidth
– 115
crosstalk
(dB)
L
R
R
L
– 120
– 125
– 130
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
f test signal
Fig.9 Inter-channel crosstalk as a function of signal frequency.
Note: Graph constructed from average measurements values of a small amount of engineering samples. No guarantee
for typical values is implied.
September 1991
16
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
PACKAGE OUTLINE
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
ME
seating plane
D
A2 A
A1
L
c
e
Z
(e 1)
w M
b1
MH
b
17
32
pin 1 index
E
1
16
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.8
1.3
0.8
0.53
0.40
0.32
0.23
29.4
28.5
9.1
8.7
1.778
10.16
3.2
2.8
10.7
10.2
12.2
10.5
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT232-1
September 1991
EUROPEAN
PROJECTION
17
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
September 1991
18