AD MT-032

Low Power, Low Noise and Distortion,
Rail-to-Rail Output Amplifiers
ADA4841-1/ADA4841-2
FEATURES
CONNECTION DIAGRAMS
Low power: 1.1 mA/amp
Low wideband noise
2.1 nV/√Hz
1.4 pA/√Hz
Low 1/f noise
7 nV/√Hz @ 10 Hz
13 pA/√Hz @ 10 Hz
Low distortion: −105 dBc @ 100 kHz, VO = 2 V p-p
High speed
80 MHz, −3 dB bandwidth (G = +1)
12 V/μs slew rate
175 ns settling time to 0.1%
Low offset voltage: 0.3 mV maximum
Rail-to-rail output
Power down
Wide supply range: 2.7 V to 12 V
ADA4841-1
–IN 2
7 +VS
+IN 3
6 VOUT
–VS 4
05614-001
TOP VIEW
NC 1 (Not to Scale) 8 POWER DOWN
5 NC
Figure 1. 8-Lead SOIC (R)
ADA4841-1
6
+VS
–VS 2
5
POWER DOWN
+IN 3
4
–IN
05614-099
VOUT 1
Figure 2. 6-Lead SOT-23 (RJ)
ADA4841-2
OUT1 1
8
+VS
–IN1 2
7
OUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
APPLICATIONS
Low power, low noise signal processing
Battery-powered instrumentation
16-bit PulSAR® ADC drivers
NOTES
1. FOR 8-LEAD LFCSP_WD, CONNECT
EXPOSED PADDLE TO GND.
05614-064
TOP VIEW
(Not to Scale)
Figure 3. 8-Lead MSOP (RM), 8-Lead SOIC_N (R), and 8-Lead LFCSP_WD (CP)
GENERAL DESCRIPTION
The ADA4841-1/ADA4841-2 provide the performance required
to efficiently support emerging 16-bit to 18-bit ADCs and are
ideal for portable instrumentation, high channel count, industrial
measurement, and medical applications. The ADA4841-1/
ADA4841-2 are ideally suited to drive the AD7685/AD7686,
16-bit PulSAR ADCs.
–30
–40
VS = ±5V
G = +1
–50
–60
–70
2V p-p THIRD
–80
–90
–100
2V p-p SECOND
–110
–120
0.01
05614-048
The ADA4841-1/ADA4841-2 output can swing to less than
50 mV of either rail. The input common-mode voltage range
extends down to the negative supply. The ADA4841-1/
ADA4841-2 can drive up to 10 pF of capacitive load with
minimal peaking.
The ADA4841-1/ADA4841-2 packages feature RoHS compliant
lead finishes. The amplifiers are rated to work over the
industrial temperature range (−40°C to +125°C).
HARMONIC DISTORTION (dBc)
The ADA4841-1/ADA4841-2 are unity gain stable, low noise
and distortion, rail-to-rail output amplifiers that have a quiescent
current of 1.5 mA maximum. In spite of their low power
consumption, these amplifiers offer low wideband voltage
noise performance of 2.1 nV/√Hz and 1.4 pA/√Hz current noise,
along with excellent spurious-free dynamic range (SFDR) of
−105 dBc at 100 kHz. To maintain a low noise environment at
lower frequencies, the amplifiers have low 1/f noise of 7 nV/√Hz
and 13 pA/√Hz at 10 Hz.
0.1
1
FREQUENCY (MHz)
Figure 4. Harmonic Distortion
Rev. E
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
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IMPORTANT LINKS for the ADA4841-1_4841-2*
Last content update 08/17/2013 01:21 pm
DOCUMENTATION
PARAMETRIC SELECTION TABLES
AN-931: Understanding PulSAR ADC Support Circuitry
AN-649: Using the Analog Devices Active Filter Design Tool
AN-581: Biasing and Decoupling Op Amps in Single Supply Apps
AN-402: Replacing Output Clamping Op Amps with Input Clamping
Amps
AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design
Constraints in Low Voltage High Speed Systems
AN-202: An IC Amplifier User’s Guide to Decoupling, Grounding, and
Making Things Go Right for a Change
MT-060: Choosing Between Voltage Feedback and Current Feedback
Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps
MT-056: High Speed Voltage Feedback Op Amps
MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR
MT-052: Op Amp Noise Figure: Don't Be Mislead
MT-050: Op Amp Total Output Noise Calculations for Second-Order
System
MT-049: Op Amp Total Output Noise Calculations for Single-Pole
System
MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and
Equivalent Noise Bandwidth
MT-047: Op Amp Noise
MT-033: Voltage Feedback Op Amp Gain and Bandwidth
MT-032: Ideal Voltage Feedback (VFB) Op Amp
A Stress-Free Method for Choosing High-Speed Op Amps
FOR THE ADA4841-1:
Find Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
CN-0255 A Complete Single-Supply, 16-Bit, 100 kSPS PulSAR ADC
System Dissipates 8 mW (for the ADA4841-1)
UG-127: Universal Evaluation Board for High Speed Op Amps in
SOT-23-5/SOT-23-6 Packages
UG-101: Evaluation Board User Guide
FOR THE ADA4841-2:
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Board and Kits page for the ADA4841-1
View the Evaluation Board and Kits page for the ADA4841-2
Symbols and Footprints for the ADA4841-1
Symbols and Footprints for the ADA4841-2
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
dBm/dBu/dBv Calculator
Power Dissipation vs Die Temp
ADIsimOpAmp™
Analog Filter Wizard 2.0
OpAmp Stability
ADA4841 SPICE Macro Model, Rev 0, 2/2007
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
Telephone our Customer Interaction Centers toll free:
Americas:
Europe:
China:
India:
Russia:
1-800-262-5643
00800-266-822-82
4006-100-006
1800-419-0108
8-800-555-45-90
Quality and Reliability
Lead(Pb)-Free Data
UG-129: Evaluation Board User Guide
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
SAMPLE & BUY
DESIGN COLLABORATION COMMUNITY
Collaborate Online with the ADI support team and other designers
about select ADI products.
ADA4841-1
ADA4841-2
View Price & Packaging
Request Evaluation Board
Request Samples Check Inventory & Purchase
Find Local Distributors
Follow us on Twitter: www.twitter.com/ADI_News
Like us on Facebook: www.facebook.com/AnalogDevicesInc
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
ADA4841-1/ADA4841-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Headroom Considerations........................................................ 14
Applications....................................................................................... 1
Capacitance Drive ...................................................................... 15
Connection Diagrams...................................................................... 1
Input Protection ......................................................................... 15
General Description ......................................................................... 1
Power-Down Operation ............................................................ 16
Revision History ............................................................................... 2
Applications Information .............................................................. 17
Specifications..................................................................................... 3
Typical Performance Values...................................................... 17
Absolute Maximum Ratings............................................................ 6
16-Bit ADC Driver..................................................................... 17
Thermal Resistance ...................................................................... 6
Reconstruction Filter ................................................................. 17
Maximum Power Dissipation ..................................................... 6
Layout Considerations............................................................... 18
ESD Caution.................................................................................. 6
Ground Plane.............................................................................. 18
Typical Performance Characteristics ............................................. 7
Power Supply Bypassing ............................................................ 18
Theory of Operation ...................................................................... 13
Outline Dimensions ....................................................................... 19
Amplifier Description................................................................ 13
Ordering Guide .......................................................................... 20
DC Errors .................................................................................... 13
Noise Considerations ................................................................. 13
REVISION HISTORY
12/10—Rev. D to Rev. E
Changes to Negative Power Supply Rejection Ration Conditions ..3
Changes to Ordering Guide .......................................................... 20
1/10—Rev. C to Rev. D
Added LFCSP Package.......................................................Universal
Changes to Operating Temperature Range Parameter, Table 4.. 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
3/06—Rev. B to Rev. C
Added SOT-23 Package .....................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Input Protection Section ........................................... 15
Changes to Ordering Guide .......................................................... 20
10/05—Rev. A to Rev. B
Added ADA4841-2.............................................................Universal
Changes to General Description and Features ............................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 4, Table 5, and Figure 4 ..................................... 6
Changes to Figure 6...........................................................................7
Changes to Figure 12, Figure 13, Figure 15, and Figure 16..........8
Deleted Figure 25; Renumber Sequentially ................................ 10
Changes to Figure 24 and Figure 28............................................. 10
Changes to Figure 31...................................................................... 11
Inserted Figure 37; Renumber Sequentially................................ 12
Changes to Amplifier Description Section and Figure 39 ........ 13
Changed DC Performance Considerations Section
to DC Errors Section...................................................................... 13
Changes to Noise Considerations Section .................................. 14
Changes to Headroom Considerations Section and Figure 39 15
Changes to Power-Down Operation Section.............................. 16
Changes to 16-Bit ADC Driver Section,
Figure 48, and Figure 49 ................................................................ 17
Changes to Power Supply Bypassing Section ............................. 18
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
9/05—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Figure 2...........................................................................1
Changes to Figure 12.........................................................................8
Changes to Figure 40...................................................................... 14
Changes to Headroom Considerations Section ......................... 15
7/05—Revision 0: Initial Version
Rev. E | Page 2 of 20
ADA4841-1/ADA4841-2
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 1 kΩ, Gain = +1, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance, Common Mode
Input Resistance, Differential Mode
Input Capacitance, Common Mode
Input Capacitance, Differential Mode
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage
Input Bias Current
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enable
Power Down
Switching Speed
Enable
Power Down
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current Limit
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
VO = 0.02 V p-p
VO = 2 V p-p
G = +1, VO = 9 V step, RL = 1 kΩ
G = +1, VO = 8 V step
G = +1, VO = 8 V step
58
80
3
13
650
1000
MHz
MHz
V/μs
ns
ns
fC = 100 kHz, VO = 2 V p-p, G = +1
fC = 1 MHz, VO = 2 V p-p
f = 100 kHz
f = 100 kHz
−111/−105
−80/−67
2.1
1.4
dBc
dBc
nV/√Hz
pA/√Hz
VO = ±4 V
40
1
3
0.1
120
12
103
Max
300
5.3
0.5
90
25
1
3
Unit
μV
μV/°C
μA
μA
dB
115
MΩ
kΩ
pF
pF
V
dB
70
60
μV
nA
Enabled
Power down
>3.6
<3.2
V
V
POWER DOWN = +5 V
POWER DOWN = −5 V
1
−13
VCM = Δ 4 V
G > +1
Sourcing, VIN = +VS , RL = 50 Ω to GND
Sinking, VIN = −VS , RL = 50 Ω to GND
30% overshoot
−5.1
95
±4.9
+4
Rev. E | Page 3 of 20
95
96
μA
μA
1
40
μs
μs
±4.955
30
60
15
V
mA
mA
pF
2.7
POWER DOWN = +5 V
POWER DOWN = −5 V
+VS = +5 V to +6 V, −VS = −5 V
+VS = +5 V, −VS = −5 V to −6 V
2
−30
1.2
40
110
120
12
1.5
90
V
mA
μA
dB
dB
ADA4841-1/ADA4841-2
TA = 25°C, VS = 5 V, RL = 1 kΩ, Gain = +1, VCM = 2.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3
Input Voltage Noise
Input Current Noise
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance, Common Mode
Input Resistance, Differential Mode
Input Capacitance, Common Mode
Input Capacitance, Differential Mode
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage
Input Bias Current
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enable
Power Down
Switching Speed
Enable
Power Down
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current Limit
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
VO = 0.02 V p-p
VO = 2 V p-p
G = +1, VO = 4 V step, RL = 1 kΩ
G = +1, VO = 2 V step
G = +1, VO = 2 V step
54
80
3
12
175
550
MHz
MHz
V/μs
ns
ns
fC = 100 kHz, VO = 2 V p-p
fC = 1 MHz, VO = 2 V p-p
f = 100 kHz
f = 100 kHz
f = 100 kHz
−109/−105
−78/−66
2.1
1.4
−117
dBc
dBc
nV/√Hz
pA/√Hz
dB
VO = 0.5 V to 4.5 V
40
1
3
0.1
124
10
103
Max
300
5.3
0.4
90
25
1
3
Unit
μV
μV/°C
μA
μA
dB
115
MΩ
kΩ
pF
pF
V
dB
70
70
μV
nA
Enabled
Power down
>3.6
<3.2
V
POWER DOWN = 5 V
POWER DOWN = 0 V
1
−13
VCM = Δ 1.5 V
G > +1
Sourcing, VIN = +VS, RL = 50 Ω to VCM
Sinking, VIN = −VS, RL = 50 Ω to VCM
30% overshoot
−0.1
88
0.08 to 4.92
+4
Rev. E | Page 4 of 20
95
96
μA
μA
1
40
μs
μs
0.029 to 4.974
30
60
15
V
mA
mA
pF
2.7
POWER DOWN = 5 V
POWER DOWN = 0 V
+VS = +5 V to +6 V, −VS = 0 V
+VS = +5 V, −VS = 0 V to −1 V
2
−30
1.1
35
110
120
12
1.4
70
V
mA
μA
dB
dB
ADA4841-1/ADA4841-2
TA = 25°C, VS = 3 V, RL = 1 kΩ, Gain =+1, VCM = 1.5 V, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance, Common Mode
Input Resistance, Differential Mode
Input Capacitance, Common Mode
Input Capacitance, Differential Mode
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage
Input Bias Current
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enable
Power Down
Switching Speed
Enable
Power Down
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current Limit
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
VO = 0.02 V p-p
G = +1, VO = 2 V step, RL = 1 kΩ
G = +1, VO = 1 V step
G = +1, VO = 1 V step
52
10
80
12
120
250
MHz
V/μs
ns
ns
fC = 100 kHz, VO = 1 V p-p
fC = 1 MHz, VO = 1 V p-p
f = 100 kHz
f = 100 kHz
−97/−100
−79/−80
2.1
1.4
dBc
dBc
nV/√Hz
pA/√Hz
VO = 0.5 V to 2.5 V
40
1
3
0.1
123
101
Max
300
5.3
0.5
90
25
1
3
Unit
μV
μV/°C
μA
μA
dB
115
MΩ
kΩ
pF
pF
V
dB
70
60
μV
nA
Enabled
Power down
>1.6
<1.2
V
POWER DOWN = 3 V
POWER DOWN = 0 V
1
−10
−0.1
86
VCM = Δ 0.4 V
G > +1
Sourcing, VIN = +VS, RL = 50 Ω to VCM
Sinking, VIN = −VS, RL = 50 Ω to VCM
30% overshoot
0.045 to 2.955
+2
Rev. E | Page 5 of 20
95
96
μA
μA
1
40
μs
μs
0.023 to 2.988
30
60
30
V
mA
mA
pF
2.7
POWER DOWN = 3 V
POWER DOWN = 0 V
+VS = +3 V to +4 V, −VS = 0 V
+VS = +3 V, −VS = 0 V to −1 V
2
−30
1.1
25
110
120
12
1.3
60
V
mA
μA
dB
dB
ADA4841-1/ADA4841-2
ABSOLUTE MAXIMUM RATINGS
PD = Quiescent Power + (Total Drive Power − Load Power)
Table 4.
Rating
12.6 V
See Figure 5
−VS − 0.5 V to +VS + 0.5 V
±1.8 V
−65°C to +125°C
−40°C to +125°C
JEDEC J-STD-20
150°C
⎛V V
PD = (VS × I S ) + ⎜⎜ S × OUT
RL
⎝ 2
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
RL
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θJA.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC_N
(125°C/W), the 6-lead SOT-23 (170°C/W), 8-lead MSOP
(145°C/W), and 8-lead LFCSP_WD (103°C/W) on a JEDEC
standard 4-layer board. θJA values are approximations.
2.0
Unit
°C/W
°C/W
°C/W
°C/W
MAXIMUM POWER DISSIPATION (W)
θJA
125
170
130
103
(VS /4 )2
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Table 5. Thermal Resistance
Package Type
8-lead SOIC_N
6-Lead SOT-23
8-lead MSOP
8-Lead LFCSP_WD
⎞ VOUT 2
⎟−
⎟
RL
⎠
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4841-1/
ADA4841-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
LFCSP
1.5
SOIC
MSOP
1.0
SOT-23
0.5
05614-061
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Junction Temperature
0
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
AMBIENT TEMPERATURE (°C)
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
Rev. E | Page 6 of 20
ADA4841-1/ADA4841-2
TYPICAL PERFORMANCE CHARACTERISTICS
RL = 1 kΩ, unless otherwise noted.
3
VOUT = 2V pp
VS = 5V
G = +1
VS = 5V
VIN = 20mV p-p
G = +1
+25°C
–40°C
0
0
GAIN (dB)
G = +10
–3
G = +2
–6
+125°C
–3
–6
–12
0.1
–9
0.1
10
1
05614-028
–9
05614-021
NORMALIZED CLOSED-LOOP GAIN (dB)
3
1
FREQUENCY (MHz)
Figure 6. Large Signal Frequency Response vs. Gain
6
VIN = 20mV p-p
G = +1
VS = 5V
100
10
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response vs. Temperature
2
20pF
20pF
WITH
100Ω SNUBBER
1
VIN = 20mV p-p
G = +1
VS = +3V
VS = +5V
VS = ±5V
0
–1
0
0pF
–3
GAIN (dB)
10pF
–2
–3
–4
05614-026
–6
–9
0.1
1
10
–5
05614-029
CLOSED-LOOP GAIN (dB)
3
–6
0.1
100
1
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response vs. Supply Voltage
Figure 7. Small Signal Frequency Response vs. Capacitive Load
VIN = 20mV p-p
VS = 5V
G = –1
3
G = +1
VS = ±5V
G = +1
10mV p-p
0
G = +10
0
GAIN (dB)
–3
–6
–3
2V p-p
400mV p-p
20mV p-p
–6
100mV p-p
–12
0.1
1
10
100
–9
0.1
05614-014
–9
05614-027
NORMALIZED CLOSED-LOOP GAIN (dB)
3
100
10
FREQUENCY (MHz)
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response vs. Gain
Figure 11. Frequency Response for Various VOUT
Rev. E | Page 7 of 20
100
ADA4841-1/ADA4841-2
–20
–40
–40
100
PHASE
80
–60
–80
60
40
–100
20
–120
0
–140
–20
10
100
1k
10k
100k
1M
10M
05614-042
OPEN-LOOP GAIN (dB)
–30
–160
100M
FREQUENCY (Hz)
VOUT = 2V p-p
G = +2
–50
+5V SECOND
–60
–70
+3V SECOND
–80
–90
+3V THIRD
–100
±5V THIRD
–110
+5V THIRD
–120
–130
0.01
05614-047
MAGNITUDE
120
0
HARMONIC DISTORTION (dBc)
VS = 5V
OPEN-LOOP PHASE (Degrees)
140
±5V SECOND
1
0.1
FREQUENCY (MHz)
Figure 15. Harmonic Distortion vs. Frequency for Various Supplies
Figure 12. Open-Loop Gain and Phase vs. Frequency
–30
10
VS = + 5V
VOUT = 2V p-p
VS = ±5V
–50
VOLTAGE NOISE (nV/ Hz)
G = +5 THIRD
–60
–70
–90
G = +2 SECOND
G = +5 SECOND
–100
G = +1 SECOND
–110
G = +1 THIRD
–120
G = +2 THIRD
–130
0.01
1
0.1
1
10
FREQUENCY (MHz)
05614-034
–80
05614-045
HARMONIC DISTORTION (dBc)
–40
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 16. Voltage Noise vs. Frequency
Figure 13. Harmonic Distortion vs. Frequency for Various Gains
–30
VS = ±5V
8V p-p SECOND
CURRENT NOISE (pA/ Hz)
–50
8V p-p THIRD
–60
–70
4V p-p THIRD
4V p-p SECOND
–90
–100
2V p-p THIRD
–110
–120
0.01
1
2V p-p SECOND
0.1
1
0.1
10
FREQUENCY (MHz)
05614-018
–80
10
05614-046
HARMONIC DISTORTION (dBc)
–40
100
VS = ±5V
G = +1
100
1k
10k
100k
FREQUENCY (Hz)
Figure 14. Harmonic Distortion vs. Frequency for Various Output Voltages
Rev. E | Page 8 of 20
Figure 17. Current Noise vs. Frequency
1M
ADA4841-1/ADA4841-2
55
0.25
45
0.24
G = +2
TIME = 50ns/DIV
VS = +3V
VS = +5V
40
OUTPUT VOLTAGE (V)
35
30
25
20
15
10
0.23
VS = ±5V
0.22
0.21
05614-053
0.20
5
0
–5
–4
–2
0
2
4
05614-033
NUMBER OF PARTS
COUNT = 190
50 x = 0.36μV/°C
σ = 1.21μV/°C
0.19
6
OFFSET DRIFT DISTRIBUTION (μV/°C)
Figure 21. Small Signal Transient Response for Various Supplies
Figure 18. Input Offset Voltage Drift Distribution
10
0.15
G = +1
VS = 5V
9
0.14
7
OUTPUT VOLTAGE (V)
NONLINEARITY (μV)
8
6
5
4
3
G = +2
VIN = 20mV p-p
TIME = 50ns/DIV
0pF
0.13
10pF
0.12
0.11
2
0
1
2
3
0.09
5
4
05614-031
0
20pF
47pF
0.10
05614-013
1
VIN (V)
Figure 19. Nonlinearity vs. VIN
0.130
0.125
60
0.120
OUTPUT VOLTAGE (V)
80
40
20
0
0.115
–40
0.095
–2
0
2
4
VS = 5V
0.105
0.100
–4
VS = 3V
0.110
–20
–60
–6
G = +1
TIME = 50ns/DIV
0.090
6
VOUT (V)
Figure 20. Input Error Voltage vs. Output Voltage
Figure 23. Small Signal Transient Response for Various Supplies
Rev. E | Page 9 of 20
05614-030
VS = ±5
05614-036
VOFFSET (μV)
100
Figure 22. Small Signal Transient Response for Various Capacitive Loads
ADA4841-1/ADA4841-2
4.5
VS = 5V
G = +1
TIME = 200ns/DIV
VIN
5
VOUT
3.5
+125°C
OUTPUT VOLTAGE (V)
4
3
2
1
2.5
–40°C
2.0
1.5
0
2.0
1.5
VOUT
2
1
05614-023
–1
VOUT
0.5
0
0
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
–2.0
Figure 28. Settling Time
6
VS = ±5V
VOUT = 2V p-p
TIME = 100ns/DIV
1.2
POWER DOWN PIN
+25°C
5
POWER DOWN PIN (V)
G = +2
0.5
G = +1
0
–0.5
05614-022
–1.0
–1.5
0.5
–0.5
Figure 25. Output Overdrive Recovery
1.0
VOUT (EXPANDED)
VIN
1.0
4
0.8
–40°C
+125°C
3
0.6
2
0.4
1
0.2
0
–1
VS = 5V
G = +1
VIN = 1VDC
TIME = 200ns/DIV
Figure 29. Power-Up Time vs. Temperature
Figure 26. Large Signal Transient Response for Various Gains
Rev. E | Page 10 of 20
0
–0.2
VOUT (V)
0
1.5
VIN AND V OUT (V)
EXPANDED V OUT (mV)
3
2.0
1.0
1.0
4
1.5
VS = 5V
G = +1
VOUT = 2V p-p
TIME = 100ns/DIV
05614-041
VS = 5V
G = +2
TIME = 100ns/DIV
VIN × 2
5
Figure 27. Slew Rate vs. Temperature
05614-039
6
05614-016
0.5
Figure 24. Input Overdrive Recovery
INPUT AND OUTPUT VOLTAGE (V)
+25°C
3.0
1.0
0
–1
OUTPUT VOLTAGE (V)
G = +2
VS = 5
TIME = 100ns/DIV
4.0
05614-019
INPUT AND OUTPUT VOLTAGE (V)
6
ADA4841-1/ADA4841-2
0.8
3
0.6
+125°C
2
+25°C
0.4
1
–40°C
0.2
0
POWER DOWN PIN
05614-040
0
–1
POWER SUPPLY REJECTION (dB)
4
0
VOUT (V)
POWER DOWN PIN
5
–0.2
VS = 5V
–20
–40
+PSR
–60
–80
–PSR
–100
–120
100
1k
10k
100k
1M
10M
100M
10M
100M
FREQUENCY (Hz)
Figure 30. POWER DOWN Time vs. Temperature
Figure 33. PSR vs. Frequency
100
+125°C
SUPPLY CURRENT/AMPLIFIER (mA)
1.4
1.2
+25°C
1.0
0.8
–40°C
0.6
0.4
0.2
–0.2
05614-020
0
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VS = 5V
10
1
0.1
0.01
05614-024
VS = 5V
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
1.6
0.001
100
5.0
1k
10k
1M
Figure 34. Output Impedance vs. Frequency
Figure 31. Supply Current per Amplifier vs. POWER DOWN Pin Voltage
0
100k
FREQUENCY (Hz)
POWER DOWN PIN (V)
40
VS = ±5V
G = +1
30
INPUT OFFSET VOLTAGE (μV)
–20
–40
–60
–80
VS = +5V
20
10
0
VS = ±5V
–10
–20
VS = +3V
–30
–100
1k
10k
100k
1M
10M
100M
–40
–50
–40
05614-057
–120
100
05614-009
COMMON-MODE REJECTION (dB)
POWER DOWN PIN (V)
1.2
VS = 5V
G = +1
VIN = 1VDC
1.0
TIME = 10μs/DIV
05614-025
6
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 32. CMR vs. Frequency
Figure 35. Input Offset Voltage vs. Temperature for Various Supplies
Rev. E | Page 11 of 20
3.6
–40
3.5
G = +1
–50 V = 5V
S
RL = 1kΩ
–60
VS = +5V
CROSSTALK (dB)
3.4
VS = +3V
3.3
VS = ±5V
–70
–80
–90
–110
3.2
05614-058
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–130
–140
10k
Figure 36. Input Bias Current vs. Temperature for Various Supplies
1.5
1.4
1.3
1.2
VS = ±5V
1.0
VS = +5V
05614-059
0.9
VS = +3V
0.8
–40
–25
–10
5
20
35
50
65
80
95
110
100k
1M
10M
FREQUENCY (Hz)
Figure 38. Crosstalk Output to Output
1.6
SUPPLY CURRENT (mA)
B TO A
–120
3.1
–40
1.1
A TO B
–100
05614-062
INPUT BIAS CURRENT (μA)
ADA4841-1/ADA4841-2
125
TEMPERATURE (°C)
Figure 37. Supply Current vs. Temperature for Various Supplies
Rev. E | Page 12 of 20
100M
1G
ADA4841-1/ADA4841-2
THEORY OF OPERATION
AMPLIFIER DESCRIPTION
The ADA4841-1/ADA4841-2 are low power, low noise,
precision voltage-feedback op amps for single or dual voltage
supply operation. The ADA4841-1/ADA4841-2 are fabricated
on ADI’s second generation XFCB process and feature trimmed
supply current and offset voltage. The 2.1 nV/√Hz voltage noise
(very low for a 1.1 mA supply current amplifier), 40 μV offset
voltage, and sub 1 μV/°C offset drift is accomplished with an
input stage made of an undegenerated PNP input pair driving a
symmetrical folded cascode. A rail-to-rail output stage provides
the maximum linear signal range possible on low voltage
supplies and has the current drive capability needed for the
relatively low resistance feedback networks required for low
noise operation. CMRR, PSRR, and open-loop gain are all
typically above 100 dB, preserving the precision performance in
a variety of configurations. Gain bandwidth is kept high for this
power level to preserve the outstanding linearity performance
for frequencies up to 100 kHz. The ADA4841-1 has a powerdown function to further reduce power consumption. All this
results in a low noise, power efficient, precision amplifier that is
well-suited for high resolution and precision applications.
Figure 39 shows a typical connection diagram and the major dc
error sources. The ideal transfer function (all error sources set
to 0 and infinite dc gain) can be written as
VCM VP − VPNOM VOUT ⎞ ⎛ RF
⎛
+
+
⎜ VOFFSETNOM +
⎟ × ⎜1 +
CMRR
PSRR
A ⎠ ⎜⎝ RG
⎝
⎞
⎟ × VIP
⎟
⎠
⎛R
− ⎜⎜ F
⎝ RG
⎞
⎟ × VIN
⎟
⎠
(1)
RF
where:
VOFFSETNOM is the offset voltage at the specified supply voltage.
This is measured with the input and output at midsupply.
VCM is the common-mode voltage.
VP is the power supply voltage.
VpNOM is the specified power supply voltage.
CMRR is the common-mode rejection ratio.
PSRR is the power supply rejection ratio.
The output error due to the input currents can be estimated as
⎛ R
VOUTERROR = (RF || RG ) × ⎜⎜1 + F
⎝ RG
⎞
⎛ R
⎟ I B − − RS × ⎜ 1 + F
⎟
⎜ R
G
⎠
⎝
⎞
⎟ × I B+
⎟
⎠
Note that setting RS equal to RF||RG compensates for the voltage
error due to the input bias current.
Figure 40 illustrates the primary noise contributors for the
typical gain configurations. The total rms output noise is
the root-mean-square of all the contributions.
+ VOUT –
RS
RF
05614-004
IB+
vn _ RG = 4kT × RG
Figure 39. Typical Connection Diagram and DC Error Sources
vn _ RF = 4kT × RF
ven
RG
ien
This reduces to the familiar forms for inverting and
noninverting op amp gain expressions
⎛ R
= ⎜⎜1 + F
⎝ RG
⎞
⎟ ×VIP
⎟
⎠
vn _ RS = 4kT × RS
(2)
⎞
⎟ ×VIN
⎟
⎠
(3)
(Inverting gain, VIP = 0 V)
Rev. E | Page 13 of 20
+ vout_en –
RS
ien
(Noninverting gain, VIN = 0 V)
⎛ − RF
VOUT = ⎜⎜
⎝ RG
(5)
NOISE CONSIDERATIONS
+ VOS –
RG
IB–
VOUT
⎞ (4)
⎟
⎟
⎠
Figure 40. Noise Sources in Typical Connection
05614-005
⎛ R
VOUT = ⎜⎜1 + F
⎝ RG
– VIP +
VOUTERROR =
A is the dc open-loop gain.
DC ERRORS
– VIN +
The total output voltage error is the sum of errors due to the
amplifier offset voltage and input currents. The output error
due to the offset voltage can be estimated as
ADA4841-1/ADA4841-2
The output noise spectral density can be calculated by
vout _ en =
[
]
2
(6)
where:
k is Boltzmann’s Constant.
T is the absolute temperature, degrees Kelvin.
300
260
ien is the amplifier input current noise spectral density, pA/√Hz.
RS is the source resistance as shown in Figure 40.
RF and RG are the feedback network resistances, as shown in
Figure 40.
1000
100
140
AMPLIFIER + RESISTOR NOISE
10
20
100
1k
–60
–100
–140
–180
–220
–260
–300
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.40
4.60
4.80 5.00
COMMON-MODE VOLTAGE (V)
Figure 42. +CMV vs. Common-Mode Error vs. VOS
0
–50
–100
–150
–40°C
–200
–250
+25°C
–300
–350
–400
–450
+125°C
–500
–550
–600
–650
–700
–750
–800
–6.00 –5.80 –5.60 –5.40 –5.20 –5.00 –4.80 –4.60 –4.40 –4.20 –4.00
05614-007
10k
–40°C
–20
1
0.1
10
+25°C
60
TOTAL AMPLIFIER NOISE
SOURCE RESISTANCE NOISE
+125°C
100
05614-054
NOISE (nV/ Hz)
180
COMMON-MODE ERROR (μV)
Source resistance noise, amplifier voltage noise (ven), and the
voltage noise from the amplifier current noise (ien × RS) are
all subject to the noise gain term (1 + RF/RG). Note that with a
2.1 nV/√Hz input voltage noise and 1.4 pA/√Hz input current,
the noise contributions of the amplifier are relatively small for
source resistances between approximately 200 Ω and 30 kΩ.
Figure 41 shows the total RTI noise due to the amplifier vs. the
source resistance. In addition, the value of the feedback resistors
used impacts the noise. It is recommended to keep the value of
feedback resistors between 250 Ω and 1 kΩ to keep the total
noise low.
COMMON-MODE ERROR (μV)
ven is the amplifier input voltage spectral density, nV/√Hz.
220
05614-055
2
⎛R ⎞
⎛ R ⎞
2
2
4 kTRf + ⎜⎜1 + F ⎟⎟ 4kTRs + ien RS 2 + ven + ⎜⎜ F ⎟⎟ 4 kTRg + ien 2 RF 2
R
G
⎝ RG ⎠
⎠
⎝
The input stage positive limit is almost exactly a volt below the
positive supply at room temperature. Input voltages above that
start to show clipping behavior. The positive input voltage limit
increases with temperature with a coefficient of about 2 mV/°C.
The lower supply limit is nominally below the minus supply;
therefore, in a standard gain configuration, the output stage
limits the signal headroom on the negative supply side. Figure 42
and Figure 43 show the nominal CMRR behavior at the limits of
the input headroom for three temperatures—this is generated
using the subtractor topology shown in Figure 44, which avoids
the output stage limitation.
COMMON-MODE VOLTAGE (V)
Figure 43. −CMV vs. Common-Mode Error vs. VOS
100k
– VCM +
SOURCE RESISTANCE (Ω)
+ VOUT –
05614-051
Figure 41. RTI Noise vs. Source Resistance
HEADROOM CONSIDERATIONS
The ADA4841-1/ADA4841-2 are designed to provide maximum
input and output signal ranges with 16-bit to 18-bit dc linearity.
As the input or output headroom limits are reached, the signal
linearity degrades.
Rev. E | Page 14 of 20
Figure 44. Common-Range Subtractor
ADA4841-1/ADA4841-2
60
Figure 45 shows the amplifier frequency response as a G = −1
inverter with the input and output stage biased near the
negative supply rail.
VS– = –150mV
VS– = –100mV
VS– = –200mV
VS– = –50mV
30
20
VS– = –20mV
–3
10
G = +2
G = +5
–6
0
10
100
10000
1000
CAPACITANCE LOAD (pF)
05614-017
–9
–12
0.1
05614-050
GAIN (dB)
0
40
1
10
100
FREQUENCY (MHz)
Figure 45. Small Signal Frequency Response vs. Negative Supply Bias
The input voltage (VIN) and reference voltage (VIP) are both at
0 V, (see Figure 39). +VS is biased at +5 V, and −VS is swept
from −200 mV to −20 mV. With the input and output voltages
biased 200 mV above the bottom rail, the G = −1 inverter
frequency response is not much different from what is seen
with the input and output voltages biased near midsupply.
At 150 mV bias, the frequency response starts to decrease
and at 20 mV, the inverter bandwidth is less than half its
nominal value.
Figure 46. Series Resistance vs. Capacitance Load
INPUT PROTECTION
The ADA4841-1/ADA4841-2 are fully protected from ESD
events, withstanding human body model ESD events of 2.5 keV
and charge device model events of 1 keV with no measured
performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 47.
VCC
BIAS
ESD
VP
CAPACITANCE DRIVE
A small resistor in series with the amplifier output and the
capacitive load mitigates the problem. Figure 46 plots the
recommended series resistance vs. capacitance for gains
of +1, +2, and +5.
VN
ESD
Capacitance at the output of an amplifier creates a delay within
the feedback path that, if within the bandwidth of the loop, can
create excessive ringing and oscillation. The G = +1 follower
topology has the highest loop bandwidth of any typical
configuration and, therefore, is the most vulnerable to the
effects of capacitance load.
ESD
ESD
VEE
TO REST OF AMPLIFIER
05614-006
3
VS+ = 5V
G = –1
VIN = 20mV p-p
SERIES RESISTANCE (Ω)
6
G = +1
50
Figure 47. Input Stage and Protection Diodes
For differential voltages above approximately 1.4 V, the diode
clamps start to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages need to be
sustained across the input terminals, it is recommended that the
current through the input clamps be limited to below 150 mA.
Series input resistors sized appropriately for the expected
differential overvoltage provide the needed protection.
The ESD clamps start to conduct for input voltages more than
0.7 V above the positive supply and input voltages more than
0.7 V below the negative supply. It is recommended that the
fault current be limited to less than 150 mA if an overvoltage
condition is expected.
Rev. E | Page 15 of 20
ADA4841-1/ADA4841-2
POWER-DOWN OPERATION
Figure 48 shows the ADA4841-1 power-down circuitry. If the
POWER DOWN pin is left unconnected, then the base of the
input PNP transistor is pulled high through the internal pull-up
resistor to the positive supply, and the part is turned on. Pulling
the POWER DOWN pin approximately 1.7 V below the positive
supply turns the part off, reducing the supply current to
approximately 40 μA.
The POWER DOWN pin is protected with ESD clamps,
as shown in Figure 48. Voltages beyond the power supplies
cause these diodes to conduct. The guidelines for limiting the
overload current in the input protection section should also be
followed for the POWER DOWN pin.
VCC
IBIAS
ESD
POWER DOWN
ESD
VEE
05614-052
TO
AMPLIFIER
BIAS
Figure 48. POWER DOWN Circuit
Rev. E | Page 16 of 20
ADA4841-1/ADA4841-2
APPLICATIONS INFORMATION
TYPICAL PERFORMANCE VALUES
RECONSTRUCTION FILTER
To reduce design time and eliminate uncertainty Table 6
provides a convenient reference for typical gains, component
values, and performance parameters.
The ADA4841-1/ADA4841-2 can also be used as a reconstruction
filter at the output of DACs for suppression of the sampling
frequency. The filter shown in Figure 49 is a two-pole, 500 kHz
Sallen-Key LPF with a fixed gain of G = +1.6.
16-BIT ADC DRIVER
C2
1320pF
The combination of low noise, low power, and high speed
make the ADA4841-1/ADA4841-2 the perfect driver solution
for low power, 16-bit ADCs, such as the AD7685. Figure 50
shows a typical 16-bit single-supply application.
+5V
There are different challenges to a single-supply, high resolution
design, and the ADA4841-1/ADA4841-2 address these nicely.
In a single-supply system, a main challenge is using the
amplifier in buffer mode with the lowest output noise and
preserving linearity compatible with the ADC.
0.1μF
R1
249Ω
INPUT
R2
249Ω
C1
1320pF
U1
10μF
R4
499Ω
05614-044
–5V
R3
840Ω
Figure 49. Two-Pole 500 kHz Reconstruction Filter Schematic
Setting the resistors and capacitors equal to each other greatly
simplifies the design equations for the Sallen-Key filter. The corner
frequency, or −3 dB frequency, can be described by the equation
fC =
1
2πR1C1
The quality factor, or Q, is shown in the equation
Q=
1
3−K
For minimum peaking, set Q equal to 0.707.
The gain, or K, of the amplifier is
K=
R4
+1
R3
Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response.
+5.2V
100nF
ADR364
100nF
10μF
100nF
0V TO 4.096V
OUTPUT
0.1μF
Rail-to-rail input amplifiers are usually higher noise than the
ADA4841-1/ADA4841-2 and cannot be used in this mode
because of the nonlinear region around the crossover point of
their input stages. The ADA4841-1/ADA4841-2, which have no
crossover region but have a wide linear input range from 100 mV
below ground to 1 V below positive rail, solve this problem, as
shown in Figure 50. The amplifier, when configured as a
follower, has a linear signal range from 0.25 V above the minus
supply voltage (limited by the amplifier’s output stage) to 1 V
below the positive supply (limited by the amplifier input stage).
A 0 V to +4.096 V signal range can be accommodated with a
positive supply as low as +5.2 V and a negative power supply of
−0.25 V. The 5.2 V supply also allows the use of a small, low
dropout, low temperature drift ADR364 reference voltage. If
ground is used as the amplifier negative supply, then note that at
the low end of the input range close to ground, the ADA4841-1/
ADA4841-2 exhibit substantial nonlinearity, as any rail-to-rail
output amplifier. The ADA4841-1/ADA4841-2 drive a onepole, low-pass filter. This filter limits the already very low noise
contribution from the amplifier to the AD7685.
ADA4841
10μF
33Ω
REF
VDD
IN+
AD7685
2.7nF
–0.25V
IN–
SCK
SDO
CNV
05614-060
GND
VIO
SDI
Figure 50. ADC Driver Schematic
Rev. E | Page 17 of 20
ADA4841-1/ADA4841-2
Table 6. Recommended Values and Typical Performance
Gain
+1
+2
−1
+5
+10
+20
RF (Ω)
0
499
499
499
499
499
RG (Ω)
N/A
499
499
124
54.9
26.1
−3 dB BW (MHz)
77
34
38
11
5
2.3
Slew Rate (V/μs)
12.5
12.5
12.5
12
12
11.2
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors, are good choices for filter elements. Figure 51
shows the filter response.
5
0
–5
GAIN (dB)
–10
–15
–20
–25
–30
–40
0.03
05614-043
–35
0.1
1
FREQUENCY (MHz)
10
Figure 51. Filter Frequency Response
LAYOUT CONSIDERATIONS
To ensure optimal performance, careful and deliberate attention
must be paid to the board layout, signal routing, power supply
bypassing, and grounding.
GROUND PLANE
It is important to avoid ground in the areas under and around
the input and output of the ADA4841-1/ADA4841-2. Stray
capacitance created between the ground plane and the input
and output pads of a device are detrimental to high speed
amplifier performance. Stray capacitance at the inverting input,
along with the amplifier input capacitance, lowers the phase
margin and can cause instability. Stray capacitance at the output
creates a pole in the feedback loop. This can reduce phase
margin and can cause the circuit to become unstable.
Peaking
(dB)
0.9
0.3
0.4
0
0
0
Output Noise ADA4841-1/
ADA4841-2 Only (nV/√Hz)
2
4
4
10
20
40
Total Output Noise
Including Resistors (nV/√Hz)
2
5.73
5.73
11.9
21.1
42.2
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect in the performance
of the ADA4841-1/ADA4841-2. A parallel connection of
capacitors from each of the power supply pins to ground works
best. A typical connection is shown in Figure 49. Smaller value
capacitors offer better high frequency response where larger
value electrolytics offer better low frequency performance.
Paralleling different values and sizes of capacitors helps to
ensure that the power supply pins are provided a low ac impedance
across a wide band of frequencies. This is important for minimizing
the coupling of noise into the amplifier. This can be especially
important when the amplifier PSR is starting to roll off—the
bypass capacitors can help lessen the degradation in PSR
performance.
Starting directly at the ADA4841-1/ADA4841-2 power supply
pins, the smallest value capacitor should be placed on the same
side of the board as the amplifier, and as close as possible to the
amplifier power supply pin. The ground end of the capacitor
should be connected directly to the ground plane. Keeping the
capacitors’ distance short but equal from the load is important
and can improve distortion performance. This process should
be repeated for the next largest value capacitor.
It is recommended that a 0.1 μF ceramic 0508 case be used. The
0508 case size offers low series inductance and excellent high
frequency performance. A 10 μF electrolytic capacitor should be
placed in parallel with the 0.1 μF capacitor. Depending on the
circuit parameters, some enhancement to performance can be
realized by adding additional capacitors. Each circuit is different
and should be individually analyzed for optimal performance.
Rev. E | Page 18 of 20
ADA4841-1/ADA4841-2
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8
3.20
3.00
2.80
5
1
5.15
4.90
4.65
4
45°
PIN 1
IDENTIFIER
8°
0°
0.65 BSC
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.95
0.85
0.75
0.15
0.05
COPLANARITY
0.10
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15° MAX
1.10 MAX
6°
0°
0.40
0.25
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
PIN 1
INDICATOR
3.00
2.80
2.60
0.95 BSC
1.90
BSC
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
4°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 54. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev. E | Page 19 of 20
0.55
0.45
0.35
121608-A
1.30
1.15
0.90
0.80
0.55
0.40
10-07-2009-B
4.00 (0.1574)
3.80 (0.1497)
3.20
3.00
2.80
ADA4841-1/ADA4841-2
2.54
2.44
2.34
3.10
3.00 SQ
2.90
0.50 BSC
8
5
0.50
0.40
0.30
0.80
0.75
0.70
1
4
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
1.80
1.70
1.60
EXPOSED
PAD
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.30
0.25
0.20
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION
OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
111809-A
PIN 1 INDEX
AREA
Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4841-1YRZ
ADA4841-1YRZ-R7
ADA4841-1YRZ-RL
ADA4841-1YRJZ-R2
ADA4841-1YRJZ-R7
ADA4841-1YRJZ-RL
ADA4841-2YRMZ
ADA4841-2YRMZ-R7
ADA4841-2YRMZ-RL
ADA4841-2YRZ
ADA4841-2YRZ-R7
ADA4841-2YRZ-RL
ADA4841-2YCPZ-R2
ADA4841-2YCPZ-R7
ADA4841-2YCPZ-RL
ADA4841-1YR-EBZ
ADA4841-1YRJ-EBZ
ADA4841-2YRM-EBZ
ADA4841-2YR-EBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05614–0–12/10(E)
Rev. E | Page 20 of 20
Package Option
R-8
R-8
R-8
RJ-6
RJ-6
RJ-6
RM-8
RM-8
RM-8
R-8
R-8
R-8
CP-8-11
CP-8-11
CP-8-11
Ordering Quantity
1
1,000
2,500
250
3,000
10,000
1
1,000
3,000
1
1,000
2,500
250
1,500
5,000
Branding
HQB
HQB
HQB
HRB
HRB
HRB
HRB
HRB
HRB