AD ADA4898-2YRDZ-R7

FEATURES
CONNECTION DIAGRAM
ADA4898-1
Ultralow noise
0.9 nV/√Hz
2.4 pA/√Hz
1.2 nV/√Hz at 10 Hz
Ultralow distortion: −93 dBc at 500 kHz
Wide supply voltage range: ±5 V to ±16 V
High speed
−3 dB bandwidth: 65 MHz (G = +1)
Slew rate: 55 V/µs
Unity gain stable
Low input offset voltage: 160 µV maximum
Low input offset voltage drift: 1 μV/°C
Low input bias current: −0.1 µA
Low input bias current drift: 2 nA/°C
Supply current: 8 mA
Power-down feature for single 8-lead package
TOP VIEW
(Not to Scale)
8
PD
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
NC = NO CONNECT
07037-001
NC 1
–IN 2
Figure 1. Single 8-Lead ADA4898-1 SOIC_N_EP (RD-8-1)
ADA4898-2
TOP VIEW
(Not to Scale)
VOUT1 1
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
07037-050
Data Sheet
High Voltage, Low Noise, Low Distortion,
Unity-Gain Stable, High Speed Op Amp
ADA4898-1/ADA4898-2
Figure 2. Dual 8-Lead ADA4898-2 SOIC_N_EP (RD-8-2)
APPLICATIONS
Instrumentation
Active filters
DAC buffers
SAR ADC drivers
Optoelectronics
GENERAL DESCRIPTION
CURRENT
VOLTAGE
1
1
0.1
1
10
100
1k
10k
0.1
100k
FREQUENCY (Hz)
CURRENT NOISE (pA/√Hz)
The ADA4898 is available in an 8-lead SOIC package that
features an exposed metal paddle to improve power dissipation and
heat transfer to the negative supply plane. This EPAD offers a
significant thermal relief over traditional plastic packages. The
ADA4898 is rated to work over the extended industrial
temperature range of −40°C to +105°C.
10
07037-002
With the wide supply voltage range, low offset voltage, and wide
bandwidth, the ADA4898 is extremely versatile, and it features a
cancellation circuit that reduces input bias current.
10
VOLTAGE NOISE (nV/√Hz)
The ADA4898 is an ultralow noise and distortion, unity gain
stable, voltage feedback op amp that is ideal for use in 16-bit and
18-bit systems with power supplies from ±5 V to ±16 V. The
ADA4898 features a linear, low noise input stage and internal
compensation that achieves high slew rates and low noise.
Figure 3. Input Voltage Noise and Current Noise vs. Frequency
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Fax: 781.461.3113 ©2008-2012 Analog Devices, Inc. All rights reserved.
ADA4898-1/ADA4898-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Applications ....................................................................................... 1
PD (Power-Down) Pin for the ADA4898-1............................ 14
Connection Diagram ....................................................................... 1
0.1 Hz to 10 Hz Noise ................................................................ 14
General Description ......................................................................... 1
Applications Information .............................................................. 15
Revision History ............................................................................... 2
Higher Feedback Resistor Gain Operation ............................. 15
Specifications..................................................................................... 3
Recommended Values for Various Gains................................ 15
±15 V Supply ................................................................................. 3
Noise ............................................................................................ 16
±5 V Supply ................................................................................... 4
Circuit Considerations .............................................................. 16
Absolute Maximum Ratings ............................................................ 5
PCB Layout ................................................................................. 16
Thermal Resistance ...................................................................... 5
Power Supply Bypassing ............................................................ 16
Maximum Power Dissipation ..................................................... 5
Grounding ................................................................................... 16
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 17
Pin Configurations and Function Descriptions ........................... 6
Ordering Guide .......................................................................... 17
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 13
REVISION HISTORY
5/12—Rev. C to Rev. D
Changes to Figure 2 Caption ........................................................... 1
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
2/10—Rev. B to Rev. C
Added ADA4898-2 ........................................................ Throughout
Changes to Features.......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 38, Figure 40, Figure 41 ................................. 14
Changes to Figure 46 ...................................................................... 15
Changes to Figure 47 ...................................................................... 16
Changes to PCB Layout Section ................................................... 17
Changes to Ordering Guide .......................................................... 20
6/09—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Specifications Section .................................................. 3
Changes to Figure 29 and Figure 31............................................. 11
Added Figure 32 ............................................................................. 12
Added Figure 41 ............................................................................. 13
Changes to PD (Power-Down) Pin Section ................................ 14
Added Table 6 ................................................................................. 14
Changes to Figure 45...................................................................... 15
8/08—Rev. 0 to Rev. A
Changes to General Description Section .......................................1
Changes to Table 5.............................................................................6
Changes to Figure 17.........................................................................9
Changes to Figure 28...................................................................... 10
Changes to Figure 29 and Figure 32 ............................................ 11
Added 0.1 Hz to 10 Hz Noise Section.......................................... 14
Added Figure 42 and Figure 43; Renumbered Sequentially ..... 14
Changes to Grounding Section..................................................... 16
Updated Outline Dimensions ....................................................... 17
5/08—Revision 0: Initial Release
Rev. D | Page 2 of 20
Data Sheet
ADA4898-1/ADA4898-2
SPECIFICATIONS
±15 V SUPPLY
TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion SFDR
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Offset Current
Input Bias Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
PD (POWER-DOWN) PIN (ADA4898-1)
PD Input Voltages
PD Turn On Time
PD Turn Off Time
Input Leakage Current
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
Max
Unit
VOUT = 100 mV p-p
VOUT = 2 V p-p
G = +2, VOUT = 2 V p-p
VOUT = 5 V step
VOUT = 5 V step
65
14
3.3
55
85
MHz
MHz
MHz
V/µs
ns
f = 100 kHz, VOUT = 2 V p-p
f = 500 kHz, VOUT = 2 V p-p
f = 1 MHz, VOUT = 2 V p-p
f = 1 kHz
f = 1 kHz
−116
−93
−79
0.9
2.4
dBc
dBc
dBc
nV/√Hz
pA/√Hz
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
VOUT = ±5 V
99
20
1
−0.1
0.03
2
103
−103
5
30
3.2
2.5
±11
−126
kΩ
MΩ
pF
pF
V
dB
≤−14
≥−13
100
20
0.1
−0.2
V
V
ns
μs
µA
µA
−11.7 to +12.1
−12.8 to +12.7
40
150
80
V
V
mA
mA
dB
Differential mode
Common mode
Differential mode
Common mode
See Figure 43
VCM = ±2 V
Chip powered down
Chip enabled
VOUT = 100 mV p-p
VOUT = 100 mV p-p
PD = +VS
PD = −VS
RL // (RF + RG) = 500 Ω, see Figure 43
RL // (RF + RG) = 1 kΩ, see Figure 43
f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω
Sinking/sourcing
f = 1 MHz, PD = −VS
−11.0 to +11.8
−12.5 to +12.5
±4.5
PD = +VS
PD = −VS
+VS = 15 V to 17 V, −VS = −15 V
+VS = 15 V, −VS = −15 V to −17 V
Rev. D | Page 3 of 20
−98
−100
7.9
0.1
−107
−114
125
−0.4
0.3
±16.5
8.7
0.3
µV
µV/°C
µA
µA
nA/°C
dB
V
mA
mA
dB
dB
ADA4898-1/ADA4898-2
Data Sheet
±5 V SUPPLY
TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion SFDR
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Offset Current
Input Bias Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
PD (POWER-DOWN) PIN (ADA4898-1)
PD Input Voltages
PD Turn On Time
PD Turn Off Time
Input Leakage Current
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current Per Amplifier
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Conditions
Min
Typ
Max
Unit
VOUT = 100 mV p-p
VOUT = 2 V p-p
G = +2, VOUT = 2 V p-p
VOUT = 2 V step
VOUT = 2 V step
57
12
3
50
90
MHz
MHz
MHz
V/µs
ns
f = 100 kHz, VOUT = 2 V p-p
f = 500 kHz, VOUT = 2 V p-p
f = 1 MHz, VOUT = 2 V p-p
f = 1 kHz
f = 1 kHz
−110
−95
−78
0.9
2.4
dBc
dBc
dBc
nV/√Hz
pA/√Hz
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
RF = 1 kΩ, see Figure 43
VOUT = ±1 V
87
30
1
−0.1
0.05
2
94
−102
5
30
3.2
2.5
−3 to +2.5
−120
kΩ
MΩ
pF
pF
V
dB
≤−4
≥−3
100
20
0.1
−2
V
V
ns
μs
µA
µA
±3.2
±3.4
8
150
80
V
V
mA
mA
dB
Differential mode
Common mode
Differential mode
Common mode
See Figure 43
ΔVCM = 1 V p-p
Chip powered down
Chip enabled
VOUT = 100 mV p-p
VOUT = 100 mV p-p
PD = +VS
PD = −VS
RL // (RF + RG) = 500 Ω, see Figure 43
RL // (RF + RG) = 1 kΩ, see Figure 43
f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω
Sinking/sourcing
f = 1 MHz, PD = −VS
±3.1
±3.3
±4.5
PD = +VS
PD = −VS
+VS = 5 V to 7 V, −VS = −5 V
+VS = 5 V, −VS = −5 V to −7 V
Rev. D | Page 4 of 20
−95
−97
7.5
0.1
−100
−104
160
−0.5
0.3
±16.5
8.4
0.2
µV
µV/°C
µA
µA
nA/°C
dB
V
mA
mA
dB
dB
Data Sheet
ADA4898-1/ADA4898-2
ABSOLUTE MAXIMUM RATINGS
Table 3.
Rating
36 V
See Figure 4
±1.5 V
±11.4 V
−65°C to +150°C
−40°C to +105°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 4 shows the maximum power dissipation vs. the ambient
temperature for the single and dual 8-lead SOIC_N_EP on a
JEDEC standard 4-layer board, with its underside paddle
soldered to a pad that is thermally connected to a PCB plane. θJA
values are approximations.
5.0
4.5
MAXIMUM POWER DISSIPATION (W)
Table 4.
Package Type
Single 8-Lead SOIC_N_EP on a 4-Layer Board
Dual 8-Lead SOIC_N_EP on a 4-Layer Board
θJA
47
42
θJC
29
29
Unit
°C/W
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4898 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4898. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
4.0
3.5
ADA4898-2
3.0
2.5
ADA4898-1
2.0
1.5
1.0
0.5
0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. D | Page 5 of 20
07037-003
Parameter
Supply Voltage
Power Dissipation
Differential Mode Input Voltage
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the output load drive. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive depends
upon the particular application. For each output, the power due
to load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
ADA4898-1/ADA4898-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADA4898-1
NC 1
8
PD
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
NOTES
1. EXPOSED PAD CAN BE CONNECTED
TO THE NEGATIVE SUPPLY (−VS) OR
LEFT FLOATING.
07037-046
TOP VIEW
(Not to Scale)
Figure 5. Single 8-Lead SOIC_N_EP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
NC
−IN
+IN
−VS
NC
VOUT
+VS
PD
EP
Description
No Connect.
Inverting Input.
Noninverting Input.
Negative Supply.
No Connect.
Output.
Positive Supply.
Power Down Not.
Exposed Pad. Can be connected to the negative supply (−VS) or can be left floating.
ADA4898-2
VOUT1 1
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
NOTES
1. EXPOSED PAD CAN BE CONNECTED
TO THE NEGATIVE SUPPLY (−VS) OR
LEFT FLOATING.
07037-051
TOP VIEW
(Not to Scale)
Figure 6. Dual 8-Lead SOIC_N_EP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VOUT1
−IN1
+IN1
−VS
+IN2
−IN2
VOUT2
+VS
EP
Description
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Positive Supply.
Exposed Pad. Can be connected to the negative supply (−VS) or can be left floating.
Rev. D | Page 6 of 20
Data Sheet
ADA4898-1/ADA4898-2
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
0
–1
–2
G = +2
RF = 100Ω
–3
–4
–5
G = +5
RF = 100Ω
–6
–7
–8
–9
–10
RL = 1kΩ
VOUT = 100mV p-p
VS = ±15V
–11
–12
1
10
100
–2
G = +2
RF = 100Ω
–3
–4
–5
–6
–7
G = +5
RF = 100Ω
–8
–9
–10
RL = 1kΩ
VOUT = 2V p-p
VS = ±15V
–12
1
10
100
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Large Signal Frequency Response for Various Gains
3
1
2
–1
RL = 100Ω
–3
–4
RL = 200Ω
–5
–6
–7
–8
–9
–10
1
10
100
FREQUENCY (MHz)
TA = +105°C
1
–5
–6
–7
–8
–9
G = +1
VOUT = 2V p-p
VS = ±15V
–12
1
2
TA = +85°C
CLOSED-LOOP GAIN (dB)
0
–1
TA = +25°C
TA = 0°C
–4
–5
TA = –40°C
–6
TA = +105°C
1
0
–3
100
Figure 11. Large Signal Frequency Response for Various Loads
–1
–2
10
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Loads
2
RL = 200Ω
RL = 100Ω
–4
–11
07037-005
–12
–3
–10
G = +1
VOUT = 100mV p-p
VS = ±15V
–11
–2
07037-008
CLOSED-LOOP GAIN (dB)
0
–1
–2
RL = 1kΩ
0
RL = 1kΩ
1
–7
–8
TA = +85°C
–2
TA = +25°C
–3
–4
–5
TA = 0°C
–6
–7
TA = –40°C
–8
–9
–9
G = +1
RL = 1kΩ
VOUT = 100mV p-p
VS = ±15V
–11
–12
1
G = +1
RL = 1kΩ
VOUT = 2V p-p
VS = ±15V
–10
–11
10
FREQUENCY (MHz)
100
–12
07037-006
–10
Figure 9. Small Signal Frequency Response for Various Temperatures
1
10
FREQUENCY (MHz)
100
07037-009
CLOSED-LOOP GAIN (dB)
G = +1
RF = 100Ω
0
–1
–11
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
G = +1
RF = 0Ω
1
07037-007
G = +1
RF = 0Ω
07037-004
NORMALIZED CLOSED-LOOP GAIN (dB)
3
G = +1
RF = 100Ω
2
NORMALIZED CLOSED-LOOP GAIN (dB)
3
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. D | Page 7 of 20
ADA4898-1/ADA4898-2
Data Sheet
2
2
1
1
0
0
VS = ±15V
–1
CLOSED-LOOP GAIN (dB)
–2
–3
–4
VS = ±5V
–5
–6
–7
–8
VS = ±5V
–5
–6
–7
–8
–10
G = +1
RL = 1kΩ
VOUT = 100mV p-p
G = +1
RL = 1kΩ
VOUT = 2V p-p
–11
–12
1
10
100
FREQUENCY (MHz)
–12
07037-010
–11
1
10
100
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Supply Voltages
07037-013
–10
Figure 16. Large Signal Frequency Response for Various Supply Voltages
1.0
3
0.9
CL = 5pF
2
0.8
1
0.7
CL = 0pF
–2
–3
–4
CL = 33pF
–5
–6
–7
–8
CL = 15pF
G = +1
RL = 1kΩ
VOUT = 100mV p-p
VS = ±15V
–10
–11
–12
0.5
0.4
0.3
0.2
VOUT = 0.1V p-p
0.1
0
–0.1
VOUT = 2V p-p
–0.2
–0.3
G = +2
RL = 1kΩ
VS = ±15V
–0.4
1
10
100
FREQUENCY (MHz)
–0.5
100k
07037-011
–9
0.6
1M
10M
FREQUENCY (Hz)
07037-014
–1
NORMALIZED GAIN (dB)
0
Figure 17. 0.1 dB Flatness for Various Output Voltages
Figure 14. Small Signal Frequency Response for Various Capacitive Loads
100
INPUT CURRENT NOISE (pA/ Hz)
10
1
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
07037-012
VOLTAGE NOISE (nV/√Hz)
VS = ±15V
–3
–4
–9
–9
CLOSED-LOOP GAIN (dB)
–2
10
1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 18. Input Current Noise vs. Frequency
Figure 15. Voltage Noise vs. Frequency
Rev. D | Page 8 of 20
100k
07037-035
CLOSED-LOOP GAIN (dB)
–1
Data Sheet
ADA4898-1/ADA4898-2
–90
–110
60
–120
50
–130
40
–140
GAIN
30
–150
20
–160
10
–170
0
–180
–10
–190
–20
100k
1M
10M
100M
–105
–200
1G
DISTORTION (dBc)
–100
70
OPEN-LOOP PHASE (Degrees)
PHASE
80
–100
–110
HD2
–115
–120
–125
HD3
–130
–135
07037-016
90
FREQUENCY (Hz)
1
0
G = +2, HD3, RF = 250Ω
–20
DISTORTION (dBc)
5
6
G = +1
VS = ±5V
VOUT = 2V p-p
RL = 100Ω, HD3
G = +2, HD2, RF = 250Ω
–60
–80
G = +1, HD3
–100
RL = 100Ω, HD2
–60
–80
RL = 1kΩ, HD3
–100
G = +1, HD2
RL = 1kΩ, HD2
1M
10M
FREQUENCY (Hz)
–140
100k
07037-017
–140
100k
Figure 20. Harmonic Distortion vs. Frequency and Gain
0
G = +1
VS = ±15V
VOUT = 2V p-p
Figure 23. Harmonic Distortion vs. Frequency and Loads
RL = 100Ω, HD3
0.14
VOUT = 100mV p-p
G = +1
0.12 R = 1kΩ
L
VS = ±15V
0.10
OUTPUT VOLTAGE (V)
–40
–60
10M
1M
FREQUENCY (Hz)
07037-020
–120
–120
RL = 100Ω, HD2
–80
–100
RL = 1kΩ, HD3
0.08
CL = 15pF
CL = 0pF
0.06
0.04
0.02
CL = 5pF
0
–120
RL = 1kΩ, HD2
–0.02
1M
10M
FREQUENCY (Hz)
Figure 21. Harmonic Distortion vs. Frequency and Loads
CL = 33pF
07037-018
–140
100k
–0.04
TIME (20ns/DIV)
07037-021
DISTORTION (dBc)
4
–40
–40
DISTORTION (dBc)
3
Figure 22. Harmonic Distortion vs. Output Amplitude
0
–20
2
OUTPUT VOLTAGE (V p-p)
Figure 19. Open-Loop Gain and Phase vs. Frequency
RL = 1kΩ
VS = ±15V
–20 VOUT = 2V p-p
f = 100kHz
G = +1
RL = 1kΩ
VS = ±15V
–80
07073-019
ΔVOUT = ±5V
VS = ±15V
100
OPEN-LOOP GAIN (dB)
–95
–70
110
Figure 24. Small Signal Transient Response for Various Capacitive Loads
Rev. D | Page 9 of 20
ADA4898-1/ADA4898-2
Data Sheet
2.5
0.14
VOUT = 100mV p-p
RL=1kΩ
0.12 V = ±15V
S
G = +1
2.0
VOUT = 2V p-p
G = +1
RL= 1kΩ
0.08
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.10
G = +2
0.06
0.04
0.02
1.5
VS = ±5V
1.0
0.5
0
VS = ±15V
0
–0.5
TIME (100ns/DIV)
Figure 25. Small Signal Transient Response for Various Gains
2.5
VOUT = 2V p-p
G = +1
RL = 100Ω
1.5
2.0
VS = ±5V
1.0
0.5
–0.5
VOUT = 2V p-p
RL = 1kΩ
VS = ±15V
1.5
G = +2
1.0
0.5
G = +1
VS = ±15V
0
0
07037-023
OUTPUT VOLTAGE (V)
2.0
Figure 28. Large Signal Transient Response for
Various Supply Voltages, RL = 1 kΩ
OUTPUT VOLTAGE (V)
2.5
07037-025
TIME (20ns/DIV)
TIME (100ns/DIV)
–0.5
Figure 26. Large Signal Transient Response for
Various Supply Voltages, RL = 100 Ω
07037-024
–0.04
07037-022
–0.02
TIME (100ns/DIV)
Figure 29. Large Signal Transient Response for Various Gains
10k
G = +1
RL = 1kΩ
VOUT = 5V p-p
VS = ±15V
OUTPUT
0.4
∆t = 85ns
0.1
0
–0.1
–0.2
100
10
PD HIGH
1
G = +1
RF = 0Ω
VS = ±15V
–0.3
–0.4
–0.5
TIME (10ns/DIV)
Figure 27. Settling Time
0.1
100k
1M
10M
FREQUENCY (Hz)
Figure 30. Output Impedance vs. Frequency
Rev. D | Page 10 of 20
100M
07037-028
0.2
INPUT
07037-026
SETTLING TIME (%)
0.3
PD LOW
1k
OUTPUT IMPEDANCE (Ω)
0.5
Data Sheet
ADA4898-1/ADA4898-2
∆VCM = 100mV p-p
–60
–80
–100
–140
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
NEGATIVE SWING, 4
VS = –5V
NEGATIVE SWING,
VS = –15V
3
9
POSITIVE SWING, VS = +5V
6
2
3
1
0
50
07037-029
G = +1
RF = 0Ω
RL = 100Ω
VS = ±15V
–120
12
100
1000
OUTPUT VOLTAGE SWING (V), VS = ±5V
CMRR (dB)
–40
POSITIVE SWING,
VS = +15V
0
4000
07037-100
OUTPUT VOLTAGE SWING (V), VS = ±15V
∆VCM = 1V p-p
–20
LOAD RESISTANCE (Ω)
Figure 34 Output Swing vs. Load, G = +2, Load = RL // (RF + RG)
Figure 31. Common-Mode Rejection Ratio (CMRR) vs. Frequency
–45
–40
G = +1
RL = 1kΩ
–50 VOUT = 2V p-p
VOUT = 0.1V p-p
VOUT = 2V p-p
–65
+IN1 TO VOUT2, VS = ±5V
+IN1 TO VOUT2, VS = ±15V
–60
–55
CROSSTALK (dB)
PD ISOLATION (dB)
5
15
0
–70
–80
+IN2 TO VOUT1, VS = ±15V
–90
1M
10M
100M
FREQUENCY (Hz)
07037-031
–75
100k
Figure 32. PD Input to Output Isolation vs. Frequency
–20
–60
–80
G = +1
RF = 0Ω
RL = 100Ω
VS = ±15V
VOUT = 2V p-p
–120
100
–PSRR
1k
10k
100k
1M
10M
FREQUENCY (Hz)
07037-030
PSRR (dB)
–40
–100
–110
1
10
FREQUENCY (MHz)
Figure 35. Crosstalk vs. Frequency
0
+PSRR
+IN2 TO VOUT1, VS = ±5V
–100
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency
Rev. D | Page 11 of 20
100
07037-101
G = +1
RL = 1kΩ
VS = ±15V
ADA4898-1/ADA4898-2
Data Sheet
1000
1000
N = 6180
MEAN: –0.13
SD: 0.02
VS = ±15V
800
N = 6180
MEAN: 27
SD: 20
VS = ±15V
800
COUNT
400
400
0
–0.25
–0.20
–0.15
–0.10
–0.05
INPUT BIAS CURRENT (µA)
0
Figure 36. Input Bias Current Distribution
0
–60
–30
0
30
60
90
INPUT OFFSET VOLTAGE (µV)
Figure 37. Input Offset Voltage Distribution, VS = ±15 V
Rev. D | Page 12 of 20
120
07037-033
200
200
07037-032
COUNT
600
600
Data Sheet
ADA4898-1/ADA4898-2
TEST CIRCUITS
+VS
10µF
+VS
+
10µF
+
RG
RF
0.1µF
0.1µF
VOUT
IN
VOUT
IN
RL
49.9Ω
49.9Ω
0.1µF
RL
0.1µF
10µF
–VS
07037-055
07037-052
+
+
10µF
CL
–VS
Figure 38. Typical Noninverting Load Configuration
Figure 41. Typical Capacitive Load Configuration
+VS
+VS
10µF
+
49.9Ω
AC
0.1µF
VOUT
VOUT
RL
RL
49.9Ω
AC
07037-053
0.1µF
–VS
–VS
Figure 39. Positive Power Supply Rejection
Figure 42. Negative Power Supply Rejection
RIN = 20Ω
+VS
10µF
+VS
+
IN-AMP
VOUT
0.1µF
1kΩ
VOUT
+IB
RL
1kΩ
–VS
VCONTROL
0.1µF
–VS
07037-054
+
10µF
1kΩ
200Ω
Figure 43.DC Test Circuit
Figure 40. Common-Mode Rejection
Rev. D | Page 13 of 20
07037-139
1kΩ
53.6Ω
RF = 1kΩ
–IB
1kΩ
IN
07037-056
+
10µF
ADA4898-1/ADA4898-2
Data Sheet
THEORY OF OPERATION
The ADA4898 is a voltage feedback op amp that combines unity
gain stability with 0.9 nV/√Hz input noise. It employs a highly
linear input stage that can maintain greater than −90 dBc (at
2 V p-p) distortion out to 600 kHz while in a unity-gain
configuration. This rare combination of unity gain stability, low
input-referred noise, and extremely low distortion is the result
of Analog Devices, Inc., proprietary op amp architecture and
high voltage bipolar processing technology.
Table 7. Power-Down Voltage Control
PD Pin
RL
CC
0.5
0.4
0.3
OUTPUT VOLTAGE (µV)
R1
±5 V
≤−4 V
Figure 45 shows the 0.1 Hz to 10 Hz voltage and current noise
of the ADA4898. The peak-to-peak noise voltage is below 0.5 μV.
Figure 46 shows the circuit used to measure the low frequency
noise. It uses a band-pass filter of approximately 0.1 Hz and 10 Hz
and a high gain stage feeding into an instrumentation amplifier.
07037-041
BUFFER
gm
±10 V
≤−9 V
0.1 Hz TO 10 Hz NOISE
The simplified ADA4898 topology, shown in Figure 44, is a
single gain stage with a unity gain output buffer. It has over 100 dB
of open-loop gain and maintains precision specifications, such
as CMRR, PSRR, and offset, to levels that are normally associated
with topologies having two or more gain stages.
VOUT
±15 V
≤−14 V
Power-Down Mode
Figure 44. Topology
PD (POWER-DOWN) PIN FOR THE ADA4898-1
0.2
0.1
0
–0.1
–0.2
–0.3
The PD pin saves power by decreasing the quiescent power
dissipated in the device. It is very useful when power is an issue
and the device does not need to be turned on at all times. The
response of the device is rapid when going from power-down
mode to full power operation mode. Note that PD does not put
the output in a high-Z state, which means that the ADA4898
is not recommended for use as a multiplexer. Leaving the PD
pin floating keeps the amplifier in full power operation mode.
–0.5
0
2
4
6
8
10
12
TIME (s)
14
16
18
20
07037-047
–0.4
Figure 45. 0.1 Hz to 10 Hz Noise
FARADAY CAGE
+IN
DUT
ADA4898-1
50Ω
+VS = +9V
1kΩ
1µF
1
10nF
2
+IN
–IN
–VR = –5V
AD743
806kΩ
806kΩ
7805
1µF
–IN
+VS = +9V
(BATTERY)
OUT
15.8kΩ
3
10nF
4
RG
RG
AD620
–IN
+VS
+IN
OUTPUT
–VS
8
7
6
REF 5
+VS = +9V
10nF
TEK
TDS 754A SCOPE
COAX
IN
FLOATING SHIELD
13kΩ
+VR = +5V
13Ω
10nF
–VS = –9V
–VS = –9V
7905
–VR = –5V
07037-048
50Ω
R = 5.36kΩ, GAIN APPROX. 10Ω
MOMENTARY
+VR = +5V
–VS = –9V
(BATTERY)
Figure 46. Low Frequency Noise Circuit
Rev. D | Page 14 of 20
Data Sheet
ADA4898-1/ADA4898-2
APPLICATIONS INFORMATION
12
HIGHER FEEDBACK RESISTOR GAIN OPERATION
CF
RF
+VS
10µF
RF = 1kΩ
6
RF = 100Ω
3
RF = 1kΩ, CF = 2.7pF
0
–3
–6
–9
–15
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 48. Small Signal Frequency Response for
Various Feedback Impedances
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 8 provides a useful reference for determining various gains
and associated performance. RF is set to 100 Ω for gains greater
than 1. A low feedback RF resistor value reduces peaking and
minimizes the contribution to the overall noise performance
of the amplifier.
0.1µF
VOUT
RL
VIN
0.1µF
10µF
–VS
07037-043
+
RT
Figure 47. Noninverting Gain Schematic
Table 8. Gains and Recommended Resistor Values Associated with Them (Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω)
Gain
+1
+2
+5
RF (Ω)
0
100
100
RG (Ω)
N/A
100
24.9
−3 dB SS BW (MHz),
VOUT = 100 mV p-p
65
30
9
07037-044
–12
+
RF
CLOSED-LOOP GAIN (dB)
The ADA4898 schematic for the noninverting gain
configuration shown in Figure 47 is nearly a textbook example.
The only exception is the feedback capacitor in parallel with
the feedback resistor, RF, but this capacitor is recommended
only when using a large RF value (>300 Ω). Figure 48 shows the
difference between using a 100 Ω resistor and a 1 kΩ feedback
resistor. Due to the high input capacitance in the ADA4898 when
using a higher feedback resistor, more peaking appears in the
closed-loop gain. Using the lower feedback resistor resolves this
issue; however, when running at higher supplies (±15 V) with
an RF of 100 Ω, the system draws a lot of extra current into the
feedback network. To avoid this problem, a higher feedback
resistor can be used with a feedback capacitor in parallel. Figure 48
shows the effect of placing a feedback capacitor in parallel with
a larger RF. In this gain-of-2 configuration, RF = RG = 1 kΩ and
CF = 2.7 pF. When using CF, the peaking drops from 6 dB to less
than 2 dB.
G = +2
RL = 1kΩ
9 VS = ±15V
Slew Rate (V/µs),
VOUT = 2 V Step
55
50
45
Rev. D | Page 15 of 20
ADA4898 Voltage
Noise (nV/√Hz), RTO
0.9
1.8
4.5
Total System Noise
(nV/√Hz), RTO
1.29
3.16
7.07
ADA4898-1/ADA4898-2
Data Sheet
NOISE
To analyze the noise performance of an amplifier circuit, identify
the noise sources, and then determine if each source has a
significant contribution to the overall noise performance of the
amplifier. To simplify the noise calculations, noise spectral densities
were used rather than actual voltages to leave bandwidth out of the
expressions. Noise spectral density, which is generally expressed
in nV/√Hz, is equivalent to the noise in a 1 Hz bandwidth.
The noise model shown in Figure 49 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the amplifier.
Each noise source has its own contribution to the noise at the
output. Noise is generally specified as referring to input (RTI),
but it is often simpler to calculate the noise referred to the
output (RTO) and then divide by the noise gain to obtain the RTI
noise.
VN, R2
R2
VN, R1
R1
NOISE GAIN =
NG = 1 + R2
R1
IN–
VN
A
4kTR1
VN, R3
VOUT
R3
IN+
GAIN FROM
= – R2
B TO OUTPUT
R1
4kTR3
VN2 + 4kTR3 + 4kTR1
RTI NOISE =
R2
R1 + R2
+ IN+2R32 + IN–2 R1 × R2
R1 + R2
2
2
+ 4kTR2
R1
R1 + R2
RTO NOISE = NG × RTI NOISE
2
07037-045
B
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4898 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
PCB LAYOUT
Because the ADA4898 has a small signal bandwidth of 65 MHz, it
is essential that high frequency board layout techniques be
employed. All ground and power planes under the pins of the
ADA4898 should be cleared of copper to prevent the formation of
parasitic capacitance between the input pins to ground and the
output pins to ground. A single mounting pad on a SOIC
footprint can add as much as 0.2 pF of capacitance to ground if
the ground plane is not cleared from under the mounting pads.
POWER SUPPLY BYPASSING
GAIN FROM
=
A TO OUTPUT
4kTR2
performance for the amplifier and associated resistors is shown
in Table 8.
Figure 49. Op Amp Noise Analysis Model
Power supply bypassing for the ADA4898 has been optimized
for frequency response and distortion performance. Figure 47
shows the recommended values and location of the bypass
capacitors. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The 0.1 µF
capacitors shown in Figure 47 should be as close to the supply
pins of the ADA4898 as possible. The 10 µF electrolytic
capacitors should be adjacent to, but not necessarily close to,
the 0.1 µF capacitors. The capacitor between the two supplies
helps improve PSR and distortion performance. In some cases,
additional paralleled capacitors can help improve frequency
and transient response.
GROUNDING
All resistors have a Johnson noise that is calculated by
(4kBTR)
where:
k is Boltzmann’s constant (1.38 × 10−23 J/K).
B is the bandwidth in Hertz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.
A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV/√Hz at 25°C.
In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
Ground and power planes should be used where possible. Ground
and power planes reduce the resistance and inductance of the
power planes and ground returns. The returns for the input
and output terminations, bypass capacitors, and RG should all
be kept as close to the ADA4898 as possible. The output load
ground and the bypass capacitor grounds should be returned to
the same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.
The ADA4898 package features an exposed paddle. For optimum
electrical and thermal performance, solder this paddle to a negative supply plane.
Rev. D | Page 16 of 20
Data Sheet
ADA4898-1/ADA4898-2
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
2.29 (0.090)
5
2.29 (0.090)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
4
BOTTOM VIEW
1.27 (0.05)
BSC
(PINS UP)
1.75 (0.069)
1.35 (0.053)
1.65 (0.065)
1.25 (0.049)
0.10 (0.004)
MAX
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.020)
0.31 (0.012)
0.50 (0.020)
0.25 (0.010)
0.25 (0.0098)
0.17 (0.0067)
45°
1.27 (0.050)
0.40 (0.016)
8°
0°
07-28-2008-A
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters and (inches)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
8
5
TOP VIEW
1
4
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
3.098 (0.122)
2.41 (0.095)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
BOTTOM VIEW
1.27 (0.05)
BSC
(PINS UP)
1.65 (0.065)
1.25 (0.049)
0.10 (0.004)
MAX
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.020)
0.31 (0.012)
0.50 (0.020)
0.25 (0.010)
0.25 (0.0098)
0.17 (0.0067)
8°
0°
45°
1.27 (0.050)
0.40 (0.016)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
07-28-2008-A
1.75 (0.069)
1.35 (0.053)
Figure 51. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-2)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADA4898-1YRDZ
ADA4898-1YRDZ-R7
ADA4898-1YRDZ-RL
ADA4898-2YRDZ
ADA4898-2YRDZ-R7
ADA4898-2YRDZ-RL
ADA4898-1YRD-EBZ
ADA4898-2YRD-EBZ
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 17 of 20
Package Option
RD-8-1
RD-8-1
RD-8-1
RD-8-2
RD-8-2
RD-8-2
Ordering Quantity
98
1,000
2,500
98
1,000
2,500
ADA4898-1/ADA4898-2
Data Sheet
NOTES
Rev. D | Page 18 of 20
Data Sheet
ADA4898-1/ADA4898-2
NOTES
Rev. D | Page 19 of 20
ADA4898-1/ADA4898-2
Data Sheet
NOTES
©2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07037-0-5/12(D)
Rev. D | Page 20 of 20