TI CD40109BQNSRQ1

CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
CMOS QUAD LOW-TO-HIGH VOLTAGE SHIFTER
Check for Samples: CD40109B-Q1
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Independent of Power Supply Sequence
Considerations
– VCC Can Exceed VDD
– Input Signals can Exceed Both VCC and VDD
Up and Down Level-Shifting Capability
Three-State Outputs With Separate Enable
Controls
Standardized Symmetrical Output
Characteristics
100% Tested for Quiescent Current at 20 V
Maximum Input Current:
– 1 µA at 18 V Over Full
Package-Temperature Range
– 100 nA at 18 V and 25°C
Noise Margin (Full Package-Temperature
Range):
– 1 V at VCC = 5 V, VDD = 10 V
– 2 V at VCC = 10 V, VDD = 15 V
5-V, 10-V, and 15-V Parametric Ratings
Meets All Requirements of JEDEC Tentative
Standard No. 13B, "Standard specifications for
•
Description of 'B' Series CMOS Devices"
Latch-Up Performance Meets 50 mA per JESD
78, Class I
APPLICATIONS
•
•
High-or-Low Level-Shifting With Three-State
Outputs for Unidirectional or Bidirectional
Bussing
Isolation of Logic Subsystem Using Separate
Power Supplies from Supply Sequencing,
Supply Loss, and Supply Regulation
Considerations
NS PACKAGE
(TOP VIEW)
DESCRIPTION
CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic
input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a high-voltage output signal (E, F, G, H) with
logical 1 = VDD and logical 0 = VSS.
The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the
high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There
are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one
exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the
device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may
exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109
will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability. A low level on any of the separately enabled
three-state output controls produces a high-impedance state in the corresponding output.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – NS
Reel of 2000
ORDERABLE PART NUMBER
CD40109BQNSRQ1
TOP-SIDE MARKING
CD40109BQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TRUTH TABLE (1)
INPUTS
(1)
OUTPUTS
A, B, C, D
ENABLE
A, B, C, D
E, F, G, H
0
1
0
1
1
1
X
0
Z
0 = VSS, 1 = VCC at inputs and VDD at outputs, X = Don't care, Z =
High impedance
Functional Diagram (1 of 4 Units)
Logic Diagram (1 of 4 Units)
2
Copyright © 2010–2011, Texas Instruments Incorporated
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VDD
PD
DC supply voltage range
Voltages referenced to VSS terminal
Output voltage range
All outputs
DC input current
Power dissipation per package
VALUE
UNIT
–0.5 to +20
V
–0.5 to VDD + 0.5
V
Any one input
±10
mA
TA = –40°C to + 100°C
500
mW
TA = 100°C to + 125°C
Derate linearly at
12 mW/°C to 200 mW
Device dissipation per output transistor
(for TA = full package-temperature range, all package types)
100
mW
°C
TA
Operating-temperature range
–40 to +125
Tstg
Storage temperature range
–65 to +150
°C
50
mA
Latch-Up Performance per JESD 78, Class I
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VDD
Supply-voltage range (for TA = full package-temperature range)
MIN
MAX
3
18
UNIT
V
STATIC ELECTRICAL CHARACTERISTICS
CONDITIONS
PARAMETER
IDD Max
IOL Min
IOH Min
VOL Max
VOH Min
IIN Max
VO
(V)
Quiescent device current
Output low (sink) current
VIH Min
–40
+85
+125
0, 5
5
1
30
0, 10
10
2
0, 15
15
4
+25
MIN
TYP
MAX
30
0.02
1
60
60
0.02
2
120
120
0.02
4
0.04
20
0, 20
20
20
600
600
0, 5
5
0.61
0.42
0.36
0.51
1
0.5
0, 10
10
1.5
1.1
0.9
1.3
2.6
1.5
0, 15
15
4
2.8
2.4
3.4
6.8
4.6
0, 5
5
–0.61
–0.42
–0.36
–0.51
–1
0, 5
5
–1.8
–1.3
–1.15
–1.6
–3.2
9.5
0, 10
10
–1.5
–1.1
–0.9
–1.3
–2.6
13.5
0, 15
15
–4
–2.8
–2.4
–3.4
–6.8
Output voltage: low-level
Output voltage: high-level
Input current
Input high voltage
VDD
(V)
2.5
Output high (source) current
Input low voltage
VIN
(V)
0.4
IOUT Max
VIL Max
LIMITS AT INDICATED TEMPERATURES (°C)
0, 5
5
0.05
0
0.05
10
0.05
0
0.05
0, 15
15
0.05
0
0.05
0, 5
5
4.95
0, 10
10
0, 15
15
0, 18
18
±0.1
±0.4
5
9.95
9.95
10
14.95
14.95
±1
±12
0, 18
18
1, 9
5
10
1.5
1.5,
13.5
10
15
3
1, 9
5
10
3.5
1.5,
13.5
10
15
7
Copyright © 2010–2011, Texas Instruments Incorporated
±1
±12
µA
mA
0, 10
4.95
UNIT
V
15
±10–5
±0.1
µA
–4
±0.4
µA
±10
1.5
3
3.5
V
7
3
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
DYNAMIC ELECTRICAL CHARACTERISTICS
TA = 25°C, Input tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SHIFTING MODE
L–H
tPHL
Propagation delay time,
high-to-low level, data
input to output
H–L
L–H
tPLH
Propagation delay time,
low-to-high level, data
input to output
H–L
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time,
3-state disable, delay,
output high to high
impedance
Propagation delay time,
3-state disable, delay,
output low to high
impedance
Propagation delay time,
3-state disable, delay,
output high impedance
to high
Propagation delay time,
3-state disable, delay,
output high impedance
to low
L–H
RL = 1 kΩ
H–L
L–H
RL = 1 kΩ
H–L
L–H
RL = 1 kΩ
H–L
L–H
RL = 1 kΩ
H–L
L–H
tTHL, tTLH
Transition time
H–L
Ci
4
Input capacitance
VCC
(V)
VDD
(V)
MIN
MAX
5
10
300
600
5
15
220
440
10
15
180
360
10
5
250
500
15
5
250
500
15
10
120
240
5
10
130
260
5
15
120
240
10
15
70
140
10
5
230
460
15
5
230
460
15
10
80
160
5
10
60
120
150
5
15
75
10
15
35
70
10
5
200
400
15
5
200
400
15
10
40
80
5
10
370
740
5
15
300
600
10
15
250
500
10
5
250
500
15
5
250
500
15
10
130
260
5
10
320
640
5
15
230
460
10
15
180
360
10
5
300
600
15
5
300
600
15
10
130
260
5
10
100
200
5
15
80
160
10
15
40
80
10
5
200
400
15
5
200
400
15
10
40
80
5
10
50
100
5
15
40
80
10
15
40
80
10
5
100
200
15
5
100
200
15
10
50
100
5
7.5
Any input
UNIT
ns
ns
ns
ns
ns
ns
ns
pF
Copyright © 2010–2011, Texas Instruments Incorporated
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS
Figure 1. Typical Output Low (Sink) Current
Characteristics
Figure 2. Minimum Output Low (Sink) Current
Characteristics
Figure 3. Typical Output High (Source) Current
Characteristics
Figure 4. Minimum Output High (Source) Current
Characteristics
Figure 5. Typical Transition Time as a Function of Load
Capacitance
Figure 6. Typical High-to-Low Propagation Delay Time as
a Function of Load Capacitance
Copyright © 2010–2011, Texas Instruments Incorporated
5
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
6
Figure 7. Typical Low-to-High Propagation Delay Time as
a Function of Load Capacitance
Figure 8. Typical Input Switching as a Function of
High-Level Supply Voltage
Figure 9. High-Level Supply Voltage vs Low-Level Supply
Voltage
Figure 10. Typical Dynamic Power Dissipation as a
Function of Input Frequency
Copyright © 2010–2011, Texas Instruments Incorporated
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 11. Output Enable Delay Times Test Circuit and Waveforms
Figure 12. Quiescent Device Current Test Circuit
Figure 13. Input Voltage Test Circuit
Figure 14. Input Current Test Circuit
Figure 15. Dynamic Power Dissipation Test Circuit
Copyright © 2010–2011, Texas Instruments Incorporated
7
CD40109B-Q1
SCHS380 A – JUNE 2010 – REVISED AUGUST 2011
Note:
www.ti.com
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid
graduations are in mils (10–3 inch).
Figure 16. Dimensions and Pad Layout
8
Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2012
PACKAGING INFORMATION
Orderable Device
CD40109BQNSRQ1
Status
(1)
ACTIVE
Package Type Package
Drawing
SO
NS
Pins
Package Qty
16
2000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD40109B-Q1 :
• Catalog: CD40109B
• Military: CD40109B-MIL
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2012
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CD40109BQNSRQ1
Package Package Pins
Type Drawing
SO
NS
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
8.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.5
2.5
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD40109BQNSRQ1
SO
NS
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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