PRELIMINARY DATA SHEET N-CHANNEL GaAs MES FET NES1823P-50 50 W L-BAND PUSH-PULL POWER GaAs MES FET DESCRIPTION The NES1823P-50 is a 50 W push-pull type GaAs MES FET designed for high power transmitter applications for PCS, DCS, PHS, and IMT2000 base station systems. It is capable of delivering 50 W of output power (CW) with high linear gain, high efficiency and excellent distortion. Its primary band is 1.8 to 2.3 GHz, however with different matching, 60 MHz or less of instantaneous bandwidth can be achieved anywhere from 0.8 to 2.3 GHz. The device employs 0.9 µm Tungsten Silicide gates, via holes, plated heat sink, and silicon dioxide passivation for superior performance, thermal characteristics, and reliability. Reliability and performance uniformity are assured by NEC’s stringent quality and control procedures. FEATURES • Push-pull type N-channel GaAs MES FET • High output power: Pout = 50 W TYP. • High linear gain: GL = 10.5 dB TYP. • High power added efficiency: ηadd = 40 % TYP. @ VDS = 10.0 V, IDset = 4.0 A (total), f = 2.20 GHz ORDERING INFORMATION (PLAN) Part Number NES1823P-50 Package T-86 Supplying Form ESD protective envelope Remark To order evaluation samples, consult your NEC sales representative. Caution Please handle this device at static-free workstation, because this is an electrostatic sensitive device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P14996EJ1V0DS00 (1st edition) Date Published July 2000 NS CP(K) Printed in Japan © 2000 NES1823P-50 ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, T A = +25 °C) Operation in excess of any one of these parameters may result in permanent damage. Parameter Symbol Ratings Unit Drain to Source Voltage VDS 15 V Gate to Source Voltage VGSO −7 V Gate to Drain Voltage VGDO −18 V Drain Current ID 30 A Gate Current IG 200 mA 110 W Total Power Dissipation Ptot Note Channel Temperature Tch 175 °C Storage Temperature Tstg −65 to +175 °C Note TC = +25 °C RECOMMENDED OPERATING CONDITIONS Parameter MIN. TYP. MAX. Unit VDS − − 10.0 V Gcomp − − 3.0 dB Channel Temperature Tch − − +150 °C Set Drain Current IDset − 4.0 7.0 A − − 20 Ω MIN. TYP. MAX. Unit − 30.0 − A −4.0 −2.6 − V − 1.0 1.5 °C/W 46.0 47.0 − dBm − 12.5 16.0 A − 40 − % 9.5 10.5 − dB − −36 − dBc Drain to Source Voltage Gain Compression Gate Resistance Symbol Test Conditions VDS = 10.0 V, RF OFF Note Rg Note Rg is the series resistance between the gate supply and the FET gate. ELECTRICAL CHARACTERISTICS (TA = +25 °C) Parameter Symbol Test Conditions Saturated Drain Current IDSS VDS = 2.5 V, VGS = 0 V Pinch-off Voltage Vp VDS = 2.5 V, ID = 130 mA Thermal Resistance Rth Channel to Case Output Power Pout f = 2.20 GHz, VDS = 10.0 V, Drain Current ID Pin = 39.5 dBm, Rg = 20 Ω, Power Added Efficiency Linear Gain 3rd Order Intermodulation Distortion ηadd GL IDset = 4.0 A Total (RF OFF) Note 1 Note 2 IM3 ∆f = 5 MHz, Pout = 39 dBm (2 tones total) Notes 1. IDset = 2.0 A each drain 2. Pin = 22 dBm 2 Preliminary Data Sheet P14996EJ1V0DS00 NES1823P-50 TYPICAL CHARACTERISTICS (TA = +25 °C) OUTPUT POWER, POWER ADDED EFFICIENCY vs. INPUT POWER 40 50 35 40 η add 30 30 25 20 25 VDS = 10.0 V f = 2.20 GHz (1 tone) 20 IDset = 4.0 A (RF OFF) Rg = 20 Ω 10 30 35 40 45 VDS = 10.0 V f = 2.20 GHz (1 tone) 12 IDset = 4.0 A (RF OFF) Rg = 20 Ω 10 80 60 ID 40 8 20 6 0 4 –20 IG –40 2 0 15 Gate Current IG (mA) 60 Pout Drain Current ID (A) 45 20 15 14 70 Power Added Efficiency ηadd (%) Output Power Pout (dBm) 50 DRAIN CURRENT, GATE CURRENT vs. INPUT POWER 20 Input Power Pin (dBm) 25 30 35 40 –60 45 Input Power Pin (dBm) Remark The graphs indicate nominal characteristics. Preliminary Data Sheet P14996EJ1V0DS00 3 NES1823P-50 PACKAGE DIMENSIONS G2 45˚ S S D1 19.4±0.4 G1 11.4±0.3 R1.2±0.3 5.7±0.3 2.4±0.3 T-86 (UNIT: mm) D2 1.4±0.2 G1, G2 : Gate D1, D2 : Drain S : Source Preliminary Data Sheet P14996EJ1V0DS00 1.8±0.2 PIN CONNECTIONS 4 4.7 MAX. 24.5±0.3 0.1 2.4±0.2 7.8±0.2 14.5±0.3 20.9±0.3 NES1823P-50 RECOMMENDED MOUNTING CONDITIONS FOR CORRECT USE (1) Fix to heat sink or mount surface completely with screws at the four holes of the flange. (2) The recommended torque strength of the screws is 30 N typical using M2.3 type screws. (3) The recommended flatness of the mount surface is less than ±10 µm (roughness of surface is ∇∇∇). RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Partial Heating Soldering Conditions Recommended Condition Symbol Pin temperature: 260 °C or below, Time: 5 seconds or less (per pin row) − For details of recommended soldering conditions, please contact your local NEC sales office. Preliminary Data Sheet P14996EJ1V0DS00 5 NES1823P-50 [MEMO] 6 Preliminary Data Sheet P14996EJ1V0DS00 NES1823P-50 [MEMO] Preliminary Data Sheet P14996EJ1V0DS00 7 NES1823P-50 CAUTION The great care must be taken in dealing with the devices in this guide. The reason is that the material of the devices is GaAs (Gallium Arsenide), which is designated as harmful substance according to the law concerned. Keep the law concerned and so on, especially in case of removal. • The information in this document is current as of July, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. 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