NEC NE552R679A-T1

DATA SHEET
SILICON POWER MOS FET
NE552R679A
3.0 V OPERATION SILICON RF POWER LD-MOS FET
FOR 460 MHz 0.6 W TRANSMISSION AMPLIFIERS
DESCRIPTION
The NE552R679A is an N-channel silicon power laterally diffused MOS FET specially designed as the
transmission power amplifier for 3.0 V FRS (Family Radio Service). Dies are manufactured using our NEWMOS2
technology (our WSi gate lateral-diffusion MOS FET) and housed in a surface mount package. This device can
deliver 28.0 dBm output power with 60% power added efficiency at 460 MHz under the 3.0 V supply voltage.
FEATURES
• High output power
: Pout = 28.0 dBm TYP. (VDS = 3.0 V, IDset = 300 mA, f = 460 MHz, Pin = 15 dBm)
• High power added efficiency : ηadd = 60% TYP. (VDS = 3.0 V, IDset = 300 mA, f = 460 MHz, Pin = 15 dBm)
• High linear gain
: GL = 20 dB TYP. (VDS = 3.0 V, IDset = 300 mA, f = 460 MHz, Pin = 5 dBm)
• Surface mount package
: 5.7 × 5.7 × 1.1 mm MAX.
• Single supply
: VDS = 2.8 to 6.0 V
APPLICATIONS
• Family Radio Service
: 3.0 V Handsets
ORDERING INFORMATION
Part Number
NE552R679A-T1
Package
Marking
79A
AU
NE552R679A-T1A
Supplying Form
• 12 mm wide embossed taping
• Gate pin face the perforation side of the tape
• Qty 1 kpcs/reel
• 12 mm wide embossed taping
• Gate pin face the perforation side of the tape
• Qty 5 kpcs/reel
Remark To order evaluation samples, contact your nearby sales office.
Part number for sample order: NE552R679A
Caution Please handle this device at static-free workstation, because this is an electrostatic
sensitive device.
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices
representative for availability and additional information.
Document No. PU10125EJ01V1DS (1st edition)
Date Published April 2002 CP(K)
Printed in Japan
 NEC Compound Semiconductor Devices 2001, 2002
NE552R679A
ABSOLUTE MAXIMUM RATINGS (TA = +25°°C)
Parameter
Symbol
Ratings
Unit
Drain to Source Voltage
VDS
8.0
V
Gate to Source Voltage
VGS
5.0
V
Drain Current
IDS
350
mA
600
mA
Drain Current (Pulse Test)
IDS
Note
Total Power Dissipation
Pt
10
W
Channel Temperature
Tch
125
°C
Storage Temperature
Tstg
−55 to +125
°C
Note Duty Cycle 50%, Ton ≤ 1 s
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Drain to Source Voltage
VDS
2.8
3.0
6.0
V
Gate to Source Voltage
VGS
0
2.0
3.0
V
Drain Current
IDS
−
300
500
mA
Input Power
Pin
14
15
20
dBm
MIN.
TYP.
MAX.
Unit
f = 460 MHz, VDS = 3.0 V
ELECTRICAL CHARACTERISTICS
(TA = +25°°C, Unless otherwise specified, using NEC standard test fixture)
Parameter
Symbol
Test Conditions
Gate to Source Leak Current
IGSO
VGS = 5.0 V
−
−
100
nA
Saturated Drain Current
(Zero Gate Voltage Drain Current)
IDSS
VDS = 8.0 V
−
−
100
nA
Gate Threshold Voltage
Vth
VDS = 3.5 V, IDS = 1 mA
1.0
1.4
1.9
V
Thermal Resistance
Rth
Channel to Case
−
−
10
°C/W
Transconductance
gm
VDS = 3.0 V, IDS = 300 mA
−
0.6
−
S
IDSS = 10 µA
15
18
−
V
26.0
28.0
−
dBm
Pin = 15 dBm,
−
320
−
mA
IDset = 300 mA (RF OFF) , Note1
55
60
−
%
−
20
−
dB
Drain to Source Breakdown Voltage
BVDSS
Output Power
Pout
Drain Current
ID
Power Added Efficiency
Linear Gain
Note2
ηadd
f = 460 MHz, VDS = 3.0 V,
GL
Note 1. DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
2. Pin = 5 dBm
2
Data Sheet PU10125EJ01V1DS
NE552R679A
100
750
75
η add
15
500
50
IDS
10
250
0
5
10
15
0
20
25
0
−30
IM3
−40
IM5
−50
−60
−70
5
10
15
20
25
30
Input Power Pin (dBm)
2Tone to Output Power Pout (dBm)
OUTPUT POWER, DRAIN CURRENT
η d, η add vs. INPUT POWER
OUTPUT POWER, DRAIN CURRENT
η d, η add vs. INPUT POWER
Pout
1 000
20
ηd
100
750
75
500
50
η add
15
IDS
10
5
−5
250
0
5
10
15
0
20
30
25
0
Output Power Pout (dBm)
25
1 250
f = 460 MHz
VDS = 3.0 V
IDQ = 100 mA
Drain Efficiency η d (%)
Power Added Efficiency η add (%)
30
25
1 250
f = 460 MHz
VDS = 3.5 V
IDQ = 100 mA
1 000
100
750
75
500
50
250
25
Pout
20
ηd
η add
15
IDS
10
5
−5
0
5
10
15
0
20
0
Drain Efficiency η d (%)
Power Added Efficiency η add (%)
ηd
20
1 000
f = 460 MHz
∆f = 1 MHz
VDS = 3.0 V
IDQ = 300 mA
−20
Drain Current
IDS (mA)
25
Pout
IMD vs. 2TONE TO OUTPUT POWER
−10
Drain Efficiency η d (%)
Power Added Efficiency η add (%)
f = 460 MHz
VDS = 3.0 V
IDQ = 300 mA
5
−5
Output Power Pout (dBm)
1 250
Drain Current
IDS (mA)
Output Power Pout (dBm)
30
IMD (dBc)
OUTPUT POWER, DRAIN CURRENT
η d, η add vs. INPUT POWER
Drain Current
IDS (mA)
TYPICAL CHARACTERISTICS (TA = +25°°C)
Input Power Pin (dBm)
Input Power Pin (dBm)
Remark The graphs indicate nominal characteristics.
Data Sheet PU10125EJ01V1DS
3
NE552R679A
S-PARAMETERS
Test Conditions: VDS = 3.0 V, IDset = 300 mA, TA = +25 °C)
S11
MAG Note MSG Note
dB
dB
Frequency
GHz
Mag.
Ang.
dB
S21
Mag.
Ang.
dB
S12
Mag.
Ang.
Mag.
Ang.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
0.655
0.651
0.666
0.660
0.656
0.655
0.654
0.658
0.656
0.658
0.663
0.668
0.668
0.668
0.672
0.674
0.673
0.675
0.677
0.677
0.677
0.677
0.681
0.677
0.675
0.674
0.673
0.670
0.667
0.665
0.662
0.648
0.656
0.652
0.651
0.648
0.644
0.641
0.636
0.633
−120.2
−142.0
−156.1
−161.4
−165.8
−168.4
−170.2
−171.8
−172.8
−173.8
−175.0
−175.8
−176.8
−177.6
−178.5
−179.2
−180.0
179.2
178.5
177.8
177.0
176.2
175.4
174.7
174.6
173.8
173.2
172.3
171.4
170.7
169.9
168.9
168.6
167.6
167.1
166.2
165.4
164.7
163.8
163.0
21.2
17.2
13.8
11.5
9.4
7.8
6.5
5.2
4.1
3.1
2.1
1.1
0.4
−0.4
−1.1
−1.8
−2.5
−3.2
−3.8
−4.4
−4.9
−5.4
−6.0
−6.5
−6.9
−7.4
−7.9
−8.3
−8.7
−9.1
−9.5
−9.8
−10.4
−10.6
−11.0
−11.3
−11.6
−12.0
−12.3
−12.6
11.42
7.25
4.89
3.74
2.96
2.46
2.10
1.81
1.61
1.43
1.27
1.14
1.04
0.96
0.88
0.81
0.75
0.69
0.65
0.61
0.57
0.54
0.50
0.48
0.45
0.43
0.40
0.39
0.37
0.35
0.33
0.32
0.30
0.29
0.28
0.27
0.26
0.25
0.24
0.23
115.3
99.3
88.2
81.6
77.2
72.6
68.4
64.4
60.6
56.6
53.3
49.9
46.6
43.7
40.6
37.5
34.6
31.7
28.9
26.4
24.0
21.2
19.2
16.6
13.9
11.7
9.5
7.8
5.7
3.5
1.4
−0.1
−1.4
−2.8
−4.5
−6.6
−7.9
−10.1
−11.5
−12.5
−31.6
−29.0
−29.3
−29.2
−29.2
−29.3
−29.5
−29.6
−29.7
−29.8
−30.0
−30.2
−30.3
−30.6
−30.7
−31.0
−31.1
−31.3
−31.6
−31.7
−31.9
−32.2
−32.2
−32.5
−32.7
−32.8
−33.0
−33.2
−33.4
−33.4
−33.7
−34.1
−34.6
−35.3
−35.6
−35.6
−35.7
−36.0
−36.1
−36.2
0.026
0.035
0.034
0.034
0.035
0.034
0.033
0.033
0.033
0.032
0.031
0.031
0.030
0.030
0.029
0.028
0.028
0.027
0.026
0.026
0.025
0.025
0.025
0.024
0.023
0.023
0.022
0.022
0.021
0.021
0.021
0.020
0.019
0.017
0.017
0.017
0.016
0.016
0.016
0.015
28.7
10.3
−0.1
−5.6
−11.8
−15.9
−20.1
−24.2
−27.6
−31.5
−35.3
−39.1
−42.1
−45.4
−49.0
−51.8
−55.3
−58.6
−61.5
−64.6
−68.3
−71.4
−75.1
−78.2
−82.0
−85.1
−89.7
−92.3
−96.7
−101.5
−106.4
−111.8
−117.6
−122.0
−123.8
−126.7
−130.5
−135.9
−140.3
−144.7
0.633
0.757
0.796
0.808
0.815
0.819
0.823
0.828
0.831
0.835
0.840
0.843
0.846
0.851
0.853
0.857
0.859
0.862
0.864
0.867
0.869
0.869
0.863
0.873
0.874
0.874
0.873
0.875
0.874
0.873
0.873
0.879
0.872
0.871
0.871
0.870
0.869
0.868
0.867
0.865
−167.5
−167.9
−173.0
−175.0
−175.9
−176.8
−177.4
−178.0
−179.4
−179.9
179.6
179.2
178.7
178.2
177.7
177.4
176.6
176.1
175.5
174.9
174.2
173.6
172.6
172.4
171.7
170.9
170.1
169.4
168.7
167.9
167.2
166.8
165.7
164.9
164.1
163.1
162.3
161.4
160.4
159.4
Note When K ≥ 1, the MAG (Maximum Available Gain) is used.
When K < 1, the MSG (Maximum Stable Gain) is used.
S22
S21
MAG = S12
MSG =
S21
S12
26.4
23.1
21.5
20.4
19.3
18.6
18.0
16.2
14.2
12.8
11.7
10.7
9.8
9.1
8.2
7.6
6.8
6.1
5.5
5.0
4.4
3.8
3.0
2.8
2.2
1.7
1.2
0.8
0.3
−0.2
−0.8
−1.0
−1.7
−2.1
−2.4
−2.8
−3.2
−3.7
−4.0
−4.4
K
−
0.59
0.36
0.40
0.50
0.62
0.76
0.91
1.04
1.20
1.37
1.54
1.75
1.93
2.14
2.38
2.61
2.87
3.20
3.51
3.76
4.12
4.57
5.14
5.35
5.82
6.29
6.90
7.45
8.10
8.64
9.63
10.28
12.13
13.80
14.87
15.51
16.66
18.41
19.61
21.02
(K – √ (K – 1) )
2
1+∆ −S11
2
−S22
2
,K=
2
,
∆ = S11 ⋅ S22 − S21 ⋅ S12
LARGE SIGNAL IMPEDANCE (VDS = 3.0 V, IDS = 300 mA, f = 460 MHz)
f (MHz)
Zin (Ω)
ZOL (Ω) Note
460
7.47 +j18.24
4.82 +j5.04
Note ZOL is the conjugate of optimum load impedance at given voltage, idling current, input power and frequency.
4
Data Sheet PU10125EJ01V1DS
NE552R679A
EVALUATION BOARD for 460 MHz
Unit : mm
VDS
VGS
C9
C8 C7
C7 C8 C9
C4
L1
R1
30.0
C6
C6
C3
C5
C2
C1
48.0
Symbol
Value
C1
9.1 pF
C2
12 pF
C3
20 pF
C4
3.3 pF
C5
13 pF
C6
22 pF
C7
1 000 pF
C8
0.33 µF
C9
3.3 µF - 16V
R1
1 000 Ω
L1
22 nH
Circuit Board
t = 0.4 mm, ε r = 4.5
Data Sheet PU10125EJ01V1DS
Comment
R4775
5
NE552R679A
PACKAGE DIMENSIONS
79A (UNIT: mm)
1.0 MAX.
0.8±0.15
A
Drain
Gate
Drain
0.4±0.15
0.8 MAX.
5.7 MAX.
0.9±0.2
0.2±0.1
3.6±0.2
79A PACKAGE RECOMMENDED P.C.B. LAYOUT (UNIT: mm)
4.0
1.7
Source
Stop up the hole with a rosin or
something to avoid solder flow.
Drain
1.2
0.5
1.0
5.9
Gate
Through Hole: φ 0.2 × 33
0.5 0.5
6.1
6
Data Sheet PU10125EJ01V1DS
1.2 MAX.
Source
4.4 MAX.
Source
0X001
1.5±0.2
U
Gate
0.6±0.15
5.7 MAX.
(Bottom View)
4.2 MAX.
NE552R679A
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For soldering
methods and conditions other than those recommended below, contact your nearby sales office.
Soldering Method
Soldering Conditions
Condition Symbol
Infrared Reflow
Peak temperature (package surface temperature)
Time at peak temperature
Time at temperature of 220°C or higher
Preheating time at 120 to 180°C
Maximum number of reflow processes
Maximum chlorine content of rosin flux (% mass)
: 260°C or below
: 10 seconds or less
: 60 seconds or less
: 120±30 seconds
: 3 times
: 0.2%(Wt.) or below
IR260
VPS
Peak temperature (package surface temperature)
Time at temperature of 200°C or higher
Preheating time at 120 to 150°C
Maximum number of reflow processes
Maximum chlorine content of rosin flux (% mass)
: 215°C or below
: 25 to 40 seconds
: 30 to 60 seconds
: 3 times
: 0.2%(Wt.) or below
VP215
Wave Soldering
Peak temperature (molten solder temperature)
Time at peak temperature
Preheating temperature (package surface temperature)
Maximum number of flow processes
Maximum chlorine content of rosin flux (% mass)
: 260°C or below
: 10 seconds or less
: 120°C or below
: 1 time
: 0.2%(Wt.) or below
WS260
Partial Heating
Peak temperature (pin temperature)
Soldering time (per pin of device)
Maximum chlorine content of rosin flux (% mass)
: 350°C or below
: 3 seconds or less
: 0.2%(Wt.) or below
HS350-P3
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet PU10125EJ01V1DS
7
NE552R679A
• The information in this document is current as of March, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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third parties by or arising from the use of NEC semiconductor products listed in this document or any other
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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redundancy, fire-containment, and anti-failure features.
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation, NEC Compound Semiconductor Devices, Ltd.
and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4 - 0110
8
Data Sheet PU10125EJ01V1DS
NE552R679A
Business issue
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0110