SONY CXG1051AFN

CXG1051AFN
Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS
Description
The CXG1051AFN is an MMIC consisting of the
power amplifier, antenna switch and low noise down
conversion mixer.
This IC is designed using the Sony's GaAs J-FET
process featuring a single positive power supply
operation.
Features
• Operates at a single positive power supply: VDD = 3V
• Small mold package: 26-pin HSOF
26 pin HSOF (Plastic)
Absolute Maximum Ratings
<Power amplifier/antenna switch transmitter block >
• Low current consumption: IDD = 150mA
(POUT = 20.2dBm, f = 1.9GHz)
• High power gain: Gp = 39dB Typ.
(POUT = 20.2dBm, f = 1.9GHz)
<Antenna switch receiver block/
low noise down conversion mixer>
• Low current consumption: IDD = 5.5mA Typ.
(When no signal)
• High conversion gain: Gc = 20.5dB Typ.
(f = 1.9GHz)
• Low distortion: Input IP3 = –13dBm Typ. (f = 1.9GHz)
• High image suppression ratio: IMR = 40dBc Typ.
(f = 1.9GHz)
• High 1/2 IF suppression ratio: 1/2IFR = 44dBc Typ.
(f = 1.9GHz)
Applications
Japan digital cordless telephones (PHS)
<Power amplifier block>
• Supply voltage
VDD
• Voltage between gate and source
VGSO
• Drain current
IDD
• Allowable power dissipation
PD
6
1.5
550
V
mA
3
W
V
<Switch block>
Control voltage
VCTL
6
<Front-end block>
• Supply voltage
• Input power
VDD
PRF
6
+10
<Common to each block>
• Channel temperature
Tch
• Operating temperature
Topr
• Storage temperature
Tstg
V
V
dBm
150
–35 to +85
–65 to +150
°C
°C
°C
Recommended Operating Conditions
<Common to each block>
• Supply voltage
VDD
Structure
GaAs J-FET MMIC
<Power amplifier block>
• Gain control voltage
VPCTL
<Switch block>
• Control voltage (H)
• Control voltage (L)
2.7 to 3.3
V
to VDD – 1.0 V
VCTL (H) 2.9 to 3.3
VCTL (L) 0 to 0.2
V
V
Note on Handling
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00225B25-PS
CXG1051AFN
Block Diagram and External Circuit
2.2nH
PIN
14
13
15
12
(VGG1)
1kΩ
VPCTL
100pF
VDD1
1nF
18nH
1nF
18nH
10nF
1.8nH
16
11
17
10
VGG2
1nF
2.2nH
VDD2
VDD3
(POUT)
1pF
30pF
18
9
(TX)
30pF
19
VCTL1
8
100pF
ANT
7
20
(RX)
30pF
30pF
VCTL2
21
6
22
5
23
4
100pF
(RFIN)
10nH
6.8nH
10pF
13pF
3.9nH
13pF
1nF
18pF
1nF
VDD
(RF AMP)
3.3kΩ
24
3
25
2
100nF
VDD
(IF AMP, MIX)
26
1
82nH
1nF
5pF
IFOUT
Pin Configuration
PIN 14
13 VGG1
GND 15
12 VPCTL
VDD1 16
11 VGG2
VDD2 17
10 POUT
VDD3 18
9
Tx
GND 19
8
VCTL1
RX 20
7
ANT
VCTL2 21
6
GND
RFIN 22
5
GND
CAP 23
4
VDD (RF AMP)
GND 24
3
GND
CAP 25
2
VDD (LO AMP)
IFOUT/VDD (IF AMP, MIX) 26
1
LOIN
26 pin – HSOF (Plastic)
–2–
VDD
(LO AMP)
LOIN
CXG1051AFN
Electrical Characteristics
1. Control Pin Logic for Antenna Switch
Conditions of control pins
ANT – TX
ANT – RX
VCTL1 = 3V, VCTL2 = 0V
ON
OFF
VCTL1 = 0V, VCTL2 = 3V
OFF
ON
2. Power Amplifier Block + Antenna Switch Transmitter Block
These specifications are those when the Sony's recommended evaluation board, shown on page 6, is used.
Unless otherwise specified: VDD = 3V, VPCTL = 2V, VCTL1 = 3V, VCTL2 = 0V,
IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz, Ta = 25°C
Item
Measurement conditions
Symbol
Min. Typ. Max. Unit
Current consumption
IDD
150
mA
Gate voltage adjustment value
VGG
0.04 0.25 0.60
V
Output power
POUT
Power gain
GP
Adjacent channel leak power ratio
(600 ± 100kHz)
ACPR600kHz
Measured with the ANT pin
–63
–55
dBc
Adjacent channel leak power ratio
(900 ± 100kHz)
ACPR900kHz
Measured with the ANT pin
–70
–60
dBc
Occupied bandwidth
OBW
Measured with the ANT pin
250
275
kHz
Measured with the ANT pin
20.2
36
dBm
dB
39
2nd-order harmonic level
—
Measured with the ANT pin
–25
dBc
3rd-order harmonic level
—
Measured with the ANT pin
–25
dBc
3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block
These specifications are those when the Sony's recommended evaluation board, shown on page 6, is used.
Unless otherwise specified: VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF1 = 1.90GHz/–35dBm,
LO = 1.66GHz/–15dBm, Ta = 25°C
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Current consumption
IDD
When no signal
5.5
Conversion gain
GC
When a small signal
Noise figure
NF
Input IP3
IIP3
When a small signal
∗1
Image suppression ratio
IMR
RF2 = 1.42GHz/–35dBm
30
40
dBc
1/2 IF suppression ratio
1/2IFR
RF2 = 1.78GHz/–35dBm
39
44
dBc
17
7.5
20.5
4.2
–17.5 –13
mA
dB
5.5
dB
dBm
2 × LO–IF suppression ratio
—
RF2 = 3.08GHz/–35dBm
39
47
dBc
2 × LO+IF suppression ratio
—
RF2 = 3.56GHz/–35dBm
24
62
dBc
–42
–37 dBm
LO to ANT leak
PLK
∗1 Conversion from IM3 suppression ratio during FR1 = 1.9000GHz/–35dBm and FR2 = 1.9006GHz/–35dBm input.
–3–
CXG1051AFN
Example of Representative Characteristics
1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C)
POUT, ACPR600kHz vs. PIN
POUT
15
–50
10
–55
5
–60
ACPR600kHz
0
–35
–30
–25
–20
–15
–70
–10
–50
30
–55
25
–60
ACPR600kHz
–65
15
0
0.5
1.0
1.5
2.0
2.5
VPCTL – Gain control voltage [V]
POUT, ACPR600kHz vs. VDD
Gp, ACPR600kHz vs. IDD
22
POUT – Output power [dBm]
35
PIN – Input power [dBm]
VDD = var., VPCTL = 2V, VGG = const., VCTL1 = 3V,
VCTL2 = 0V
IDD = 150mA (@VDD = 3V, POUT = 20.2dBm),
PIN = –19.3dBm
–40
23
–45
POUT
21
–50
20
–55
ACPR600kHz
19
18
17
2.0
–45
20
–60
–65
2.5
3.0
3.5
4.0
4.5
–70
5.0
–70
3.0
VDD = 3V, VPCTL = 2V, VGG = var., VCTL1 = 3V,
VCTL2 = 0V
IDD = var., PIN = var., POUT = 20.2dBm
Gp – Power gain [dB]
–5
–40
–65
GP
40
42
–40
41
–45
GP
40
–50
39
–55
ACPR600kHz
38
–60
37
–65
36
100
VDD – Supply voltage [V]
120
140
160
180
200
IDD – Current consumption [mA]
–4–
–70
220
ACPR600kHz – Adjacent channel leak power rario [dBc]
–45
ACPR600kHz – Adjacent channel leak power rario [dBc]
20
VDD = 3V, VPCTL = var., VGG = const., VCTL1 = 3V,
VCTL2 = 0V
IDD = 150mA (@VPCTL = 2V),
PIN = var., POUT = 20.2dBm
45
–40
Gp – Power gain [dB]
–40
ACPR600kHz – Adjacent channel leak power rario [dBc]
POUT – Output power [dBm]
25
ACPR600kHz – Adjacent channel leak power rario [dBc]
Gp, ACPR600kHz vs. VPCTL
VDD = 3V, VPCTL = 2V, VGG = const., VCTL1 = 3V,
VCTL2 = 0V
IDD = 150mA (@POUT = 20.2dBm),
PIN = var.
CXG1051AFN
2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C)
GC, NF vs. PLO
5.50
22
5.25
GC
20
5.00
19
4.75
4.50
18
NF – Noise figure [dB]
GC – Convertion gain [dB]
21
NF
17
4.25
16
–25
4.00
–20
–15
–10
–5
0
PLO – Local input [dBm]
Input IP3, PLK vs. PLO
Input IP3 [dBm]
Input IP3
–12
–35
–14
–40
–16
–45
PLK
–18
–50
–20
–55
PLK – LO to ANT leak level [dBm]
–30
–10
–60
–20
–15
–10
VDD = 3V, VCTL1 = 0V, VCTL2 = 3V,
RF1 = 1.9000GHz, RF2 = 1.9006GHz,
LO = 1.66GHz/–15dBm
20
0
POUT
–20
–40
PIM3
–60
–80
Input IP3
–100
–50
–40
–30
–20
–10
PIN – RF input power [dBm]
VDD = 3V, VCTL1 = 0V, VCTL2 = 3V,
RF = 1.90GHz/–35dBm,
LO = 1.66GHz
–22
–25
POUT – IF output power,
PIM3 – 3rd-order intermodulation distortion power [dBm]
POUT, PIM3 vs. PIN
VDD = 3V, VCTL1 = 0V, VCTL2 = 3V,
RF = 1.90GHz/small signal,
LO = 1.66GHz
–5
0
PLO – Local input [dBm]
–5–
0
CXG1051AFN
Recommended Evaluation Board
Via Hole
VGG
PAIN
VPCTL
VDD_PA
VCTL1
VCTL2
ANT
VDD_LNA
VDD_LO
IFOUT
LOIN
VDD_IF
Via Hole
Glass fabric-base epoxy board (4 layers)
Thickness between layers 1 and 2: 0.2mm
Dimensions: 50mm × 50mm
Enlarged Diagram of External Circuit Block
R1
R1 = 1kΩ
R2 = 3.3kΩ
C8
C8
C7
L2
L6
C8
C1
L2
L6
C6
C9
L1
C6
C6
C7
C6
C3
L3
C7
C4
L5
L4
L1 = 1.8nH
L2 = 2.2nH
L3 = 3.9nH
L4 = 6.8nH
L5 = 10nH
L6 = 18nH
L7 = 82nH
C4
R2
C10
C5
C2
C8
L7
C8
–6–
C8
C1 = 1pF
C2 = 5pF
C3 = 10pF
C4 = 13pF
C5 = 18pF
C6 = 30pF
C7 = 100pF
C8 = 1nF
C9 = 10nF
C10 = 100nF
CXG1051AFN
Package Outline
Unit: mm
HSOF 26PIN(PLASTIC)
0.08
0.45 ± 0.15
0.9 ± 0.1
S
*5.6 ± 0.05
5.5
4.2
A
0.4
0.5
(1.5)
(0.7)
4.4 ± 0.1
(1.75)
14
3.8 ± 0.05
26
13
1
0.4
S
0.2
4.4
0.2
0.07 M S A
(0.2)
0.2 ± 0.05
+ 0.05
0.2 0
Solder Plating
B
+ 0.05
0.14 – 0.03
DETAILB
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.06g
HSOF-26P-01
SONY CODE
Kokubu Ass'y
HSOF 26PIN(PLASTIC)
0.08
0.45 ± 0.15
0.9 ± 0.1
S
*5.6 ± 0.05
5.5
4.2
A
0.4
0.5
(1.5)
(0.7)
4.4 ± 0.1
(1.75)
14
3.8 ± 0.05
26
13
1
0.4
S
4.4
0.2
0.2
0.07 M S A
(0.2)
0.2 ± 0.05
+ 0.05
0.2 0
Solder Plating
B
+ 0.05
0.14 – 0.03
DETAILB
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.06g
SONY CODE
HSOF-26P-01
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
–7–
Sony Corporation
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.