Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA # " %$ % ! ! ! $ The MC74F803 is a high-speed, low-power, quad D-type flip-flop featuring separate D-type inputs, and inverting outputs with closely matched propagation delays. With a buffered clock (CP) input that is common to all flip-flops, the F803 is useful in high-frequency systems as a clock driver, providing multiple outputs that are synchronous. Because of the matched propagation delays, the duty cycles of the output waveforms in a clock driver application are symmetrical within 1.0 to 1.5 nanoseconds. • • • • CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock J SUFFIX CERAMIC CASE 632-08 Matched Outputs for Synchronous Clock Driver Applications Outputs Guaranteed for Simultaneous Switching 14 1 Pinout: 14-Lead Plastic (Top View) VCC 14 NC O3 D3 D2 O2 CP 13 12 11 10 9 8 N SUFFIX PLASTIC CASE 646-06 14 1 1 2 3 4 5 6 7 GND NC O0 D0 D1 O1 GND D SUFFIX SOIC CASE 751A-03 14 1 GUARANTEED OPERATION RANGES Symbol Parameter Min Typ Max Unit 4.5 5.0 5.5 V LOGIC SYMBOL VCC Supply Voltage TA Operating Ambient Temperature Range 0 25 70 °C 4 5 10 11 IOH Output Current — High — — –20 mA D0 D1 D2 D3 IOL Output Current — Low — — 24 mA O0 O1 O2 O3 3 6 9 12 8 CP LOGIC DIAGRAM D0 D1 D2 D3 CP CP D CP D CP D CP D Q Q Q Q O0 O1 O2 O3 VCC = PIN 14 GND = PINS 1 AND 7 NC = PINS 2 AND 13 11/93 Motorola, Inc. 1994 REV 3 MC74F803 FUNCTIONAL DESCRIPTION The F803 consists of four positive edge-triggered flip-flops with individual D-type inputs and inverting outputs. The buffered clock is common to all flip-flops and the following specifications allow for outputs switching simultaneously. The four flip-flops store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. The maximum frequency of the clock input is 70 megahertz, and the LOW-to-HIGH and HIGH-to-LOW propagation delays of the O1 output vary by, at most, 1 nanosecond. Therefore, the device is ideal for use as a divide-by-two driver for high-frequency clock signals that require symmetrical duty cycles. The difference between the LOW-to-HIGH and HIGH-to-LOW propagation delays for the O0, O2, and O3 outputs vary by at most 1.5 nanoseconds. These outputs are very useful as clock drivers for circuits with less stringent requirements. In addition, the output-to-output skew is a maximum of 1.5 nanoseconds. Finally, the IOH specification at 2.5 volts is guaranteed to be at least – 20 milliamps. If their inputs are identical, multiple outputs can be tied together and the IOH is commensurately increased. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions* VIH Input HIGH Voltage 2.0 — — V Guaranteed Input HIGH Voltage VIL Input LOW Voltage — — 0.8 V Guaranteed Input LOW Voltage VIK Input Clamp Diode Voltage — — – 1.2 V IIN = –18 mA VCC = MIN VOH Output HIGH Voltage 2.5 — — V IOH = –20 mA VCC = 4.5 V VOL Output LOW Voltage — 0.35 0.5 V IOL = 24 mA VCC = MIN — — 20 µA VIN = 2.7 V VCC = MAX IIH Input HIGH Current — — 100 VIN = 7.0 V VCC = MAX IIL Input LOW Current — — –0.6 mA VIN = 0.5 V VCC = MAX IOS Output Short Circuit Current –60 — –150 mA VOUT = 0 V VCC = MAX (Note 2) ICC Power Supply Current — — 70 mA VCC = MAX * Normal test conditions for this device are all four outputs switching simultaneously. Two outputs of the 74F803 can be tied together and the IOH doubles. 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 0 to 70°C, VCC = 5.0 V ± 10%, see Note 1) CL = 50 pF Symbol Parameter CL = 100 pF Min Max Min Max Unit fmax Maximum Clock Frequency 70 — 50 — MHz tPLH tPHL Propagation Delay CP to On 3.0 7.5 3.0 10 ns tPv Propagation Delay CP to On Variation (see Note 3) — 3.0 — 4.0 ns tps O1 Propagation Delay Skew |tPLH Actual – tPHL Actual| for O1 Only — 1.0 — 2.0 ns tps O0, O2, O3 Propagation Delay Skew |tPLH Actual – tPHL Actual| for O0, O2, O3 — 1.5 — 2.0 ns tos Output to Output Skew (see Note 2) |tp On – tp Om| — 1.5 — 2.5 ns trise, tfall O1 Rise/Fall Time for O1 (0.8 to 2.0 V) — 3.0 — 4.0 ns trise, tfall O0, O2, O3 Rise/Fall Time for O0, O2, O3 (0.8 to 2.0 V) — 3.5 — 4.5 ns 1. The test conditions used are all four outputs switching simultaneously. The AC characteristics described above (except for O1) are also guaranteed when two outputs are tied together. 2. Where tp On and tp Om are the actual propagation delays (any combination of high or low) for two separate outputs from a given high transition of CP. 3. For a given set of conditions (i.e., capacitive load, temperature, VCC, and number of outputs switching simultaneously) the variation from device to device is guaranteed to be less than or equal to the maximum. MOTOROLA 2 TIMING SOLUTIONS BR1333 — REV 4 MC74F803 AC OPERATING REQUIREMENTS (TA = 0 to 70°C, VCC = 5.0 V ± 10%) CL = 50 pF Symbol Parameter CL = 100 pF Min Max Min Max Unit ts(H) ts(L) Setup Time, HIGH or LOW Dn to CP 3.0 3.0 — — 4.0 4.0 — — ns tf tp + ts (see Note) — 9.0 — 12 ns th(H) th(L) Hold Time, HIGH or LOW Dn to CP 2.0 2.0 — — 2.0 2.0 — — ns tw(H) CP Pulse Width 7.0 — 8.0 — ns tw(L) HIGH or LOW 6.0 — 8.0 — The combination of the setup time (ts) requirement and maximum propagation delay (tp) are guaranteed to be within this limit for all conditions. APPLICATION NOTE The closely matched outputs of the MC74F803 provide an ideal interface for the clock input of Motorola’s high-frequency microprocessors. 74F803 INTERFACE AS CLOCK TO MC68020 SYSTEM MC68020/MC68030 E1 CLK VCC MC68881/MC68882 33CLK1 14 C2 MC74F803 4 5 10 74F04 1 2 11 1 D0 O0 D1 O1 D2 O2 D3 O3 CLK 3 VCC 6 RU 9 33CLK2 (40 mA OUTPUT DRIVE) 12 RT 7 CP 8 33CLK CLK TIMING SOLUTIONS BR1333 — REV 4 66 MHz MOTOROLA 3 MC74F803 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 632-08 -A14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 5. 632-01 THRU -07 OBSOLETE, NEW STANDARD 632-08. -BC -T- L K SEATING PLANE F G D 14 PL 0.25 (0.010) M N J 14 PL M T A 0.25 (0.010) S M T B N SUFFIX PLASTIC PACKAGE CASE 646-06 14 8 1 7 A NOTE 4 F DIM A B C D F G H J K L M N L C J N G H S D K SEATING PLANE M D SUFFIX SOIC PACKAGE CASE 751A-02 8 P -B- 0.25 (0.010) M B M 7 PL 1 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC10° 0° 0.39 7 K D 14 PL 0.25 (0.010) R X 45° C G M T B S A S SEATING PLANE M F INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC ° ° 15 0 0.020 0.040 1.01 INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0° 10° 0.015 0.039 NOTES: 1. DIMENSIONS “A” AND “B” ARE DATUMS AND “T” IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. CONTROLLING DIMENSION: MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 6. 751A-01 IS OBSOLETE, NEW STANDARD 751A-02. -A14 MILLIMETERS MIN MAX 19.05 19.94 7.11 6.23 5.08 3.94 0.50 0.39 1.65 1.40 2.54 BSC 0.38 0.21 4.31 3.18 7.62 BSC ° ° 15 0 1.01 0.51 NOTES: 1. LEADS WITHIN 0.13 mm (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION “L” TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 5. 646-05 OBSOLETE, NEW STANDARD 646-06. B MOTOROLA 4 DIM A B C D F G J K L M N J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 ° ° 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 ° ° 7 0 0.229 0.244 0.010 0.019 TIMING SOLUTIONS BR1333 — REV 4 MC74F803 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, ASIA-PACIFIC: Tai Po, N.T., Hong Kong. TIMING SOLUTIONS BR1333 — REV 4 ◊ CODELINE TO BE PLACED HERE *MC74F803/D* MC74F803/D MOTOROLA 5