Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA !%! $ & # # ! # &" The MC74F1803 is a high–speed, low–power, quad D–type flip–flop featuring separate D–type inputs and inverting outputs with closely matched propagation delays. With a buffered clock (CP) input that is common to all flip–flops, the MC74F1803 is useful in high–frequency systems as a clock driver, providing multiple outputs that are synchronous. Because of the matched propagation delays, the duty cycles of the output waveforms in a clock driver application are symmetrical within 2.0 nanoseconds. • • • • CLOCK DRIVER QUAD D–TYPE FLIP–FLOP WITH MATCHED PROPAGATION DELAYS Edge–Triggered D–Type Inputs Buffered Positive Edge–Triggered Clock Matched Outputs for Synchronous Clock Driver Applications N SUFFIX PLASTIC CASE 646–06 Outputs Guaranteed for Simultaneous Switching 14 1 Pinout: 14–Lead Plastic (Top View) VCC 14 NC 13 O3 12 D3 11 D2 10 O2 CP 9 8 D SUFFIX SOIC CASE 751A–03 14 1 LOGIC SYMBOL 1 2 3 4 5 6 7 GND NC O0 D0 D1 O1 GND 8 LOGIC DIAGRAM D1 D0 CP D CP D2 D CP D CP D Q Q Q Q O0 O1 O2 O3 10 11 D0 D1 D2 D3 O0 O1 O2 O3 3 6 9 12 CP VCC = PIN 14 GND = PINS 1 AND 7 NC = PINS 2 AND 13 VCC = Pin 14; GND = Pins 1,7; NC = Pins 2, 13 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 7/95 1 5 D3 CP Motorola, Inc. 1995 4 REV 4 MC74F1803 FUNCTIONAL DESCRIPTION The MC74F1803 consists of four positive edge–triggered flip–flops with individual D–type inputs and inverting outputs. The buffered clock is common to all flip–flops and the following specifications allow for outputs switching simultaneously. The four flip–flops store the state of their individual D inputs that meet the setup and hold time requirements on the LOW–to–HIGH Clock (CP) transition. The maximum frequency of the clock input is 70 megahertz and the LOW–to–HIGH and HIGH–to–LOW propagation delays of the On output vary by at most, 2.0 nanoseconds. Therefore, the device is ideal for use as a divide–by–two driver for high–frequency clock signals that require symmetrical duty cycles. In addition, the output–to–output skew is a maximum of 2.0 nanoseconds. Finally, the IOH specification at 2.5 volts is guaranteed to be at least –20 milli–amps. If their inputs are identical, multiple outputs can be tied together and the IOH is commensurately increased. GUARANTEED OPERATION RANGES Symbol Parameter Min Typ Max Unit 4.5 5.0 5.5 V VCC Supply Voltage TA Operating Ambient Temperature Range 0 25 70 °C IOH Output Current — High — — –20 mA IOL Output Current — Low — — 24 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions 1,2 VIH Input HIGH Voltage 2.0 – – V Guaranteed Input HIGH Voltage VIL Input LOW Voltage – – 0.8 V Guaranteed Input LOW Voltage VIK Input Clamp Diode Voltage – – –1.2 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage An Outputs 74 2.5 – – V IOH = –20 mA VCC =4.5 V VOL Output LOW Voltage An Outputs 74 – 0.35 0.5 V IOL = 24 mA VCC = MIN IIH Input HIGH Current – – 20 µA VCC = MAX, VIN = 2.7 V – – 100 µA VCC = MAX, VIN = 7.0 V – – –0.6 mA VCC = MAX, VIN = 0.5 V –60 – –150 mA VCC = MAX, VOUT = 0 V – – 70 mA VCC = MAX IIL Input LOW Current IOS Output Short Circuit Current 3 ICC Power Supply Current 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Normal test conditions for this device are all four outputs switching simultaneously. Two outputs of the MC74F1803 can be tied together and the IOH doubles. 3. Not more than one output should be shorted at a time, nor for more than 1 second. AC OPERATING REQUIREMENTS (TA = 0°C to +70°C: VCC = +5.0 V ±10%: RL = 500 Ω) CL = 50 pF Symbol Parameter Min Max Unit 3.0 3.0 – – ns – 9.0 ns ts(H) ts(L) Setup Time, HIGH or LOW: Dn to CP tf tp + ts 1 th(H) th(L) Hold Time, HIGH or LOW: Dn to CP 2.0 2.0 – – ns tw(H) tw(L) Cp Pulse Width HIGH or LOW 7.0 6.0 – – ns 1. The combination of the setup time (ts) requirement and maximum propagation delay (tp) are guaranteed to be within this limit for all conditions. MOTOROLA 2 TIMING SOLUTIONS BR1333 — REV 5 MC74F1803 AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C: VCC = +5.0 V ±10%: RL = 500 Ω) 1 CL = 50 pF Min Max Unit fmax Symbol Maximum Clock Frequency Parameter 70 – MHz tPLH tPHL Propagation Delay CP to On 3.0 7.5 ns tPv Propagation Delay CP to On Variation – 3.0 ns tps O0, O1, O2, O3, Propagation Delay Skew |tPLH Actual – tPHL Actual| for O0, O1, O2, O3 – 2.0 ns tos Output to Output Skew 2 |tp On – tp Om| – 2.0 ns trise, tfall O1, Rise/Fall Time for O1 (0.8 to 2.0 V) – 3.0 ns trise, tfall O0, O2, O3, Rise/Fall Time for O1, O2, O3, (0.8 to 2.0 V) – 3.5 ns 1. The test conditions used are all four outputs switching simultaneously. The AC characteristics described above are also guaranteed when two outputs are tied together. 2. Where tp On and tp Om are the actual propagation delays (any combination of high or low) for two separate outputs from a given high transition of CP. 3. For a given set of conditions (i.e., capacitive load, temperature, VCC, and number of outputs switching simultaneously) the variation from device to device is guaranteed to be less than or equal to the maximum. TYPICAL MC74F1803 APPLICATION VCC 33 MHz Clock 14 4 5 D0 O0 D1 O1 3 6 MC74F1803 10 74F04 1 O2 D2 33 MHz Clock (40 mA Output Drive) 11 D3 2 9 O3 12 7 1 33 MHz Clock CP 8 CLK 66 MHz TIMING SOLUTIONS BR1333 — REV 5 3 MOTOROLA MC74F1803 OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646-06 14 8 1 7 NOTES: 1. LEADS WITHIN 0.13 mm (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION “L” TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 5. 646-05 OBSOLETE, NEW STANDARD 646-06. B A NOTE 4 F DIM A B C D F G H J K L M N L C J N G H D K SEATING PLANE M D SUFFIX SOIC PACKAGE CASE 751A-02 8 P -B- B M M 7 PL 1 7 K D 14 PL 0.25 (0.010) R X 45° C G MOTOROLA 0.25 (0.010) 0.39 M T B S A SEATING PLANE M F S 4 1.01 INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0° 10° 0.015 0.039 NOTES: 1. DIMENSIONS “A” AND “B” ARE DATUMS AND “T” IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. CONTROLLING DIMENSION: MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 6. 751A-01 IS OBSOLETE, NEW STANDARD 751A-02. -A14 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 10° 0° J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 ° ° 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 ° ° 7 0 0.229 0.244 0.010 0.019 TIMING SOLUTIONS BR1333 — REV 5 MC74F1803 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 TIMING SOLUTIONS BR1333 — REV 5 ◊ CODELINE 5 *MC74F1803/D* MC74F1803/D MOTOROLA