MOTOROLA MTW14N50E

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SEMICONDUCTOR TECHNICAL DATA
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TMOS POWER FET
14 AMPERES
500 VOLTS
RDS(on) = 0.40 OHM
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Designed to Replace External Zener Transient Suppressor —
Absorbs High Energy in the Avalanche Mode
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
D
G
CASE 340K–01, Style 1
TO–247AE
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
500
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
500
Vdc
Gate–Source Voltage — Continuous
VGS
± 20
Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
14
9.0
60
Adc
Total Power Dissipation
Derate above 25°C
PD
180
1.44
Watts
W/°C
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vpk, IL = 14 Apk, L = 8.8 mH, RG = 25 Ω )
EAS
860
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.7
40
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MTW14N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
500
—
—
520
—
—
Vdc
mV/°C
—
—
—
—
250
1000
—
—
100
nAdc
2.0
—
3.2
7.0
4.0
—
Vdc
mV/°C
—
0.32
0.40
Ohm
—
—
—
—
6.7
5.6
gFS
5.0
—
—
mhos
Ciss
—
2510
3510
pF
Coss
—
280
392
Crss
—
67
94
td(on)
—
28
60
tr
—
80
160
td(off)
—
80
160
tf
—
60
120
QT
—
65
85
Q1
—
17
—
Q2
—
47
—
Q3
—
34
—
VSD
—
—
1.0
09
0.9
1.6
—
Vdc
trr
—
390
—
ns
ta
—
245
—
tb
—
145
—
QRR
—
5.35
—
µC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
—
5.0
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
—
13
—
nH
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 V, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0)
(VDS = 500 Vdc, VGS = 0, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
µAdc
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 7.0 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 14 Adc)
(ID = 7.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 7.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc,
Vdc VGS = 0,
0
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS* ✝
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 250 Vdc,
Adc,
Vd ID = 14 Ad
VGS = 10 Vdc
Vdc,
RG = 4.7 Ω))
Fall Time
Gate Charge
Vd , ID = 14 Adc,
Ad ,
( DS = 400 Vdc,
(V
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
g
((IS = 14 Adc,, VGS = 0))
(IS = 14 Adc, VGS = 0, TJ = 125°C)
Reverse Recovery Time
((IS = 14 Adc,
Ad , VGS = 0,
0,
dIS/dt = 100 A/µs, VGS = 0)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
✝ Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTW14N50E
TYPICAL ELECTRICAL CHARACTERISTICS
20
TJ = 25°C
14
12
10
8
VGS = 5 V
6
4
2
0
1
3
9
TJ = 100°C
8
25°C
6
4
0
10
VGS = 10V
0.6
TJ = 100°C
0.4
TJ = 25°C
0.2
TJ = –55°C
4
8
12
16
20
ID, DRAIN CURRENT (AMPS)
28
24
0
9
10
0.36
TJ = 25°C
0.34
0.32
0.30
0.28
VGS = 10 V
0.26
VGS = 15 V
0.24
0.22
0.20
0
4
8
12
16
20
ID, DRAIN CURRENT (AMPS)
24
28
Figure 4.On–Resistance versus Drain Current
100000
I DSS , DRAIN-TO-SOURCE LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.5
1
0.38
Figure 3.On–Resistance versus Drain Current
2.0
1.5
1.0
VGS = 10 V
ID = 7 A
0.5
0
– 50
– 55°C
Figure 2. Transfer Characteristics
8
0.8
0
10
Figure 1. On–Region Characteristics
6
1.0
0.0
12
2
3
4
5
6
7
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
4
7
14
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
2
5
16
2
4V
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
VDS ≥ 10 V
18
6V
16
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
18
20
7V
10 V
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
200
Figure 5.On–Resistance Variation
With Temperature
Motorola TMOS Power MOSFET Transistor Device Data
VGS = 0 V
20000
10000
TJ = 125°C
2000
1000
TJ = 100°C
200
100
TJ = 25°C
20
10
0
100
200
300
400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
500
Figure 6.Drain–To–Source Leakage
Current versus Voltage
3
MTW14N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 10) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000
7000
10000
TJ = 25°C
VDS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
2000
6000
5000
4000
Ciss
3000
2000
0
10
1000
200
Coss
100
Crss
Coss
1000
20
Crss
5
0
VGS
5
VGS = 0 V
Ciss
VGS = 0 V
10
15
20
25
VDS
10
1
2
20
10
100 200
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Low Voltage Capacitance Variation
4
Figure 7b. High Voltage Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
500
TJ = 25°C
ID = 14 A
VDS = 400 V
VDS
12
QT
400
9
300
Q1
6
200
Q2
VGS
3
0
100
Q3
0
10
20
30
40
50
60
70
80
90
0
100
10000
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
15
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTW14N50E
td(off)
TJ = 25°C
ID = 14 A
VDD = 250 V
VGS = 10 V
2000
1000
td(on)
200
100
tr
20
tf
10
1
2
10
20
100
200
QT, TOTAL CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
1000
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
14
TJ = 25°C
VGS = 0 V
dIS/dt = 100 A/µs
12
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive
pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in
AN569, “Transient Thermal Resistance–General Data and Its
Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10µs. In addition the total power averaged
over a complete switching cycle must not exceed (TJ(MAX) –
TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used in
switching circuits with unclamped inductive loads. For reliable
Motorola TMOS Power MOSFET Transistor Device Data
operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
I D , DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
20
10 µs
100 µs
10
1 ms
2
10 ms
1
THERMAL LIMIT
PACKAGE LIMIT
RDS(on) LIMIT
0.2
0.1
1
2
dc
20
10
100 200
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
MTW14N50E
900
800
600
500
400
300
200
100
0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
25
150
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1
PEAK ID = 14 A
VDD = 50 V
700
D = 0.5
= 0.2
0.2
0.1
= 0.1
= 0.05
= 0.02
= 0.01
0.02
0.01
RθJC(t) = r(t) RθJC
RθJC = 0.7°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
SINGLE PULSE
0.002
DUTY CYCLE, D = t1/t2
P(pk)
t1
t2
0.001
0.01
0.02
0.1
0.2
1
2
t, TIME (ms)
10
20
100
200
1000
Figure 13. Thermal Response
6
Motorola TMOS Power MOSFET Transistor Device Data
MTW14N50E
PACKAGE DIMENSIONS
0.25 (0.010)
M
–T–
–Q–
T B M
E
–B–
C
4
L
U
A
R
1
K
2
3
STYLE 1:
PIN 1.
2.
3.
4.
–Y–
P
V
H
F
D
0.25 (0.010)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
Y Q
J
G
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
E
F
G
H
J
K
L
P
Q
R
U
V
MILLIMETERS
MIN
MAX
19.7
20.3
15.3
15.9
4.7
5.3
1.0
1.4
1.27 REF
2.0
2.4
5.5 BSC
2.2
2.6
0.4
0.8
14.2
14.8
5.5 NOM
3.7
4.3
3.55
3.65
5.0 NOM
5.5 BSC
3.0
3.4
INCHES
MIN
MAX
0.776
0.799
0.602
0.626
0.185
0.209
0.039
0.055
0.050 REF
0.079
0.094
0.216 BSC
0.087
0.102
0.016
0.031
0.559
0.583
0.217 NOM
0.146
0.169
0.140
0.144
0.197 NOM
0.217 BSC
0.118
0.134
S
CASE 340K–01
ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7
MTW14N50E
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8
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*MTW14N50E/D*
Motorola TMOS Power MOSFET TransistorMTW14N50E/D
Device Data