MOTOROLA MTY10N100E

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by MTY10N100E/D
SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
10 AMPERES
1000 VOLTS
RDS(on) = 1.3 OHM
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. Designed for high voltage and high speed
switching applications in power supplies, converters and PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
•
•
•
•

Robust High Voltage Termination
Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
D
G
CASE 340G–02, STYLE 1
TO–264
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
1000
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
1000
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous @ TC = 25°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
IDM
10
30
Amps
Total Power Dissipation
Derate above 25°C
PD
250
2.0
Watts
W/°C
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 10 Apk, L = 10 mH, RG = 25 Ω )
EAS
500
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.5
30
°C/W
TL
260
°C
Rating
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
TMOS
Motorola
Motorola, Inc.
1995 Power MOSFET Transistor Device Data
1
MTY10N100E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
1000
1000
—
—
—
1.254
—
—
—
Vdc
—
—
—
—
—
—
5.0
10
100
—
—
±100
nAdc
2.0
—
3.0
7.0
4.0
—
Vdc
mV/°C
—
1.10
1.3
Ohm
—
—
11
—
15
15.3
gFS
8.0
10
—
mhos
Ciss
—
3500
5600
pF
Coss
—
264
530
Crss
—
52
90
td(on)
—
29
60
tr
—
57
120
td(off)
—
118
240
tf
—
70
140
QT
—
100
120
Q1
—
18.4
—
Q2
—
33
—
Q3
—
36.7
—
—
—
0.885
0.8
1.1
—
trr
—
885
—
ta
—
220
—
tb
—
667
—
QRR
—
8.0
—
—
3.5
4.5
—
—
7.5
—
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
(VGS = 0, ID = 3.0 mA)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
V/°C
µAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 5.0 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 10 Adc)
(ID = 5.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS ≥ 8.0 Vdc, ID = 5.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 500 Vdc, ID = 10 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 10 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 10 Adc, VGS = 0 Vdc)
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
nH
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTY10N100E
TYPICAL ELECTRICAL CHARACTERISTICS
20
20
TJ = 25°C
12
10
5V
6
4
2
0
2
4
6
8
12
10
8
100°C
6
25°C
4
TJ = 55°C
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
TJ = 100°C
2
1.6
25°C
1.2
0.8
–55°C
0.4
0
14
0
10 12 14 16 18 20 22 24 26 28 30
2.4
0
16
2
4V
2
4
6
8
10
12
16
14
20
18
5.6
6
18
20
1.56
TJ = 25°C
1.48
1.4
1.32
VGS = 10 V
1.24
15 V
1.16
1.08
1.00
0
2
4
6
8
10
12
14
16
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.8
100000
VGS = 0 V
VGS = 10 V
ID = 10 A
2.4
2
100°C
1000
1.6
1.2
0.8
100
25°C
10
0.4
0
– 50
TJ = 125°C
10000
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
I D , DRAIN CURRENT (AMPS)
14
8
VDS ≥ 10 V
18
6V
16
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
18
VGS = 10 V
– 25
0
25
50
75
100
125
150
1
0
100 200
300
400
500
600
700
800
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
900 1000
3
MTY10N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000
VDS = 0 V
10000
VGS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
Ciss
TJ = 25°C
6000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
7000
5000
Crss
4000
Ciss
3000
2000
Coss
1000
Coss
100
Crss
1000
Crss
0
10
5
0
VGS
5
10
15
20
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
4
25
10
10
100
1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Motorola TMOS Power MOSFET Transistor Device Data
QT
12
480
10
400
VGS
8
Q1
6
320
Q2
240
TJ = 25°C
ID = 10 A
4
80
2
0
160
VDS
Q3
0
10
20
30
40
50
60
70
80
90
1000
VDD = 480 V
ID = 10 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
560
14
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTY10N100E
100
td(off)
tf
tr
td(on)
0
100
10
0
10
RG, GATE RESISTANCE (OHMS)
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate Charge versus Gate–to–Source Voltage
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
10
I S , SOURCE CURRENT (AMPS)
9
VGS = 0 V
TJ = 25°C
8
7
6
5
4
3
2
1
0
0.5
0.54
0.58 0.62 0.66
0.7
0.74
0.78 0.82
0.86
0.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTY10N100E
SAFE OPERATING AREA
10
500
10 µs
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
100 µs
1
1 ms
10 ms
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.01
0.1
1
10
dc
100
ID = 10 A
400
300
200
100
0
1000
25
50
75
100
125
150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
P(pk)
0.05
0.1
0.02
0.01
t1
SINGLE PULSE
t2
DUTY CYCLE, D = t1/t2
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTY10N100E
PACKAGE DIMENSIONS
0.25 (0.010)
M
T B
M
–Q–
–B–
–T–
C
E
U
N
A
1
R
2
L
3
–Y–
P
K
W
F 2 PL
G
J
H
D 3 PL
0.25 (0.010)
M
Y Q
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
DIM
A
B
C
D
E
F
G
H
J
K
L
N
P
Q
R
U
W
MILLIMETERS
MIN
MAX
2.8
2.9
19.3
20.3
4.7
5.3
0.93
1.48
1.9
2.1
2.2
2.4
5.45 BSC
2.6
3.0
0.43
0.78
17.6
18.8
11.0
11.4
3.95
4.75
2.2
2.6
3.1
3.5
2.15
2.35
6.1
6.5
2.8
3.2
INCHES
MIN
MAX
1.102
1.142
0.760
0.800
0.185
0.209
0.037
0.058
0.075
0.083
0.087
0.102
0.215 BSC
0.102
0.118
0.017
0.031
0.693
0.740
0.433
0.449
0.156
0.187
0.087
0.102
0.122
0.137
0.085
0.093
0.240
0.256
0.110
0.125
STYLE 1:
PIN 1. GATE
2. DRAIN
3. SOURCE
CASE 340G–02
TO–264
ISSUE E
Motorola TMOS Power MOSFET Transistor Device Data
7
MTY10N100E
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8
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*MTY10N100E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTY10N100E/D