January 1997 ML6680 Token Ring Copper-to-Fiber Converter GENERAL DESCRIPTION FEATURES The ML6680 is a single-chip conversion between Token Ring ISO/IEC8802-5 copper-based media and Token Ring ISO/IEC8802-5 fiber-based media. The ML6680 fiber-optic interface contains a data quantizer, circuitry for fiber optic key signal generation and recognition, pin-selectable signal switching, and current driven transmitter outputs. ■ The ML6680 copper interface consists of a twisted pair line equalizer, receive squelch circuit, pin selectable phantom wire fault detection and signal switching, and a transmit driver. This section supports the ISO/IEC8802-5 standard requirements. The ML6680 provides an optional PECL compatible interface. The ML6680 may be configured to one of four modes: 1. 2. 3. 4. Standard Media Converter Concentrator Media Converter Lobe or Ring Out Port Media Converter Ring In Port Media Converter ■ ■ ■ ■ ■ ■ ■ ■ Single-chip copper-to-fiber converter for Token Ring 16Mbps and 4Mbps data rates with the same external components Four modes of operation covering a wide variety of applications Full duplex operation Highly stable data quantizer with 55dB input dynamic range Current driven fiber optic LED driver for accurate launch power Current driven output for low RFI noise and low jitter Capable of driving 100Ω UTP or 150Ω STP Pin selectable phantom wire fault detection and signal switching BLOCK DIAGRAM EQA EQB RTSETOP TPINP TPINN TPINOK OPVCC TWISTED PAIR EQUALIZER LED DRIVER TWISTED PAIR RECEIVE SQUELCH SIGNAL MUX FIBER OPTIC RECEIVE SQUELCH OPOUT OPINOK RTSETTP TPOUTP TPOUTN OPINP TWISTED PAIR DRIVER FIBER OPTIC QUANTIZER OPINN VDC PHTM1 PHTM2 PHANTOM DRIVER CONTROL LOGIC BIAS XTAL1 CRYSTAL OSCILLATOR KEYGEN XTAL2 INSERTED 1 ML6680 PIN CONFIGURATION EQB EQA VCC2 XTAL1 XTAL2 QVCC OPINP ML6680 28-Pin PLCC (Q28) 4 3 2 1 28 27 26 25 TPINP 5 OPINN TPINN 6 24 QGND PHTM1 7 23 VDC PHTM2 8 22 KEYGEN GND2 OPOUT 15 16 17 VCC1 13 14 TOP VIEW 2 OPVCC 19 18 OPINOK 11 12 RTSETOP OPGND TPOUTN INSERTED GND1 20 RTSETTP 21 10 TPINOK 9 TPOUTP ML6680 PIN DESCRIPTION PIN# NAME FUNCTION 1, 28 XTAL1, XTAL2 Crystal inputs. A 32.768kHz watch crystal connected between these pins provides timing for the fiber optic insertion key signal. An external clock can be used to drive XTAL1 while grounding XTAL2. The frequency of the external clock should be between 32.7kHz and 34.5kHz. 2 3, 4 VCC2 7, 8 PHTM1/2 GND2 RTSETTP Twisted pair transmit level set resistor input. A precision resistor between RTSETTP and VCC sets the amplitude of the TPOUTP/N output. 14 VCC1 Positive 5V power supply. 15 INSERTED Insertion indicator. It is an active low, open collector LED driver. In configurations 1, 3 and 4 this output goes low when the ML6680 is in the “Insert State.” In configuration 2 this output goes low when the ML6680 is in the “Insert State” and no wire fault is detected. This input is tied to ground to disable the frequency squelch, and to reduce the time constant of the amplitude squelch of the optical input. 16 RTSETOP A precision resistor between RTSETOP and VCC sets the amplitude of the OPOUT output. Phantom drive/sense inputs/outputs. In configuration 1, these pins are TTL inputs from two external opto isolators. They are low when phantom power is present and high when phantom power is removed. These pins provide the phantom drive current and are used to check for a wire fault on the phantom circuits when it is required in configuration 2. In configuration 3, these pins are don’t cares. In configuration 4, these pins are low for normal operation, or any or both of them is high to force the ML6680 into the “Bypass State.” 17 OPINOK Valid fiber optic input signal indicator. It is an active low, open collector LED driver. This output goes low when the signal at OPINP/N meets frequency and amplitude squelch limit for received signals at TPINP/N. 18 OPVCC Positive 5V power supply for fiber optic LED driver. 19 OPOUT Fiber optic LED driver output. The fiber optic LED connects between this pin and OPVCC. 20 OPGND Ground for the fiber optic LED driver. 21 GND1 Ground. Ground. 22 KEYGEN Key generation select CMOS input. This input is low for configurations 2 and 3 of the general description, and is high for configurations 1 and 4. 23 VDC Offset correction time constant capacitor input. An external capacitor between this pin and QGND determines the time constant of the internal offset correction circuit for the fiber optic quantizer. 24 QGND Quantizer’s ground. Positive 5V power supply. Receive twisted pair inputs. This differential input pair receives differential Manchester signals from the coupling transformer (or PECL compatible levels). 10, 11 TPOUTP/N Transmit twisted pair outputs. This differential current output pair drives differential Manchester signals into the network coupling transformer and transmit filter. Output edge rates are controlled to allow use of a simpler filter than would otherwise be required. These outputs can be PECL compatible with an external resistor network. 12 TPINOK FUNCTION 13 EQA, EQB Equalizer network pins. An external combination of two resistors and a capacitor connected at EQA and EQB sets up the on-chip twisted pair receive equalizer. 5, 6 TPINP/N 9 PIN# NAME Valid twisted pair input signal indicator. It is an active low, open collector LED driver. This output goes low when the signal at TPINP/N meets frequency and amplitude squelch requirements. This input is tied to ground for configurations 3 and 4 to enable signal path switching. 26, 25 OPINP/N 27 QVCC Receive fiber inputs. This pair of inputs receive differential Manchester signals from the fiber optic receiver/preamp and present them to the on-chip fiber optic quantizer. These inputs should be capacitively coupled to the input source. The input resistance is approximately 1.3kΩ. Quantizer’s positive 5V power supply. 3 ML6680 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Power Supply Voltage, VCC ................................. 5V ± 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. Ambient Temperature,TA ................................ 0°C to 70°C Junction Temperature, TJ ....................................... 0°C to 125°C LED on Current ......................................................... 4mA RTSETOP ......................................................... 115Ω ± 1% RTSETTP ......................................................... 255Ω ± 1% Power Supply Voltage Range, VCC .................... –0.3 to 6V Input Voltage Range ........................................ –0.3 to VCC Output Current TPOUTP, TPOUTN .............................................. 50mA OPOUT ............................................................... 70mA PHTM1, PHTM2 .................................................. 10mA Input Current RTSETTP, RTSETOP, TPINOK, OPINOK, INSERTED ........................................... 20mA Storage Temperature ................................. –65°C to 150°C Lead Temperature (soldering, 10 sec.) ....................... 260° Thermal Resistance .............................................. 68°C/W ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified (Note 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 36 50 mA 160 mA 0.1 x VCC V POWER SUPPLY CURRENT ICC1 VCC Supply Current No transmitting, phantom power off 30 ICC2 VCC Supply Current RTSETTP = 255, RTSETOP = 115, transmitting, phantom power on (Note 2) 120 CMOS INPUTS PHTM1, PHTM2 (when KEYGEN = High or TPINOK is grounded) AND KEYGEN VILC Input Low Voltage VIHC Input High Voltage 0.9 x VCC V TTL INPUT: XTAL1 VILT Input Low Voltage 0.8 VIHT Input High Voltage IILT Input Low Current V(XTAL1) = 0V IIHT Input High Current V(XTAL1) = 2.7V RIX1 Input Resistance V 2 V –100 µA 400 100 µA 560 kΩ 0.1 V CONTROL INPUTS: INSERTED, TPINOK VILS Input Low Voltage IILS Input Low Current VIN = 0V µA –50 STATUS LED OUTPUTS: INSERTED, TPINOK, OPINOK IOLS Output Low Current IOHS Output Off Current 4 Pin connected to VCC 14 19 24 mA 3 10 µA ML6680 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 5.5 kΩ 50 Ω PHANTOM DRIVE OUTPUTS: PHTM1, PHTM2 RNF No Fault Phantom Load Resistance RSC Short Circuit Phantom Load Resistance ROC Open Circuit Phantom Load Resistance VOHP Phantom Output High Voltage 2.9 50 kΩ IOHP > –1mA 4.1 V IOHP > –2mA 3.5 V ISC Phantom Short Circuit Current V(PHTM1) or V(PHTM2) = 0V IOFFP Phantom Off Current V(PHTM1) or V(PHTM2) = 0V –1.8 –1.2 mA –100 100 µA TWISTED PAIR RECEIVER: TPINP, TPINN VOSRTP Differential Offset Voltage –35 35 mV VDSTP Differential Squelch Threshold 200 300 mVP-P VPSTP Differential Post-Squelch Threshold 100 150 mVP-P VCMTP Open-Circuit Common Mode Bias Voltage RIDRTP Differential Input Resistance 2.4 8 9.6 V 12.5 kΩ 29.5 mA 1.5 mA 300 µA TWISTED PAIR TRANSMITTER: TPOUTP, TPOUTN ITTP Peak Output Current IOFFTP Off State Output Current IDCI Differential Current Im Balance 27 RTSETTP = 255Ω, Pins Connected to VCC –300 OPTICAL RECEIVER: OPINP, OPINN VCMOP Open Circuit Common Mode Bias Voltage VIROP Input Signal Range VOSROP Differential Offset Voltage EN Input Referred Voltage Noise RIDROP Differential Input Resistance VDSOP Differential Squelch Threshold VPSOP Differential Post Squelch Threshold H Hysteresis 1.6 VDSOP 50MHz BW 1.8 V 1600 mVP-P 3 mV 25 µVRMS 2.6 3.3 kΩ 5 6 mVP-P 4 5 mVP-P 20 % OPTICAL TRANSMITTER: OPOUT ITOP Peak Output Current IOFFOP Off State Output Current RTSETOP = 115Ω 47 52 57 mA 1 mA 5 ML6680 AC CHARACTERISTICS Over full range of operating conditions unless otherwise specified. (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CLOCK REFERENCE: XTAL1 fXO Reference Clock Frequency 32.7 34.5 kHz DXO Reference Clock Duty Cycle 30 70 % 550 1000 ns 2 5 µs 550 1000 ns TWISTED PAIR RECEIVER: TPINP, TPINN tTHTP Input Pulse Width Threshold tUSQTP Time to Unsquelch (Off to On) tREJTP Time to Reject (On to Off) OPTICAL RECEIVER: OPINP, OPINN tTHOP Input Pulse Width Threshold V(INSERTED) > 0.7V 550 1000 ns tUSQOP Time to Unsquelch (Off to On) V(INSERTED) > 0.7V 3 9 µs 0.8 1.2 µs 3 9 µs 0.8 1.2 µs V(INSERTED) = 0V tREJOP Time to Reject (On to Off) V(INSERTED) > 0.7V V(INSERTED) = 0V PROPAGATION DELAYS STEADY STATE tTPOP TPINP-TPINN to OPOUT 20 ns tOPTP OPINP-OPINN to TPOUTP-TPOUTN 30 ns tTPTP TPINP-TPINN to TPOUTP-TPOUTN 30 ns tOPOP OPINP-OPINN to OPOUT 20 ns INSERTION AND BYPASS KEY GENERATION (Fig. 1) T_K1 Key Element #1 (avg. PO < PO_Off) 808 858 µs T_K2 Key Element #2 (avg. PO > PO_Off) 1616 1717 µs T_K3 Key Element #3 (avg. PO < PO_Off) 1616 T_BYP Bypass Element (avg. PO > PO_Off) 4.85 T_KINIT1 Time that phantom power should be applied in config 1 before generating the insertion key. T_KINIT4 T_KOFF 6 µs 26.5 ms V(KEYGEN) = VCC, V(TPINOK) > 0.7V 26.5 ms Time that the optical input should be valid in config 4 before generating the insertion key. V(KEYGEN) = VCC, V(TPINOK) = 0V V(PHTM1) = 0V, V(PHTM2) = 0V 26.5 ms Time that the optical input should be invalid before generating the bypass key. V(KEYGEN) = VCC, V(TPINOK) = 0V V(PHTM1) = 0V, V(PHTM2) = 0V 26.5 ms ML6680 AC CHARACTERISTICS (continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 100 ms INSERTION KEY ECHO AND BYPASS KEY RECOGNITION (Fig. 1) T_ECHO Time since starting insertion key generation until receiving the insertion key echo. T_E1Key Key Echo From T_K1 766 900 µs T_E2Key Key Echo From T_K2 1533 1800 µs T_E3Key Key Echo From T_K3 1533 T_BYPDET Time of optical input not valid before recognizing a bypass key Note 1: Note 2: µs 4 4.5 ms Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Current into all VCC pins, external bias resistors, and external transmit loads. Does not include status LED’s current. GENERATED INSERTION KEY T_K1 T_K2 T_K1 T_K3 RECEIVED INSERTION KEY ECHO T_ECHO T_E1 T_E2 T_E1 T_E3 GENERATED BYPASS KEY T_BYP RECEIVED BYPASS KEY INSERTED T_BYPDET Figure 1 7 ML6680 FUNCTIONAL DESCRIPTION Copper Pair Driver Fiber Optic LED Driver The output stage of the transmitter is a current mode switch which develops the output light by sinking current from OPVCC through the LED into the OPOUT pin. Once the current requirement for the LED is determined, the RTSETOP resistor is selected. The following equation is used to select the correct RTSETOP resistor: RTSETOP = (52mA/IOUT) × 115Ω No current is provided during the off cycles of the Insertion, Bypass, or Echo Keys, or when the input signal that should be routed to the Fiber Optic LED Driver does not meet the corresponding input squelch requirements. Fiber Optic Quantizer The OPINP, OPINN input signal is fed into a limiting amplifier with a gain of about 100 and input resistance of 1.3kΩ. Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC bias voltage is set by an on-chip network at about 1.7V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3dB corner frequency, fL, at fL = 1/(2 × π × 1300 × C) Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to VCC. The internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal to noise ratio. Although the input is AC coupled, the offset voltage, VOS, within the amplifier will be present at the amplifier’s output. In order to reduce this error a DC feedback loop nulls the offset voltage, forcing VOS to be zero. The comparator is a high-speed differential zero crossing detector that slices and accurately digitizes the receive signal. The output of the comparator is fed in parallel into both the fiber optic squelch circuit and the signal MUX. The capacitor between pin VDC and QGND should be set to 500pF. Fiber Optic Squelch The ML6680 monitors the frequency and amplitude of the input from a fiberoptic receiver. The optical squelch circuit rejects signals whose frequencies are lower than 1MHz or whose amplitudes are lower than –32dBm. If both requirements are met, the LED output OPINOK goes low, and the amplitude threshold is lowered 20%. FREQUENCY OK AMPLITUDE OK SET RESET Q OPINOK The output stage of the twisted pair transmitter is a current mode switch which develops the output voltage by driving current through the terminating resistor and the output filter. The harmonic content is controlled to simplify the filter design. The transmitter employs a center tap 2:1 transformer where the center tap is tied to VCC. While one pin of the transmit pair is pulled low, the other pin floats. The output pins to the twisted pair wires, TPOUTP and TPOUTN, can drive shielded or unshielded twisted pair cable through the appropriate isolation transformer. The output current is set by the value of RTSETTP. No transitions are generated at TPOUTP and TPOUTN when the input signal that should be routed to the Copper Pair Driver does not meet the corresponding input squelch requirements. PECL compatible output are obtained with an external network of 3 resistors. In this case the current of the output stage can be reduced by adjusting the value of RTSETTP. Twisted Pair Line Equalizer The receive equalizer compensates for twisted pair cable dispersion, which otherwise would give rise to inter-symbol interference (ISI). The amount of equalization varies with the average amplitude of the received signal. The received signal amplitude gives a rough value for the length of the attached cable. The filter/equalizer characteristic is the inverse of the cable’s dispersion characteristic. Both UTP and STP cables approximate a low-pass filter, so the filter/ equalizer approximates an inverse square root equalizer. Two external resistors and one external capacitors are required between pins EQA and EQB. The output of the equalizer is fed into the signal MUX. On a PECL application these pins should be connected between each other. Twisted Pair Squelch Circuit The twisted pair line receiver internally sets the common mode bias of the input TPINP and TPINN. Voltage offset comparators are used to set the amplitude squelch threshold, and analog timers are used to set the pulse width squelch threshold. When the input signal meets amplitude and pulse width requirements, the squelch circuit reduces the offset voltage of the comparators, decreasing the amplitude squelch threshold by half. This hysteresis allows the receiver to stay on in the presence of a fading input signal. The twisted pair squelch circuit rejects signals whose frequencies are lower than 1MHz or whose amplitudes are lower than 300mVP-P. If both requirements are met, the LED output TPINOK goes low. Clock Oscillator The ML6680 provides an on-chip clock oscillator by connecting a 32.768kHz watch crystal between pins XTAL1 and XTAL2. The part can also be driven by an external clock applied at XTAL1 and tying XTAL2 to ground. The frequency of the external clock should be between 32.7kHz and 34.5kHz. Status LED Drivers The ML6680 has three status LED drivers. The LED driver pins are active low. The LED’s are tied to their respective pins through a 300Ω resistor to VCC. 8 ML6680 Modes of Operation CONFIGURATION 3 Four configurations are possible with the ML6680, as follows: Lobe or Ring Out Port Media Converter: 1.Standard Media Converter: Senses ISO/IEC8802-5 phantom power and generates ISO/IEC8802-5 fiberoptic insertion or bypass requests. 2.Concentrator Media Converter: Recognizes the ISO/ IEC8802-5 fiberoptic insertion or bypass requests and drives the ISO/IEC8802-5 phantom circuits. 3.Lobe or Ring Out Port Media Converter: Recognizes the ISO/IEC8802-5 fiberoptic insertion or bypass requests. 4.Ring In Port Media Converter: Generates ISO/ IEC8802-5 fiberoptic insertion or bypass requests. Modifies the internal signal paths depending on the presence or absence of a fiberoptic link, and on the reception of the ISO/IEC8802-5 “Insertion Key Echo.” CONFIGURATION 1 This configuration is selected by tying both KEYGEN and TPINOK to ground. When the ML6680 is in the “Insert State,” the signal paths are from TPINP and TPINN to OPVCC and OPOUT, and from OPINP and OPINN to TPOUTP and TPOUTN. Otherwise, the signal paths are from TPINP and TPINN to TPOUTP and TPOUTN, and from OPINP and OPINN to OPVCC and OPOUT. The part powers on in the “Bypass State” and goes to the “Insert State” after recognizing an “Insertion Key” at its fiber optic inputs. It goes back to the “Bypass State” after recognizing a “Bypass Key.” While it is at the “Insert State,” the LED output INSERTED stays low. CONFIGURATION 4 Ring In Port Media Converter: This configuration is selected by tying KEYGEN to VCC. There are always two fixed signal paths, one from TPINP and TPINN to OPVCC and OPOUT, and another from OPINP and OPINN to TPOUTP and TPOUTN. The generation of the “Insertion Key” or “Bypass Key” is exclusively controlled by the logic values at PHTM1 and PHTM2. The “Insertion Key” is generated when both PHTM1 and PHTM2 go low, and stay low for at least 26.5ms. If the “Insertion Key Echo” is received within the following 100ms, the part goes to the “Insert State” and the LED output INSERTED goes low. During the generation of the “Insertion Key,” and while waiting for the “Insertion Key Echo” the states of PHTM1 and PHTM2 do not have any effect. When the part is in the “Insert State” and either PHTM1 or PHTM2 goes high, the LED output INSERTED goes high, the part leaves the “Insert State,” generates the “Bypass Key,” and starts waiting for PHTM1 and PHTM2 to go low again. This configuration is selected by tying KEYGEN to VCC and TPINOK to ground. When the part is in the “Insert State,” the signal paths are from TPINP and TPINN to OPVCC and OPOUT, and from OPINP and OPINN to TPOUTP and TPOUTN. Otherwise, the input at TPINP and TPINN is routed to TPOUTP and TPOUTN, and also to OPVCC and OPOUT. The “Insertion Key” is generated when activity is detected at OPINP and OPINN for at least 26.5ms and, PHTM1 and PHTM2 stay low. If the “Insertion Key Echo” is received within the following 100ms, the ML6680 goes to the “Insert State” and the LED output INSERTED goes low. During the generation of the “Insertion Key,” and while waiting for the “Insertion Key Echo” the logic states of PHTM1 and PHTM2 do not have any effect. When the part is in the “Insert State” and no activity is detected at OPINP and OPINN for at least 26.5ms, or either PHTM1 or PHTM2 goes high, the LED output INSERTED goes high, the part leaves the “Insert State,” generates the “Bypass Key,” and starts waiting for 26.5ms of optical input activity again. CONFIGURATION 2 Low Frequency Signaling Mode Standard Media Converter: Concentrator Media Converter: This configuration is selected by tying KEYGEN to ground. There are always two fixed signal paths, one from TPINP and TPINN to OPVCC and OPOUT, and another from OPINP and OPINN to TPOUTP and TPOUTN. The part powers on in the “Bypass State” where it neither applies phantom current nor checks for a phantom wire fault. After recognizing an “Insertion Key” at its fiber optic inputs, it applies phantom power by providing current at PHTM1 and PHTM2, goes to the “Phantom Wire Fault Check State,” and starts waiting for a “Bypass Key.” At this state, the LED output INSERTED stays low while no phantom wire fault is detected. When the part is in the “Phantom Wire Fault Check State” and a “Bypass Key” is recognized, the part leaves this state, removes the phantom power, and starts waiting for a “Insertion Key” again. Some old implementations of discrete media converters, use a non-standard protocol with frequencies between 1 and 10kHz. To facilitate the migration to the ML6680, a specific operating mode is provided by grounding the pin INSERTED. Pin KEYGEN should also be grounded to prevent the generation of unwanted “Insertion” or “Bypass Keys.” In this operating mode, the optical frequency squelch circuitry is disabled and the time constant of the amplitude squelch is significantly reduced. For each edge of the low frequency optical input, the ML6680 generates a pulse at the led output OPINOK. It also generates a pulse at the TPOUTP output for each rising edge and another at the TPOUTN output for each falling edge. 9 4 5 6 4 5 6 9 8 Figure 2. ML6680 Configurations 1 and 2 4 5 6 4 5 6 6 5 4 RJ45 6 5 4 3 3 0.1µF C15 11 6 12 4 13 T1 5 15 2 47µF 16 1 C19 J5 14 3 7 6 5 2.7KΩ 2 3 4 OC1 8 1 R16 FGND C20 0.1µF CONCENTRATOR MEDIA CONVERTER CONFIGURATION 2: CONNECT J4 AND J5, AND CONNECT J1 TO FGND. REMOVE OC1, OC2, R16, R17, R18 AND R19 SHORT THE LOCATIONS OF PINS 2 AND 6 OF OC1 SHORT THE LOCATIONS OF PINS 2 AND 6 OF OC2 STANDARD MEDIA CONVERTER CONFIGURATION 1: REMOVE J4 AND J5 AND CONNECT J1 TO FVCC CONFIGURATION ADJUSTMENTS: RJ45 3 3 7 10 CONFIG. 2 PHANTOM DRIVE U2 RJ45 3 3 CONFIG. 1 PHANTOM SENSE C16 0.1µF 4.7µH R12 J4 L2 C18 C17 237Ω R20 500Ω 0.1µF R11 237Ω 47µF 4 OC2 5 6 7 2.7KΩ 2 3 8 1 R18 0.1µF C8 5 PHTM1 TPINN TPINP D3 12 TPOUTN TPOUTP R10 300Ω C7 0.1µF 11 10 14 J2 D2 R1 255Ω R6 300Ω 13 X2 28 15 17 R2 115Ω R5 300Ω D1 16 ML6680 U1 1 2 50pF 3 C13 50pF C12 4 10Ω R15 R17 8 PHTM2 4.7KΩ 9 GND2 7 R13 118Ω 6 R19 4.7KΩ 698Ω 220pF C14 R14 EQB TPINOK D4 EQA RTSETTP FVCC 18 27 XTAL2 RTSETOP L1 VCC2 VCC1 32KHz QVCC OPINOK 4.7µH XTAL1 INSERTED OPOUT OPGND GND1 KEYGEN VDC QGND OPINN 26 OPINP 10 OPVCC VCC +5V J1 C1 500pF U3 R3 1KΩ 4 3 U4 5 6 0.1µF C5 1414 1 8 0.1µF 2 7 C21 1nF C2 4 3 2 2416 5 6 7 8 U1: ML6680 U2: RJ45 CONNECTOR U3: HFBR2416 (HP) OR OP2416 (OPTEK) OPTICAL RECEIVER U4: HFBR1414 (HP) OR OP1414(OPTEK) OPTICAL TRANSMITTER OC1: MOTOROLA MOC217 X2: 32.768KHz CRYSTAL OSCILLATOR T1: TRANSFORMER MODULE, VALOR SF1304 OR BEL S553–2793–03 D1-4: LED, SURFACE MOUNT, PANASONIC LN146IC-(TR) 0.1µF C6 19 20 21 22 23 24 25 10Ω R4 C4 0.1µF 1nF C3 1 ML6680 ML6680 VCC +5V FVCC 4.7µH L1 D4 R20 500Ω 47µF 0.1µF C17 C18 47µF 0.1µF C19 HFBR 2416 C20 L2 4.7µH CLOCK 9 COUTP 10 COUTN 11 OPINP QVCC OPINN QGND PHTM1 VDC ML6680 U1 PHTM2 GND2 KEYGEN GND1 TPOUTP OPGND TPOUTN OPOUT 12 13 14 15 16 2 7 0.1µF C4 3 6 4 5 17 25 R4 1nF C2 24 500pF C1 23 22 21 20 19 J1 0.1µF C21 0.1µF 1 HFBR 8 C5 2 7 R3 1KΩ 3 6 4 5 U4 18 J2 0.1µF C7 XTAL2 XTAL1 TPINN TPINOK TO THE DOWNSTREAM LOBE PORT IN CONFIG. 4 TO THE DOWNSTREAM RING IN PORT IN CONFIG. 3 R8 49.9Ω 1nF C3 10Ω 26 OPVCC 8 R7 49.9Ω 27 OPINOK 7 8 U3 NC 28 RTSETOP 6 1 INSERTED 25nF C10 TPINP 2 VCC1 CINN 5 3 RTSETTP 25nF C9 CINP 4 VCC2 C8 EQA 0.1µF EQB FROM THE UPSTREAM RING OUT PORT IN CONFIG. 4 FROM THE UPSTREAM LOBE PORT IN CONFIG. 3 FGND 1 R1 499Ω R2 115Ω D2 0.1µF C6 D1 CONFIGURATION 3: LOBE OR RING OUT PORT, J1 TO FGND CONFIGURATION 4: RING IN PORT, J1 TO FVCC R6 300Ω R5 300Ω U1: ML6680 U3: HFBR2416 (HP) OR OP2416 (OPTEK) OPTICAL RECEIVER U4: HFBR1414 (HP) OR OP1414 (OPTEK) OPTICAL TRANSMITTERS D1, 2, 4: LED, SURFACE MOUNT, PANASONIC LN146IC (TR) Figure 3. ML6680 Configurations 3 and 4 11 ML6680 PHYSICAL DIMENSIONS inches (millimeters) Package: Q28 28-Pin PLCC 0.485 - 0.495 (12.32 - 12.57) 0.042 - 0.056 (1.07 - 1.42) 0.450 - 0.456 (11.43 - 11.58) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 0.042 - 0.048 (1.07 - 1.22) PIN 1 ID 8 22 0.300 BSC (7.62 BSC) 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.390 - 0.430 (9.90 - 10.92) 15 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.099 - 0.110 (2.51 - 2.79) SEATING PLANE ORDERING INFORMATION PART NUMBER ML6680CQ TEMPERATURE RANGE 0°C to 70°C PACKAGE 28-PIN PLCC (Q28) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS6680-01