We make the parts that set creative people free Features General Description The AL1401A OptoGen interface is designed to accept four stereo pairs of audio data and produce the data stream appropriate for the Alesis ADATâ optical format, U.S. patent number 5,297,181. Use of this product requires a license agreement between manufacturer and Alesis Studio Electronics. Details and agreement information are available upon request from Alesis Semiconductor or Alesis Studio Electronics. G G G G Compatible with ADATâ Type I and II formats 4 stereo pairs as inputs using standard DAC formats 4 user bit inputs to transmit timecode, MIDI data, etc. Internal PLL generates required clocks from Word Clock. Applications G Transmit information compatible devices GND N/C N/C WDCLK RESET WDCLKNEG FMT0 FMT1 FMT2 FMT3 to VDD OPDIGOUT USER3 USER2 USER1 USER0 IN 7/8 IN 5/6 IN 3/4 IN 1/2 Figure A. 24 pin SOIC Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 ADATâ Table 1. Electrical Characteristics and Operating Conditions Symbol Description Min Typ Max Units Electrical Characteristics and Operating Conditions VDD IDD GND Fs Temp Supply Voltage Supply Current Ground Sample rate Temperature 4.5 30 0 5.0 1.5 0.0 48 25 5.5 55 70 V mA V kHz °C 0.9 VDD - - VDD - - 0.1 VDD VDD - - -8 mA - - 8 mA Outputs (OPDIGOUT) Logical “1” voltage Logical “0” voltage Logical “1” current Logical “0” current VOH VOL IOH IOL output output output output Inputs (WDCLK, WDCLKNEG, FMT, IN, USER, RESET) Logical “1” input voltage Logical “0” input voltage Logical “1” input current Logical “0” input current Logic Input Capacitance VIH VIL IIH IIL CIN 0.75 VDD - - VDD - - 0.25 VDD VDD - - 1 uA - - 1 uA - 5 - pF Table 2. Pin Descriptions Pin # Name Pin Type Description Ground pin 1 GND Power 2 N/C - No connection 3 N/C - No connection 4 WDCLK Input Word clock. Equal to sample frequency (Fs) 5 RESET Input Active low reset 6 WDCLKNEG Input Sets phase of word clock 7 FMT0 Input Format0, Sets data format 8 FMT1 Input Format1. Sets data format 9 FMT2 Input Format2. Sets data format 10 FMT3 Input Format3. Sets data format 11 IN 1/2 Input Channels 1 and 2 data input 12 IN 3/4 Input Channels 3 and 4 data input 13 IN 5/6 Input Channels 5 and 6 data input 14 IN 7/8 Input Channels 7 and 8 data input 15 USER0 Input User 0 data bit input. Used to transmit timecode. 16 USER1 Input User 1 data bit input. Used to transmit MIDI data. 17 USER2 Input User 2 data bit input. Reserved, tie low. 18 USER3 Input User 3 data bit input. Reserved, tie low. 19 OPDIGOUT 20 VDD Output Power Output to optical driver +5V power pin Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -2- Table 3. Formats Format0 Format1 Format2 Format3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Mode 16-bit right justified 18-bit right justified 20-bit right justified 22-bit right justified 16-bit left justified 18-bit left justified 20-bit left justified 22-bit left justified Reserved Reserved Reserved Reserved 24-bit right justified 24-bit left justified Reserved Mute one period WordClock, WordNeg Low WordClock Right Just 16 15 MSB Right Just 18 17 MSB Right Just 20 19 MSB Right Just 22 15 MSB Left Just 18 17 MSB Left Just 20 19 MSB Left Just 22 21 MSB Right Just 24 23 MSB 19 MSB 15 MSB 0 17 MSB 0 0 19 MSB 0 0 0 0 0 0 Figure B. Format Timing Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -3- 0 0 23 MSB 23 MSB 0 0 21 MSB 0 0 0 21 MSB 0 23 MSB Left Just 24 17 MSB 0 0 21 MSB Left Just 16 15 MSB 0 Figure C/Table 4. Input Timing Symbol Description Setup of IN relative to center of bit period tSI Hold of IN relative to center of bit period tHI Setup of USER relative to end of right channel WDCLK time tSU Hold of USER relative to end of right channel WDCLK time tHU (Above specifications hold after 2000 WDCLK cycles) Min - Typ 10 Max 30 Units nsec - 10 30 nsec - 100 - nsec - 100 nsec Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -4- Use The AL1401A OptoGen interface has been designed for ease of use and flexibility in systems designed to interface to the ADAT protocol. It supports both left and right justified 16, 18, 20, 22 and 24-bit data formats for ease of integration into existing devices as well as new devices. These formats allow it to operate in parallel with many standard DACs. edge of WDCLK signals the start of a new sample period. In both cases, the first sample data sent is the odd numbered (left) channel. The second is the even numbered (right) channel. The format pins are summarized in Table 3. The AL1401A provides support for both the ADAT Type I format (16-bit) and the ADAT Type II format (20-bit). â â â USER0 is used to transmit the ADAT format 32-bit timecode. USER1 is used to transmit MIDI data. USER2 and USER3 are reserved and should be tied low. User bits are sampled at the WDCLK edge that indicates the end of right channel data. The designer uses the WDCLKNEG, Format0, Format1, Format2 and Format3 pins to select the desired format. If WDCLKNEG is high, the falling edge of WDCLK signals the start of a new sample period. If low, the rising Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -5- Mechanical Specification Table 5. Package Dimensions Dimensions (Typical) Inches Millimeters A B C D E F G H J K L A C 20 11 1 10 B .504” .295” .406” .100” .008” .025” .050” .017” .011” .352” .033” 12.80 7.50 10.30 2.50 0.20 0.64 1.27 0.42 0.27 8.94 0.83 Notes: 1) Dimension “A” does not include mold flash, protrusions or gate burrs. 7° nom K 4° nom D H E J L G F Figure D. Mechanical Drawing Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -6- Sample Application Schematic +5V 0.1uF 5 NC INPUT VCC C_LIMIT GND NC +5V 4 3 2 1 OPTOGEN 19 TOTX173* 6 OPTICAL OUT 4 WDCLK WDCLK 5 RESET 0.1uF 20 VDD OPDGOUT 8.2k OUTPUT VCC GND1 GND2 NC 2 NC 3 +5V 15 16 17 18 7 8 9 10 NC NC GND 1 3 MIDI DATA +5V 1 2 4 +5V 0.1uF TORX173* 1/2 3/4 5/6 7/8 TIME CODE WDCLKNEG +5V 47uH USER0 USER1 USER2 USER3 FMT0 FMT1 FMT2 FMT3 IN IN IN IN RESET 6 5 IN 1/2 IN 3/4 IN 5/6 IN 7/8 11 12 13 14 0.1uF 6 OPTOREC 6 3 4 OPTICAL IN ERROR 24 VDD OPDIGTHRU OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 OPDIGIN FMT0 FMT1 21 20 ERROR HOLDERR 23 2 5 22 LINMODE MODE0 MODE1 MUTE GND USER0 USER1 USER2 USER3 DVCO SVCO WDCLK BCLK 19 10 11 12 13 14 15 16 17 18 7 8 9 OPDIGTHRU OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 TIME CODE NC NC MIDI DATA DVCO SVCO 1 (Master Mode, can be MCLK) WDCLK (Slave Mode) WDCLK (Master Mode) BCLK (Master Mode) * Optical I/O parts shown are Toshiba parts. The Sharp GP1F33RT or equivalent is also compatible. LEFTIN LEFTOUT RIGHTIN INL/R WDCLK BCLK MCLK RIGHTOUT OUTL/R WDCLK BCLK MCLK ADC DAC Figure E. OptoGen/OptoRec setup The OptoGen accepts input from an ADC, then outputs the Alesis optical format. The OptoRec accepts input in Alesis optical format, then outputs to a DAC. Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -7- NOTICE Alesis Semiconductor reserves the right to make changes to their products or to discontinue any product or service without notice. All products are sold subject to terms and conditions of sale supplied at the time of order acknowledgement. Alesis Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Information contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, no responsibility is assumed for inaccuracies. Alesis Semiconductor products are not designed for use in applications which involve potential risks of death, personal injury, or severe property or environmental damage or life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. All trademarks and registered trademarks are property of their respective owners. Contact Information: Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone: (310) 301-0780 Fax: (310) 306-1551 Email: [email protected] Copyright 2002 Alesis Semiconductor Datasheet July 2002 Reproduction, in part or in whole, without the prior written consent of Alesis Semiconductor is prohibited. Alesis Semiconductor 12555 Jefferson Blvd., Suite285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1401A-0702 -8-