LC2MOS
12-Bit, 3.3 V Sampling ADC
AD7883
a
FEATURES
Battery-Compatible Supply Voltage: Guaranteed Specs
for VDD of 3 V to 3.6 V
12-Bit Monolithic A/D Converter
50 kHz Throughput Rate
15 ms Conversion Time
5 ms On-Chip Track/Hold Amplifier
Low Power
Power Save Mode: 1 mW typ
Normal Operation: 8 mW typ
70 dB SNR
Small 24-Lead SOIC and 0.3" DIP Packages
APPLICATIONS
Battery Powered Portable Systems
Laptop Computers
FUNCTIONAL BLOCK DIAGRAM
V DD
SAMPLING
COMPARATOR
V INA
+
V INB
Fast bus access times and standard control inputs ensure easy
interfacing to modern microprocessors and digital signal
processors.
MODE
–
V REF
12-BIT DAC
AGND
CS
SAR +
COUNTER
CLKIN
CONVST
CONTROL
LOGIC
RD
BUSY
THREE
STATE
BUFFERS
DB11
GENERAL DESCRIPTION
The AD7883 is a high speed, low power, 12-bit A/D converter
which operates from a single +3 V to +3.6 V supply. It consists
of a 5 µs track/hold amplifier, a 15 µs successive-approximation
ADC, versatile interface logic and a multiple-input-range circuit.
The part also includes a power save feature.
LOW POWER
CONTROL
CIRCUIT
DB0
AD7883
DGND
PRODUCT HIGHLIGHTS
1. 3 V Operation
The AD7883 is guaranteed and tested with a supply voltage
of 3 V to 3.6 V. This makes it ideal for battery-powered applications where 12-bit A/D conversion is required.
The AD7883 features a total throughput time of 20 µs and can
convert full power signals up to 25 kHz with a sampling frequency of 50 kHz.
2. Fast Conversion Time
15 µs conversion time and 5 µs acquisition time allow for
large input signal bandwidth. This performance is ideally
suited for applications in areas such as telecommunications,
audio, sonar and radar signal processing.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7883 is also fully
specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio.
3. Low Power Consumption
1 mW power consumption in the power-down mode makes
the part ideally suited for portable, hand held, battery powered applications.
The AD7883 is fabricated in Analog Devices’ Linear Compatible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The part is available in a 24-pin, 0.3 inch-wide, plastic
dual-in-line package (DIP) as well as a small 24-lead SOIC
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7883–SPECIFICATIONS
(VDD = +3 V to +3.6 V, VREF = VDD, AGND = DGND = 0 V, f CLKIN = 2 MHz,
MODE = Logic High. All specifications TMIN to TMAX unless othewise noted.)
Parameter
B Versions 1
Units
Test Conditions/Comments
69
dB min
–80
–80
dB typ
dB typ
Typically SNR Is 71 dB
VIN = 1 kHz Sine Wave, fSAMPLE = 50 kHz
VIN = 1 kHz Sine Wave, fSAMPLE = 50 kHz
VIN = 1 kHz, fSAMPLE = 50 kHz
–80
–80
dB typ
dB typ
fa = 0.983 kHz, fb = 1.05 kHz, f SAMPLE = 50 kHz
fa = 0.983 kHz, fb = 1.05 kHz, f SAMPLE = 50 kHz
12
Bits
±2
±1
± 20
± 12
±3
All DC ACCURACY Specifications Apply for the Two
Analog Input Ranges
LSB max
LSB max
LSB max
LSB max
LSB max
0 to VREF
± VREF
10
5/12
Volts
Volts
MΩ min
kΩ min/max
VDD
1.2
V
mA max
2.1
0.6
± 10
10
V min
V max
µA max
pF max
VDD –0.2
0.2
± 100
10
V
V
µA max
pF max
2.4
0.4
V min
V max
± 10
10
µA max
pF max
15
5
µs max
µs max
fCLKIN = 2 MHz
+3.3
V nom
+3 V to +3.6 V for Specified Performance
3
4
400
800
mA max
mA max
µA max
µA max
Typically 2 mA; MODE = VDD
Typically 2.5 mA; MODE = V DD
Logic Inputs @ 0 V or VDD; MODE = 0 V; Typically 250 µA
Logic Inputs @ 0 V or VDD; MODE = 0 V; Typically 300 µA
11
15
1.5
3
mW max
mW max
mW max
mW max
VDD = 3.6 V: Typically 8 mW; MODE = VDD
VDD = 3.6 V: Typically 9 mW; MODE = VDD
VDD = 3.6 V: Typically 1 mW; MODE = 0 V
VDD = 3.6 V: Typically 1 mW; MODE = 0 V
2
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio3 (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Full-Scale Error
Bipolar Zero Error
Unipolar Offset Error
ANALOG INPUT
Input Voltage Ranges
Input Resistance
REFERENCE INPUT
VREF (For Specified Performance)
IREF
LOGIC INPUTS
CONVST, RD, CS, CLKIN
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, I IN
Input Capacitance, C IN4
MODE INPUT
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, I IN
Input Capacitance, C IN4
LOGIC OUTPUTS
DB11–DB0, BUSY
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
Floating-State Leakage Current
Floating-State Output Capacitance4
CONVERSION
Conversion Time
Track/Hold Acquisition Time
POWER REQUIREMENTS
VDD
IDD
Normal Power Mode @ +25°C
TMIN to TMAX
Power Save Mode @ +25°C
TMIN to TMAX
Power Dissipation
Normal Power Mode @ +25°C
TMIN to TMAX
Power Save Mode @ +25°C
TMIN to TMAX
Guaranteed Monotonic
See Figure 4
See Figure 5
0 to VREF Range
8 kΩ typical: ± VREF Range
VIN = 0 V or VDD
VIN = 0 V or VDD
ISOURCE = 200 µA
ISINK = 0.8 mA
NOTES
1
Temperature range is as follows: B Versions, –40°C to +85°C.
2
VIN = 0 to VREF.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. 0
AD7883
TIMING CHARACTERISTICS1 (V
Parameter
t1
t2
t3
t4
t5
t6
t7 2
t8 3
SS
= +3 V to +3.6 V, VREF = VDD, AGND = DGND = 0 V)
Limit at +258C
(All Versions)
Limit at TMIN, T MAX
(All Versions)
Units
Conditions/Comments
50
200
0
0
0
110
100
5
90
60
200
0
0
0
150
140
5
90
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
CONVST Pulse Width
CONVST to BUSY Falling Edge
BUSY to CS Setup Time
CS to RD Setup Time
CS to RD Hold Time
RD Pulse Width
Data Access Time after RD
Bus Relinquish Time after RD
NOTES
1
Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
t1
0.8mA
CONVST
t2
TRACK/HOLD
GOES INTO HOLD
tCONVERT
TO
OUTPUT
PIN
BUSY
+1.6V
50pF
t3
CS
200µA
t5
t4
t6
Figure 2. Load Circuit for Access and Relinquish Time
RD
t7
DB0 – DB11
THREE-STATE
Figure 1. Timing Diagram
t8
DATA
VALID
Table I. Truth Table
CS
CONVT
RD
Function
1
1
0
0
1
j
1
1
X
1
0
1
Not Selected
Start Conversion g
Enable ADC Data
Data Bus Three Stated
ORDERING GUIDE
Model
Temperature Range
AD7883BN
AD7883BR
–40°C to +85°C
–40°C to +85°C
Package Option*
N-24
R-24
*N = Plastic DIP; R = SOIC (Small Outline Integrated Circuit).
REV. 0
–3–
AD7883
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VINA, VINB to AGND (Figure 4) . . . . . –0.3 V to VDD + 0.3 V
VINA to AGND (Figure 5) . . . . . . –VDD –0.3 V to V DD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VINA
1
24
VINB
2
23
MODE
AGND
3
22
DB11
VREF
4
21
DB10
CS
5
AD7883
20
DB9
CONVST
6
TOP VIEW
19
DB8
RD
7
18
DB7
(Not to Scale)
VDD
BUSY
8
17
DB6
CLKIN
9
16
DB5
DGND
10
15
DB4
DB0
11
14
DB3
DB1
12
13
DB2
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7883 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTION
Pin
No.
Pin
Mnemonic
11
12
13
14
15
16
VINA
VINB
AGND
VREF
CS
CONVST
17
18
19
RD
BUSY
CLKIN
10
DGND
11 . . . 22 DB0–DB11
23
MODE
24
VDD
Function
Analog Input.
Analog Input.
Analog Ground.
Voltage Reference Input. This is normally tied to VDD.
Chip Select. Active Low Logic input. The device is selected when this input is active.
Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts
conversion. This input is asynchronous to the CLKIN and is independent of CS and RD.
Read. Active Low Logic Input. This input is used in conjunction with CS low to enable data outputs.
Active Low Logic Output. This status line indicates converter status. BUSY is low during conversion.
Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark/
space ratio of the clock can vary from 40/60 to 60/40.
Digital Ground.
Three-State Data Outputs. These become active when CS and RD are brought low.
MODE Input. This input is used to put the device into the power save mode (MODE = 0 V). During
normal operation, the MODE input will be a logic high (MODE = VDD).
Power Supply. This is nominally +3.3 V.
–4–
REV. 0
AD7883
CIRCUIT INFORMATION
The AD7883 is a single supply 12-bit A/D converter. The part
requires no external components apart from a 2 MHz external
clock and power supply decoupling capacitors. It contains a
12-bit successive approximation ADC based on a fast-settling
voltage output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7883 provides the user with an inherent trackand-hold function. The ADC is specified to work with sampling
rates up to 50 kHz.
CONVERTER DETAILS
The AD7883 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. The rising edge of the CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified conversion time is 15 µs. During conversion the BUSY output will
remain low, and the output databus drivers will be three-stated.
When a conversion is completed, the BUSY output will go to a
high level, and the result of the conversion can be read by bringing CS and RD low.
The AD7883 accommodates two separate input ranges, 0 to
VREF and ± VREF. The input configurations corresponding to
these ranges are shown in Figures 4 and 5.
With VREF = VDD and using a nominal VDD of +3.3 V, the input
ranges are 0 V to 3.3 V and ± 3.3 V, as shown in Table II.
Table II. Analog Input Ranges
Analog Input
Range
VREF
Input Connections
VINA
VINB
Connection
Diagram
0 V to +3.3 V
± 3.3 V
VDD
VDD
VIN
VIN
Figure 4
Figure 5
VIN
VREF
SAMPLING
COMPARATOR
R
VIN = 0 TO VREF
0 TO VREF
VINA
+
R
–
VINB
VREF
VREF
12-BIT DAC
AGND
The track/hold amplifier acquires a 12-bit input signal in 5 µs.
The overall throughput time for the AD7883 is equal to the conversion time plus the track/hold acquisition time. For a 2 MHz
input clock the throughput time is 20 µs.
Figure 4. 0 to VREF Unipolar Input Configuration
REFERENCE INPUT
For specified performance, it is recommended that the reference
input be tied to VDD . The part, however, will operate with a
reference down to 2.5 V though with reduced performance
specifications.
+
R
–
VREF
VINB
VREF
ANALOG INPUT
12-BIT DAC
AGND
The AD7883 has two analog input pins, VINA and VINB. Figure
3 shows the input circuitry to the ADC sampling comparator.
The onboard attenuator network, made up of equal resistors, allows for various input ranges.
Figure 5. ±VREF Bipolar Input Configuration
R
VINA
+
R
–
VDAC
Figure 3. AD7883 Input Circuit
REV. 0
0 TO VREF
VINA
VREF must not be allowed to go above VDD by more than 100 mV.
VINB
SAMPLING
COMPARATOR
R
VIN = ±VREF
–5–
AD7883
CLOCK INPUT
The AD7883 has one unipolar input range, 0 V to VREF. Figure
4 shows the analog input for this range. The designed code
transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The
output code is straight binary with 1 LSB = FS/4096 = 3.3 V/
4096 = 0.8 mV when VREF = 3.3 V. The ideal input/output
transfer characteristic for the unipolar range is shown in Figure 6.
The AD7883 is specified to operate with a 2 MHz clock connected to the CLKIN input pin. This pin may be driven directly
by CMOS buffers. The mark/space ratio on the clock can vary
from 40/60 to 60/40. As the clock frequency is slowed down, it
can result in slightly degraded accuracy performance. This is
due to leakage effects on the hold capacitor in the internal
track-and-hold amplifier. Figure 8 is a typical plot of accuracy
versus clock frequency for the ADC.
OUTPUT
CODE
2.5
111...111
111...110
NORMALIZED LINEARITY ERROR
111...101
111...100
000...011
FS
1LSB =
4096
000...010
2.0
1.5
1.0
0.5
000...001
000...000
0V
+FS – 1LSB
1LSB
0.0
VIN INPUT VOLTAGE
Figure 6. Unipolar Transfer Characteristics
100...101
100...000
011...111
011...110
000...001
000...000
AA
AA
–FS
2
TRACK/HOLD AMPLIFIER
The charge balanced comparator used in the AD7883 for the
A/D conversion provides the user with an inherent track/hold
function. The track/hold amplifier acquires an input signal to
12-bit accuracy in less than 5 µs. The overall throughput time is
equal to the conversion time plus the track/hold amplifier acquisition time. For a 2 MHz input clock, the throughput time is
20 µs.
AA
AA
AA
111...111
111...110
–1LSB
The operation of the track/hold amplifier is essentially transparent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion, i.e., on the rising edge of CONVST as shown in Figure 1.
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal range match the maximum possible dynamic range of the
ADC. In such applications, offset and full-scale error will have
to be adjusted to zero.
+FS
– 1LSB
2
+1LSB
2.0
3.0
CLOCK FREQUENCY – MHz
Figure 8. Normalized Linearity Error vs. Clock Frequency
Figure 5 shows the AD7883’s ± VREF bipolar analog input configuration. Once again the designed code transitions occur midway between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 6.6 V/4096 = 1.6 mV.
The ideal bipolar input/output transfer characteristic is shown
in Figure 7.
OUTPUT
CODE
1.0
FS = 10V
FS
4096
1LSB =
0V
VIN INPUT VOLTAGE
The following sections describe suggested offset and full-scale
adjustment techniques which rely on adjusting the inherent offset of the op amp driving the input to the ADC as well as tweaking an additional external potentiometer as shown in Figure 9.
Figure 7. Bipolar Transfer Characteristic
–6–
REV. 0
AD7883
Signal-to-Noise Ratio (SNR)
R1
10kΩ
V1
R2
500Ω
+
VINA
–
R4
10kΩ
R3
10kΩ
AD7883*
R5
10kΩ
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by:
SNR = (6.02 N + 1.76) dB
AGND
*ADDITIONAL PINS OMITTED FOR CLARITY
(1)
where N is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
Figure 9. Offset and Full-Scale Adjust Circuit
Unipolar Adjustments
In the case of the 0 V to 3.3 V unipolar input configuration, unipolar offset error must be adjusted before full-scale error. Adjustment is achieved by trimming the offset of the op amp
driving the analog input of the AD7883. This is done by applying an input voltage of 0.4 mV (1/2 LSB) to V1 in Figure 9 and
adjusting the op amp offset voltage until the ADC output code
flickers between 0000 0000 0000 and 0000 0000 0001. For fullscale adjustment, an input voltage of 3.2988 V (FS–3/2 LSBs) is
applied to V1 and R2 is adjusted until the output code flickers
between 1111 1111 1110 and 1111 1111 1111.
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input which is
sampled at a 50 kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be obtained. Figure 10 shows a typical 2048 point FFT plot of the
AD7883 with an input signal of 2.5 kHz and a sampling frequency of 50 kHz. The SNR obtained from this graph is 71 dB.
It should be noted that the harmonics are taken into account
when calculating the SNR.
0
INPUT FREQUENCY = 2.5kHz
SAMPLE FREQUENCY = 50kHz
SNR = 71.4dB
T A = +25°C
–30
SIGNAL AMPLITUDE – dBs
Bipolar Adjustments
Bipolar zero and full-scale errors for the bipolar input configuration of Figure 5 are adjusted in a similar fashion to the unipolar
case. Again, bipolar zero error must be adjusted before full-scale
error. Bipolar zero error adjustment is achieved by trimming the
offset of the op amp driving the analog input of the AD7883
while the input voltage is 1/2 LSB below ground. This is done
by applying an input voltage of –0.8 mV (1/2 LSB) to V1 in Figure 9 and adjusting the op amp offset voltage until the ADC
output code flickers between 0111 1111 1111 and 1000 0000
0000. For full-scale adjustment, an input voltage of 3.2988 V
(FS/2–3/2 LSBs) is applied to V1 and R2 is adjusted until the
output code flickers between 1111 1111 1110 and 1111 1111
1111.
–60
–90
–120
0
2.5
FREQUENCY – kHz
25
Figure 10. FFT Plot
DYNAMIC SPECIFICATIONS
Effective Number of Bits
The AD7883 is specified and tested for dynamic performance
specifications as well as traditional dc specifications such as integral and differential nonlinearity. The ac specifications are required for signal processing applications such as speech
recognition, spectrum analysis and high speed modems. These
applications require information on the ADC’s effect on the
spectral content of the input signal. Hence, the parameters for
which the AD7883 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These
terms are discussed in more detail in the following sections.
The formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
REV. 0
N=
SNR –1.76
6.02
(2)
The effective number of bits for a device can be calculated directly from its measured SNR.
Figure 11 shows a plot of effective number of bits versus input
frequency for an AD7883 with a sampling frequency of 50 kHz.
The effective number of bits typically remains better than 11.5
for frequencies up to 12 kHz.
–7–
AD7883
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order
terms are usually distanced in frequency from the original sine
waves, while the third order terms are usually at a frequency
close to the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where
it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.
In this case, the input consists of two, equal amplitude, low distortion, sine waves. Figure 12 shows a typical IMD plot for the
AD7883.
EFFECTIVE NUMBER OF BITS
12
11.5
11
10.5
SAMPLE FREQUENCY = 50kHz
TA = +25 °C
5
10
15
INPUT FREQUENCY – kHz
20
Figure 11. Effective Number of Bits vs. Frequency
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. For the AD7883, THD is defined as:
THD = 20 log
V22 +V32 +V 42 +V52 +V62
V1
INPUT FREQUENCY
F1 = 0.983kHz
F2 = 1.05kHz
SAMPLE FREQUENCY = 50kHz
25
SIGNAL AMPLITUDE – dBs
10
0
–30
TA = +25°C
IMD
ALL TERMS = 81.5dB
2ND ORDER TERMS = 83.6dB
3RD ORDER TERMS = 85.4dB
–60
–90
(3)
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
–120
0
25
2.5
FREQUENCY – kHz
Figure 12. IMD Plot
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
–8–
REV. 0
AD7883
APPLICATION HINTS
LK2
A B
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed A/D performance.
The AD7883’s comparator is required to make bit decisions on
an LSB size of 0.8 mV. To achieve this, the designer must be
conscious of noise both in the ADC itself and in the preceding
analog circuitry. Switching mode power supplies are not recommended, as the switching spikes will feed through to the comparator causing noisy code transitions. Other causes of concern
are ground loops and digital feedthrough from microprocessors.
These are factors which influence any ADC, and a proper
PCB layout which minimizes these effects is essential for best
performance.
VDD
V+
V+
ANALOG
INPUT
C1
10µF
C2
0.1µF
LK1
SKT1
V+
+
IC1
–
TO ADC
V–
C3
10µF
C4
0.1µF
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible. Take
care not to run digital tracks alongside analog signal tracks.
Guard (screen) the analog input with AGND.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AD7883 AGND pin or as
close as possible to the AD7883. Connect all other grounds and
the AD7883 DGND to this single analog ground point. Do not
connect any other digital grounds to this analog ground point.
Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. The use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise.
NOISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable between the source and the ADC. Reduce the ground circuit impedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
REV. 0
V–
A B
LK3
Figure 13. Analog Input Buffering
ANALOG INPUT BUFFERING
To achieve specified performance, it is recommended that the
analog input (VINA , VINB) be driven from a low impedance
source. This necessitates the use of an input buffer amplifier.
The choice of op amp will be a function of the particular application and the desired analog input range.
The simplest configuration is the 0 V to VREF range of Figure 4.
A single supply op amp is recommended for such an implementation. This will allow for operation of the AD7883 in the 0 to
VREF unipolar range without supplying an external supply to V+
and V– of the op amp. Recommended single-supply op amps
are the OP-195 and AD820.
In bipolar operation, positive and negative supplies must be
connected to V+ and V– of the op amp.
The AD711 is a general purpose op amp which could be used
to drive the analog input of the AD7883, in this input range.
–9–
AD7883
be carried out. Figure 14 gives a plot of power consumption as a
function of time for such operation. The total conversion time
for each cycle is 11 × 20 µs (where 20 µs is the time taken for a
single conversion) corresponding to 2.2 × 10–4 secs.
POWER-DOWN CONTROL (MODE INPUT)
The AD7883 is designed for systems which need to have minimum power consumption. This includes such applications as
hand held, portable battery powered systems and remote monitoring systems. As well as consuming minimum power under
normal operating conditions, typically 8 mW, the AD7883 can
be put into a power-down or sleep mode when not required to
convert signals. When in this power-down mode, the AD7883
consumes 1 mW of power.
CONVERTING
CONVERTING
8
POWER
CONSUMPTION
– mW
POWER-DOWN
POWER-DOWN
1
0
The AD7883 is powered down by bringing the MODE input
pin to a Logic Low in conjunction with keeping the RD input
control High. The AD7883 will remain in the power-down
mode until MODE is brought to a Logic High again. The
MODE input should be driven with CD4000 or HCMOS logic
levels.
2.2 x 10–4
1
2
TIME – secs
Figure 14. Power Consumption for Normal Operation and
Power-Down Operation vs. Time
Hence:
It is recommended that one “dummy” conversion be implemented before reading conversion data from the AD7883 after it
has been in the powerdown mode. This is required to reset all
internal logic and control circuitry. Allow one clock cycle before
doing the dummy conversion. In a remote monitoring system
where, say, 10 conversions are required to be taken with a sampling interval of 1 second, an additional 11th conversion must
Average Power
–10–
= PowerCONVERTING + Power POWER-DOWN
= {8 mW × (2.2 × 10–4)}
+ {1 mW × (0.9998)}
= 1.0015 mW
REV. 0
AD7883
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP (N-24)
24-Lead SOIC (R-24)
REV. 0
–11–
–12–
PRINTED IN U.S.A.
C1699–24–9/92