® ADS ADS820 820 ADS U 820 E 10-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES DESCRIPTION ● NO MISSING CODES The ADS820 is a low power, monolithic 10-bit, 20MHz analog-to-digital converter utilizing a small geometry CMOS process. This COMPLETE converter includes a 10-bit quantizer with internal track/hold, reference, and a power down feature. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals. The ADS820 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR and high oversampling capability give it the extra margin needed for telecommunications and video applications. This high performance converter is specified for AC and DC performance at a 20MHz sampling rate. The ADS820 is available in 28-pin SOIC and SSOP packages. ● INTERNAL REFERENCE ● LOW DIFFERENTIAL LINEARITY ERROR: 0.2LSB ● LOW POWER: 195mW ● HIGH SNR: 60dB ● WIDEBAND TRACK/HOLD: 65MHz ● PACKAGES: 28-Pin SOIC and 28-PIN SSOP APPLICATIONS ● SET-TOP BOXES ● CABLE MODEMS ● VIDEO DIGITIZING ● CCD IMAGING Camcorders Copiers Scanners Security Cameras ● IF AND BASEBAND DIGITIZATION CLK MSBI OE Error Correction Logic 3-State Outputs Timing Circuitry IN Pipeline A/D T/H IN 10-Bit Digital Data +3.25V REFT CM REFB +1.25V International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1995 Burr-Brown Corporation PDS-1288D Printed in U.S.A. October, 1996 SPECIFICATIONS At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. ADS820U, E PARAMETER CONDITIONS Resolution Specified Temperature Range ANALOG INPUT Differential Full Scale Input Range Common-Mode Voltage Analog Input Bandwidth (–3dB) Small Signal Full Power TEMP MIN –40 +1.25 –20dBFS(1) Input 0dB Input +25°C +25°C +85 Bits °C 2.25 +3.25 V V 120 65 MHz MHz 1.25 || 4 MΩ || pF ±0.6 ±1.0 ±85 0.01 ±2.1 0.02 +25°C Full Delta +VS = ±5% +25°C Full +25°C Delta +VS = ±5% CONVERSION CHARACTERISTICS Sample Rate Data Latency 10k ±1.5 ±2.5 0.1 ±3.0 0.1 ±0.15 ±0.15 ±0.2 ±0.2 Guaranteed ±0.5 +25°C Full +25°C Full Full Full f = 10MHz No Missing Codes Integral Linearity Error at f = 500kHz Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) +25°C Full +25°C Full f = 10MHz (–1dBFS input) Two-Tone Intermodulation Distortion (IMD)(3) f = 4.4MHz and 4.5MHz (referred to –1dBFS envelope) 67 64 59 57 +25°C Full Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) f = 10MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 10MHz (–1dBFS input) NTSC or PAL NTSC or PAL fIN = 3.58MHz Sample/s Convert Cycle ±1.0 ±1.0 ±1.0 ±1.0 LSB LSB LSB LSB ±2.0 LSB 77 74 63 62 dBFS dBFS dBFS dBFS –61 –60 dBc dBc +25°C Full +25°C Full 58 56 58 56 60.5 60 60 60 dB dB dB dB +25°C Full +25°C Full +25°C +25°C 58 55 56 54 60.5 60 58 57 0.5 0.1 9.5 2 7 2 dB dB dB dB % degrees Bits ns ps rms ns +25°C +25°C +25°C 1.5x Full Scale Input % % ppm/°C %FSR/% % %FSR/% 20M 6.5 DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz Differential Gain Error Differential Phase Error Effective Bits(4) Aperture Delay Time Aperture Jitter Overvoltage Recovery Time(5) UNITS TTL/HCT Compatible CMOS Falling Edge Start Conversion ACCURACY(2) Gain Error Gain Tempco Power Supply Rejection of Gain Input Offset Error Power Supply Rejection of Offset MAX 10 Guaranteed TAMBIENT Input Impedance DIGITAL INPUT Logic Family Convert Command TYP NOTE: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D Full Scale Range of 4Vp-p. (3) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) Based on (SINAD – 1.76)/6.02. (5) No "rollover" of bits. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS820 2 SPECIFICATIONS (CONT) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. ADS820U, E PARAMETER CONDITIONS OUTPUTS Logic Family Logic Coding Logic Levels TEMP MIN TYP Full Full 3-State Enable Time 3-State Disable Time 20 2 0.4 +VS 40 10 V V V ns ns +5 39 40 195 200 +5.25 47 55 235 275 V mA mA mW mW 0 2.5 Full Operating Operating Operating Operating Operating Power Consumption UNITS TTL/HCT Compatible CMOS SOB or BTC Logic Selectable Logic “LO”, CL = 15pF Logic “HI”, CL = 15pF POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS MAX Full +25°C Full +25°C Full Thermal Resistance, θJA 28-Pin SOIC 28-Pin SSOP +4.75 °C/W °C/W 75 50 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input .............................................................. 0V to (+VS + 300mV) Logic Input ................................................................ 0V to (+VS + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Top Reference Voltage (REFT) .................................. +3.4V Max External Bottom Reference Voltage (REFB) .............................. +1.1V Min This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. NOTE: Stresses above these ratings may permanently damage the device. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ADS820U ADS820E 28-Pin SOIC 28-Pin SSOP 217 324 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 ADS820 PIN DESCRIPTIONS PIN CONFIGURATION TOP VIEW SOIC/SSOP PIN DESIGNATOR GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DNC DNC GND +VS CLK +VS OE GND 1 28 GND Bit 1(MSB) 2 27 IN Bit 2 3 26 IN Bit 3 4 25 GND Bit 4 5 24 +VS Bit 5 6 23 REFT Bit 6 7 22 CM Bit 7 8 21 REFB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Bit 8 9 20 +VS 19 MSBI Bit 9 10 19 MSBI Bit 10 (LSB) 11 18 OE 20 21 +VS REFB DNC 12 17 +VS DNC 13 16 CLK 22 CM GND 14 15 +VS 23 REFT 24 25 26 27 28 +VS GND IN IN GND ADS820 DNC: Do Not Connect DESCRIPTION Ground Bit 1, Most Significant Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10, Least Significant Bit Do not connect. Do not connect. Ground +5V Power Supply Convert Clock Input, 50% Duty Cycle +5V Power Supply HI: High Impedance State. LO or Floating: Normal Operation. Internal pull-down resistor. Most Significant Bit Inversion, HI: MSB inverted for complementary output. LO or Floating: Straight output. Internal pull-down resistor. +5V Power Supply Bottom Reference Bypass. For external bypassing of internal +1.25V reference. Common-Mode Voltage. It is derived by (REFT + REFB)/2. Top Reference Bypass. For external bypassing of internal +3.25V reference. +5V Power Supply Ground Input Complementary Input Ground TIMING DIAGRAM tCONV tL CONVERT CLOCK tD tH DATA LATENCY (6.5 Clock Cycles) Hold Hold Hold Hold Hold Hold Track "N + 1" Track "N + 2" Track "N + 3" Track "N + 4" Track "N + 5" Track "N + 6" Track (1) Track INTERNAL TRACK/HOLD Hold "N" t2 OUTPUT DATA Data Valid N-8 Data Valid N-7 Data Valid N-6 N-5 N-4 N-3 N-2 N-1 t1 Data Invalid SYMBOL tCONV tL tH tD t1 t2 NOTE: (1) “ DESCRIPTION MIN Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 50 24 24 MAX UNITS 100µs ns ns ns ns ns ns 25 25 2 3.9 12.5 ” indicates the portion of the waveform that will stretch out at slower sample rates. ® ADS820 TYP 4 N TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 500kHz fS = 10MHz fIN = 4.8MHz –20 –40 Amplitude (dB) Amplitude (dB) –20 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 Frequency (MHz) 6.0 0 fIN = 9.8MHz f1 = 4.5MHz –20 –20 Amplitude (dB) Amplitude (dB) 10.0 TWO-TONE INTERMODULATION SPECTRAL PERFORMANCE 0 –40 –60 –80 –100 f2 = 4.4MHz –40 –60 –80 –100 –120 –120 0 2.0 4.0 6.0 8.0 0.0 10.0 2.50 Frequency (MHz) 5.00 7.50 10.00 Frequency (MHz) DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 2.0 2.0 fIN = 10MHz fIN = 500kHz 1.0 DLE (LSB) 1.0 DLE (LSB) 8.0 Frequency (MHz) 0 0 –1.0 –1.0 –2.0 –2.0 24 224 424 624 824 24 1024 224 424 624 824 1024 Code Code ® 5 ADS820 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SWEPT POWER SFDR DYNAMIC PERFORMANCE vs INPUT FREQUENCY 100 85 fIN = 10MHz 80 80 75 SFDR (dBFS) SFDR, SNR (dB) SFDR 70 65 SNR 60 40 20 60 55 100k 0 1M 10M –50 100M –40 –30 –20 –10 0 10 Input Amplitude (dBm) Frequency (Hz) SWEPT POWER SNR INTEGRAL LINEARITY ERROR 60 4.0 fIN = 500kHz fIN = 10MHz 50 2.0 ILE (LSB) SNR (dB) 40 30 0 20 –2.0 10 0 –48.125 –4.0 –40 –30 –20 –10 0 10 24 424 624 824 Code DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE 80 80 SFDR (fIN = 500kHz) 1024 SFDR (fIN = 500kHz) 75 Dynamic Range (dB) 75 Dynamic Range (dB) 224 Input Amplitude (dBm) 70 SFDR (fIN = 10MHz) 65 SNR (fIN = 500kHz) 60 70 SFDR (fIN = 10MHz) 65 SNR (fIN = 500kHz) 60 SNR (fIN = 10MHz) SNR (fIN = 10MHz) 55 55 1 2 3 4 5 1 Single-Ended Full-Scale Input Range (Vp-p) NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V. 3 4 5 NOTE: REFTEXT varied, REFB is fixed at internal value of +1.25V. ® ADS820 2 Differential Full-Scale Input Range (Vp-p) 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.3 90 fIN = 500kHz 80 0.2 SFDR (dBFS) DLE (LSB) fIN = 10MHz 0.1 fIN = 500kHz 70 60 fIN = 10MHz 0 50 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 75 100 Ambient Temperature (°C) Ambient Temperature (°C) SIGNAL-TO-NOISE RATIO vs TEMPERATURE SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE 70 62 fIN = 500kHz 65 60 SINAD (dB) SNR (dB) fIN = 500kHz 60 fIN = 10MHz 55 58 fIN = 10MHz 56 50 54 –50 –25 0 25 50 75 100 –50 –25 Ambient Temperature (°C) 0 25 50 Ambient Temperature (°C) SUPPLY CURRENT vs TEMPERATURE POWER DISSIPATION vs TEMPERATURE 42 210 200 IQ (mA) Power (mW) 40 38 190 180 36 –50 –25 0 25 50 75 170 100 –50 Ambient Temperature (°C) –25 0 25 50 75 100 Ambient Temperature (°C) ® 7 ADS820 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. GAIN ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE Offset (% FSR) –1.75 –0.55 –1.05 –1.55 –2.0 –2.25 –2.50 –50 –25 0 25 50 75 100 –50 –25 0 Ambient Temperature (°C) 0 1M –1 0.8M Counts 1.2M –2 0.4M –4 0.2M –5 1M 10M 100M 0.0 N–2 1G Frequency (Hz) N–1 N Code ® ADS820 75 100 0.6M –3 100k 50 OUTPUT NOISE HISTOGRAM (NO SIGNAL) 1 10k 25 Ambient Temperature (°C) TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH Track-Mode Input Response (dB) Gain (% FSR) –0.05 8 N+1 N+2 THEORY OF OPERATION Op Amp Bias The ADS820 is a high speed sampling analog-to-digital converter with pipelining. It uses a fully differential architecture and digital error correction to guarantee 10-bit resolution. The differential track/hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping two phase signal, φ1 and φ2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time the charge redistributes between CI and CH, completing one track/hold cycle. The differential output is a held DC representation of the analog input at the sample time. The track/hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. The pipelined quantizer architecture has 9 stages with each stage containing a two-bit quantizer and a two bit digital-toanalog converter, as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the sub-clock, which is twice the frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to IN IN φ1 φ1 CH φ2 CI IN IN φ1 φ2 OUT φ1 OUT φ1 CI φ2 CH φ1 φ1 Input Clock (50%) Op Amp Bias VCM Internal Non-overlapping Clock φ1 φ2 φ1 FIGURE 1. Input Track/Hold Configuration with Timing Signals. Digital Delay Input T/H 2-Bit Flash STAGE 1 VCM 2-Bit DAC + Σ – x2 Digital Delay STAGE 2 B1 (MSB) 2-Bit DAC B2 Digital Error Correction 2-Bit Flash + Σ – x2 B3 B4 B5 B6 B7 B8 B9 Digital Delay 2-Bit Flash STAGE 8 B10 (LSB) 2-Bit DAC + Σ – x2 STAGE 9 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Architecture. ® 9 ADS820 DIGITAL OUTPUT DATA time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique gives the ADS820 excellent differential linearity and guarantees no missing codes at the 10-bit level. The 10-bit output data is provided at CMOS logic levels. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all “1’s” at the output. This condition is met with pin 19 “LO” or Floating due to an internal pull-down resistor. By applying a high voltage to this pin, a Binary Two’s Complement output will be provided where the most significant bit is inverted. The digital outputs of the ADS820 can be set to a high impedance state by driving OE (pin 18) with a logic “HI”. Normal operation is achieved with pin 18 “LO” or Floating due to internal pull-down resistors. This function is provided for testability purposes and is not meant to drive digital buses directly or be dynamically changed during the conversion process. There is a 6.5 clock cycle data latency from the start convert signal to the valid output data. The output data is available in Straight Offset Binary (SOB) or Binary Two’s Complement (BTC) format. THE ANALOG INPUT AND INTERNAL REFERENCE The analog input of the ADS820 can be configured in various ways and driven with different circuits, depending on the nature of the signal and the level of performance desired. The ADS820 has an internal reference that sets the full scale input range of the A/D. The differential input range has each input centered around the common-mode of +2.25V, with each of the two inputs having a full scale range of +1.25V to +3.25V. Since each input is 2V peak-to-peak and 180° out of phase with the other, a 4V differential input signal to the quantizer results. As shown in Figure 3, the positive full scale reference (REFT) and the negative full scale reference (REFB) are brought out for external bypassing. In addition, the common-mode voltage (CM) may be used as a reference to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this reference node. For more information regarding external references, single-ended inputs, and ADS820 drive circuits, refer to the applications section. OUTPUT CODE DIFFERENTIAL INPUT(1) SOB PIN 19 FLOATING or LO BTC PIN 19 HI 1111111111 1111111111 1111111110 1110000000 1100000000 1010000000 1000000001 1000000000 0111111111 0110000000 0100000000 0010000000 0000000001 0000000000 0111111111 0111111111 0111111110 0110000000 0100000000 0010000000 0000000001 0000000000 1111111111 1110000000 1100000000 1010000000 1000000001 1000000000 +FS (IN = +3.25V, IN = +1.25V) +FS –1LSB +FS –2LSB +3/4 Full Scale +1/2 Full Scale +1/4 Full Scale +1LSB Bipolar Zero (IN = IN = +2.25V) –1LSB –1/4 Full Scale –1/2 Full Scale –3/4 Full Scale –FS +1LSB –FS (IN = +1.25V, IN = +3.25V) Note: In the single-ended input mode, +FS = +4.25V and –FS = +0.25V. TABLE I. Coding Table for the ADS820. ADS820 +3.25V 23 APPLICATIONS REFT DRIVING THE ADS820 0.1µF 2kΩ +2.25V 22 The ADS820 has a differential input with a common-mode of +2.25V. For AC-coupled applications, the simplest way to create this differential input is to drive the primary winding of a transformer with a single-ended input. A differential output is created on the secondary if the center tap is tied to the common-mode voltage (CM) of +2.25V per Figure 4. This transformer-coupled input arrangement pro- To Internal Comparators CM 2kΩ 21 REFB 0.1µF +1.25V FIGURE 3. Internal Reference Structure. 22 CM CLOCK REQUIREMENTS 0.1µF The CLK pin accepts a CMOS level clock input. The rising and falling edge of the externally applied convert command clock control the various interstage conversions in the pipeline. Therefore, the duty cycle of the clock should be held at 50% with low jitter and fast rise/fall times of 2ns or less. This is especially important when digitizing a high frequency input and operating at the maximum sample rate. Deviation from a 50% duty cycle will effectively shorten some of the interstage settling times, thus degrading the SNR and DNL performance. ADS820 22pF Mini-Circuits TT1-6-KK81 or equivalent 27 IN 22pF FIGURE 4. AC-Coupled Single-Ended to Differential Drive Circuit Using a Transformer. ® ADS820 26 IN AC Input Signal 10 vides good high frequency AC performance. It is important to select a transformer that gives low distortion and does not exhibit core saturation at full scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the common-mode (CM) output in this instance. In general, it is advisable to keep the current draw from the CM output pin below 0.5µA to avoid nonlinearity in the internal reference ladder. A FET input operational amplifier such as the OPA130 can provide a buffered reference for driving external circuitry. The analog IN and IN inputs should be bypassed with 22pF capacitors to minimize track/hold glitches and to improve high input frequency performance. each input. The cut-off frequency of the filter is determined by fC = 1/(2πRSER•(CSH+CADC)) where RSER is the resistor in series with the input, CSH is the external capacitor from the input to ground, and CADC is the internal input capacitance of the A/D converter (typically 4pF). Resistors R1 and R2 are used to derive the necessary common mode voltage from the buffered top and bottom references. The total load of the resistor string should be selected so that the current does not exceed 1mA. Although the circuit in Figure 5 uses two resistors of equal value so that the common mode voltage is centered between the top and bottom reference (+2.25V), it is not necessary to do so. In all cases the center point, VCM, should be bypassed to ground in order to provide a low impedance AC ground. Figure 5 illustrates another possible low cost interface circuit which utilizes resistors and capacitors in place of a transformer. Depending on the signal bandwidth, the component values should be carefully selected in order to maintain the performance outlined in the data sheet. The input capacitors, CIN, and the input resistors, RIN, create a high-pass filter with the lower corner frequency at fC = 1/(2πRINCIN). The corner frequency can be reduced by either increasing the value of RIN or CIN. If the circuit operates with a 50Ω or 75Ω impedance level, the resistors are fixed and only the value of the capacitor can be increased. Usually AC-coupling capacitors are electrolytic or tantalum capacitors with values of 1µF or higher. It should be noted that these large capacitors become inductive with increased input frequency, which could lead to signal amplitude errors or oscillation. To maintain a low AC-coupling impedance throughout the signal band, a small value (e.g. 1µF) ceramic capacitor could be added in parallel with the polarized capacitor. If the signal needs to be DC coupled to the input of the ADS820, an operational amplifier input circuit is required. In the differential input mode, any single-ended signal must be modified to create a differential signal. This can be accomplished by using two operational amplifiers, one in the noninverting mode for the input and the other amplifier in the inverting mode for the complementary input. The low distortion circuit in Figure 6 will provide the necessary input shifting required for signals centered around ground. It also employs a diode for output level shifting to guarantee a low distortion +3.25V output swing. Another DC-coupled circuit is shown in Figure 7. Other amplifiers can be used in place of the OPA642s if the lowest distortion is not necessary. If output level shifting circuits are not used, care must be taken to select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier. The OPA620 and OPA621, or the lower power OPA650 and OPA651 can be used in place of the OPA642s in Figure 6. In that configuration, the OPA650 and OPA651 will typically swing to within 100mV of positive full scale. If the OPA621 or OPA651 is used, the input buffer must be configured in a gain of 2. Capacitors CSH1 and CSH2 are used to minimize current glitches resulting from the switching in the input track and hold stage and to improve signal-to-noise performance. These capacitors can also be used to establish a low-pass filter and effectively reduce the noise bandwidth. In order to create a real pole, resistors RSER1 and RSER2 were added in series with C1 0.1µF CIN 0.1µF *RSER1 49.9Ω R1 (6kΩ) +3.25V Top Reference IN RIN1 25Ω RIN2 25Ω CIN 0.1µF CSH1 22pF R3 1kΩ C2 0.1µF *RSER2 49.9Ω ADS8xx VCM R2 (6kΩ) IN CSH2 22pF +1.25V Bottom Reference C3 0.1µF NOTE: * indicates optional component. FIGURE 5. AC-Coupled Differential Input Circuit. ® 11 ADS820 +5V 604Ω +5V 301Ω BAS16(1) (3) Optional High Impedance Input Amplifier 301Ω 301Ω 27 IN OPA642 2.49kΩ +5V(2) 22pF 0.1µF 0.1µF –5V DC-Coupled Input Signal +5V (3) OPA642 604Ω 604Ω ADS820 49.9Ω OPA130 +5V –5V 2.49kΩ +2.25V 22 CM +5V 301Ω 24.9Ω Input Level Shift Buffer 301Ω BAS16(1) (3) 26 IN OPA642 22pF 0.1µF –5V NOTES: (1) A Philips BAS16 diode or equivalent may be used. (2) Supply bypassing not shown. (3) OPA620 or OPA650 may be substituted. See "Driving the ADS820" section. 604Ω 301Ω FIGURE 6. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit. DC-Coupled Input Signal 2kΩ +5V –5V 7 4 1 3 243Ω –5V B C 2 E 26 IN +1 OTA 6 1kΩ 22pF OPA660 8 200Ω 1nF 5 500Ω +5V 1kΩ ADS820 2 50Ω OPA130 1kΩ C1 15pF 200Ω 500Ω 8 2 E 3 B 3 22 CM 0.1µF 200Ω 5 OTA VOUT +1 6 C 243Ω –5V OPA660 27 IN 22pF NOTE: Power supplies and bypassing not shown. The measured SNR performance with 12.5MHz input signal is 57dB with this driver circuit. FIGURE 7. A Wideband DC-Coupled, Single-Ended to Differential Input Driver Circuit. The ADS820 can also be configured with a single-ended input full scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference voltage as shown in Figure 8. This configuration will result in increased even-order harmonics, especially at higher input frequencies. However, this tradeoff may be quite acceptable for time-domain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case. 22 CM 0.1µF ADS820 Single-Ended Input Signal 26 IN 27 IN 22pF Full Scale = +0.25V to +4.25V with internal references. FIGURE 8. Single-Ended Input Connection. ® ADS820 12 DYNAMIC PERFORMANCE TESTING EXTERNAL REFERENCES AND ADJUSTMENT OF FULL SCALE RANGE The ADS820 is a high performance converter and careful attention to test techniques is necessary to achieve accurate results. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using data windowing functions. A low jitter signal generator such as the HP8644A for the test signal, phase-locked with a low jitter HP8022A pulse generator for the A/D clock, gives excellent results. Low pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low distortion of the ADS820. Using a signal amplitude slightly lower than full scale will allow a small amount of “headroom” so that noise or DC offset voltage will not overrange the A/D and cause clipping on signal peaks. The internal reference buffers are limited to approximately 1mA of output current. As a result, these internal +1.25V and +3.25V references may be overridden by external references that have at least 18mA (at room temperature) of output drive capability. In this instance, the common-mode voltage will be set halfway between the two references. This feature can be used to adjust the gain error, improve gain drift, or to change the full scale input range of the ADS820. Changing the full scale range to a lower value has the benefit of easing the swing requirements of external input amplifiers. The external references can vary as long as the value of the external top reference (REFTEXT) is less than or equal to +3.4V and the value of the external bottom reference (REFBEXT) is greater than or equal to +1.1V and the difference between the external references are greater than or equal to 800mV. DYNAMIC PERFORMANCE DEFINITIONS 1. Signal-to-Noise-and-Distortion Ratio (SINAD): Sinewave Signal Power 10 log Noise + Harmonic Power (first 15 harmonics) For the differential configuration, the full scale input range will be set to the external reference values that are selected. For the single-ended mode, the input range is 2•(REFTEXT – REFBEXT), with the common-mode being centered at (REFTEXT + REFBEXT)/2. Refer to the typical performance curves for expected performance vs full scale input range. 2. Signal-to-Noise Ratio (SNR): Sinewave Signal Power 10 log Noise Power The circuit in Figure 9 works completely on a single +5V supply. As a reference element, it uses the micro-power reference REF1004-2.5, which is set to a quiescent current of 0.1mA. Amplifier A2 is configured as a follower to buffer the +1.25V generated from the resistor divider. To provide the necessary current drive, a pull-down resistor, RP is added. Amplifier A1 is configured as an adjustable gain stage, with a range of approximately 1 to 1.32. The pull-up resistor again relieves the op amp from providing the full current drive. The value of the pull-up/down resistors is not critical and can be varied to optimize power consumption. The need for pull-up/down resistors depends only on the drive capability of the selected drive amplifiers and thus can be omitted. 3. Intermodulation Distortion (IMD): Highest IMD Product Power (to 5th-order) 10 log Sinewave Signal Power IMD is referenced to the larger of the test signals f1 or f2. Five “bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. PC BOARD LAYOUT AND BYPASSING A well-designed, clean PC board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high frequency circuits. Multilayer PC boards are recommended for best performance but if carefully designed, a two-sided PC board with large, heavy ground planes can give excellent results. It is recommended that the analog and digital ground pins of the ADS820 be connected directly to the analog ground plane. In our experience, this gives the most consistent results. The A/D power supply commons should be tied together at the analog ground plane. Power supplies should be bypassed with 0.1µF ceramic capacitors as close to the pin as possible. ® 13 ADS820 +5V RP 220Ω A1 1/2 OPA2234 +5V Top Reference +2.5V to +3.25V 2kΩ 10kΩ 6.2kΩ 10kΩ REF1004 +2.5V A2 0.1µF +1.25V 1/2 OPA2234 10kΩ* 10kΩ Bottom Reference RP 220Ω 10kΩ* NOTE: (*) Use parts alternatively for adjustment capability. FIGURE 9. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. IDT74FCT2245 +5V 0.1µF +VS CLK Ext Clk 0.1µF R1 50Ω +VS OE MSBI 0.1µF +VS REFB CM REFT 0.1µF 0.1µF 0.1µF 0.1µF AC Input Signal +VS GND IN R2 50Ω IN 22pF Mini-Circuits TT1-6-KK81 or equivalent (1) 22pF GND 15 14 16 13 17 12 18 11 19 10 20 9 GND 24 25 26 27 28 7 14 6 15 5 16 4 17 3 18 2 DNC 1 LSB 19 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 7 6 5 4 3 2 1 MSB GND FIGURE 10. ADS820 Interface Schematic with AC-Coupling and External Buffers. 14 G+ 11 1 19 ® Dir IDT74FCT2245 NOTE: (1) All capacitors should be located as close to the pins as the manufacturing process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended. ADS820 8 13 DNC ADS820 23 9 12 8 21 22 11 Dir G+