19-3273; Rev 1; 7/04 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock The MAX7033 is available in a 28-pin TSSOP package and is specified over the extended (-40°C to +105°C) temperature range. Features ♦ Optimized for 315MHz or 433MHz Band ♦ Operates from Single +3.3V or +5.0V Supplies ♦ High Dynamic Range with On-Chip AGC ♦ AGC Hold Circuit ♦ 1ms AGC Release Time ♦ Selectable Image-Rejection Center Frequency ♦ Selectable x64 or x32 fLO/fXTAL Ratio ♦ Low 5.2mA Operating Supply Current ♦ <3.5µA Low-Current Power-Down Mode for Efficient Power Cycling ♦ 250µs Startup Time ♦ Built-In 44dB RF Image Rejection ♦ Better than -114dBm Receive Sensitivity ♦ -40°C to +105°C Operation Applications Automotive Remote Keyless Entry Security Systems Garage Door Openers Ordering Information Home Automation Remote Controls Local Telemetry Wireless Sensors Typical Application Circuit appears at end of data sheet. PART TEMP RANGE PIN-PACKAGE MAX7033EUI -40°C to +105°C 28 TSSOP MAX7033ETJ* -40°C to +105°C 32 Thin QFN-EP** *Future product—contact factory for availability. **EP = Exposed paddle. 25 DATAOUT AGND 5 LNAOUT 6 MAX7033 AVDD 7 AVDD XTAL1 XTAL2 SHDN PDOUT N.C. 29 28 27 26 25 26 PDOUT LNASRC 4 LNAIN 27 SHDN LNAIN 3 30 28 XTAL2 AVDD 2 LNASRC XTAL1 1 31 TOP VIEW 32 Pin Configurations N.C. 1 24 DATAOUT 24 VDD5 AGND 2 23 VDD5 23 DSP LNAOUT 3 22 DSP AVDD 4 21 N.C. 20 DFFB 22 DFFB MAX7033 IRSEL 8 17 DFO MIXOUT 12 17 IFIN1 DGND 13 16 XTALSEL DVDD 14 15 AC TSSOP 16 18 IFIN2 IFIN2 DSN IRSEL 11 15 18 IFIN1 7 14 AGND XTALSEL 19 DFO 13 OPP AGND 10 N.C. 19 12 6 AC MIXIN2 11 20 DSN DVDD MIXIN2 9 9 5 10 MIXIN1 DGND 21 OPP MIXOUT MIXIN1 8 THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX7033 General Description The MAX7033 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency range. The receiver has an RF input signal range of -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal for cost-sensitive and power-sensitive applications typical in the automotive and consumer markets. The MAX7033 consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an on-chip phaselocked loop (PLL) with integrated voltage-controlled oscillator (VCO), a 10.7MHz IF limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX7033 also has a discrete one-step automatic gain control (AGC) that reduces the LNA gain by 35dB when the RF input signal exceeds -62dBm. The AGC circuitry offers an externally controlled hold feature. MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock ABSOLUTE MAXIMUM RATINGS VDD5 to AGND.......................................................-0.3V to +6.0V AVDD to AGND ......................................................-0.3V to +4.0V DVDD to DGND......................................................-0.3V to +4.0V AGND to DGND.....................................................-0.1V to +0.1V IRSEL, DATAOUT, XTALSEL, AC, SHDN to AGND .............................-0.3V to (VDD5 + 0.3V) All Other Pins to AGND............................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW 32-Thin QFN (derate 21.3mW/°C above +70°C) ....1702.1mW Operating Temperature Range .........................-40°C to +105°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (+3.3V OPERATION) (Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +3.3V nominal supply voltage 3.0 3.3 3.6 V fRF = 315MHz 5.2 6.23 fRF = 433MHz 5.7 6.88 fRF = 315MHz 2.6 fRF = 433MHz 3.5 Supply Voltage AVDD, DVDD Supply Current IDD V SHDN = DVDD ISHDN V SHDN = 0V, VXTALSEL = 0V Shutdown Supply Current Input-Voltage Low VIL Input-Voltage High VIH Input Logic Current High IIH 0.4 DVDD 0.4 fRF = 375MHz, VIRSEL = VDD5 / 2 VOL ISINK = 10µA DATAOUT Output-Voltage High VOH ISOURCE = 10µA V µA VDD5 0.4 VDD5 1.0 1.1 fRF = 315MHz, VIRSEL = 0V DATAOUT Output-Voltage Low µA V 10 fRF = 433MHz, VIRSEL = VDD5 Image-Reject Select Voltage (Note 2) 8.0 mA V 0.4 0.125 V DVDD 0.125 V DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER Supply Voltage Supply Current Shutdown Supply Current Input-Voltage Low 2 SYMBOL VDD5 CONDITIONS MIN TYP MAX UNITS +5.0V nominal supply voltage 4.5 5.0 5.5 V fRF = 315MHz 5.2 6.4 fRF = 433MHz 5.7 6.76 fRF = 315MHz 3.7 fRF = 433MHz 4.2 IDD V SHDN = VDD5 ISHDN V SHDN = 0V, VXTALSEL = 0V VIL _______________________________________________________________________________________ 9.0 0.4 mA µA V 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock (Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Input-Voltage High VIH Input Logic Current High IIH CONDITIONS TYP MAX VDD5 0.4 fRF = 375MHz, VIRSEL = VDD5 / 2 UNITS V 15 fRF = 433MHz, VIRSEL = VDD5 Image-Reject Select Voltage (Note 2) MIN µA VDD5 0.4 VDD5 1.5 1.1 fRF = 315MHz, VIRSEL = 0V V 0.4 DATAOUT Output-Voltage Low VOL ISINK = 10µA 0.125 V DATAOUT Output-Voltage High VOH ISOURCE = 10µA VDD5 0.125 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Startup Time tON Receiver Input Frequency fRF Maximum Receiver Input Level Time for valid signal detection after V SHDN = DVDD 300 Modulation depth >18dB Sensitivity (Note 3) AGC Hysteresis Maximum Data Rate 250 µs 450 0 Average carrier power level -120 Peak power level -114 MHz dBm dBm LNA gain from low to high 8 dB Switching time from low to high gain 1 ms Manchester coded 33 NRZ coded 66 kbps LNA IN HIGH-GAIN MODE Input Impedance ZIN_LNA 1dB Compression Point Input-Referred 3rd-Order Intercept Normalized to 50Ω Noise Figure 1 - j3.4 fRF = 375MHz 1 - j3.9 fRF = 315MHz 1 - j4.7 P1dBLNA -22 dBm IIP3LNA -12 dBm -80 dBm LO Signal Feedthrough to Antenna Output Impedance fRF = 433MHz ZOUT_LNA NFLNA Normalized to 50Ω 0.12 - j4.4 3 dB _______________________________________________________________________________________ 3 MAX7033 DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (continued) MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LNA IN LOW-GAIN MODE Input Impedance 1dB Compression Point Input-Referred 3rd-Order Intercept ZIN_LNA Normalized to 50Ω (Note 4) fRF = 433MHz 1 - j3.4 fRF = 375MHz 1 - j3.9 fRF = 315MHz 1 - j4.7 P1dBLNA -10 dBm IIP3LNA -7 dBm -80 dBm LO Signal Feedthrough to Antenna Output Impedance Noise Figure ZOUT_LNA Normalized to 50Ω 0.4 3 dB AGC enabled (depends on tank Q) 35 dB NFLNA Voltage-Gain Reduction MIXER Input Impedance ZIN_MIX Input-Referred 3rd-Order Intercept IIP3MIX -18 ZOUT_MIX 330 Ω NFMIX 16 dB Output Impedance Noise Figure Normalized to 50Ω 0.25 - j2.4 fRF = 433MHz, VIRSEL = DVDD Image Rejection (Not Including LNA Tank) LNA/Mixer Voltage Gain dBm 42 fRF = 375MHz, VIRSEL = DVDD / 2 44 fRF = 315MHz, VIRSEL = 0V 44 LNA in high-gain mode 48 LNA in low-gain mode 13 330Ω IF filter load dB dB INTERMEDIATE FREQUENCY (IF) Input Impedance Operating Frequency ZIN_IF fIF Bandpass response 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level AGC Threshold 330 Ω 10.7 MHz 10 MHz ±0.5 dB 80 dB PRFIN < -120dBm 1.15 PRFIN > 0dBm, AGC enabled 2.2 LNA gain from low to high 1.39 LNA gain from high to low 1.98 V V DATA FILTER Maximum Bandwidth 50 kHz 100 kHz DATA SLICER Comparator Bandwidth 4 _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock (Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Maximum Load Capacitance CONDITIONS MIN CLOAD TYP MAX UNITS 10 pF Output High Voltage VDD5 V Output Low Voltage 0 V CRYSTAL OSCILLATOR VXTALSEL = 0V fRF = 433MHz Crystal Frequency (Note 5) 6.6128 VXTALSEL = VDD5 fXTAL fRF = 315MHz 13.2256 VXTALSEL = 0V 4.7547 VXTALSEL = VDD5 9.5094 Crystal Tolerance Input Capacitance From each pin to ground MHz 50 ppm 6.2 pF Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass to AGND with a 1nF capacitor in a noisy environment. Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz) / 64 for XTALSEL = 0V, and (fRF - 10.7MHz) / 32 for XTALSEL = VDD5. Typical Operating Characteristics (Typical Application Circuit , AVDD = DVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) +85°C 5.2 5.0 4.8 4.6 +25°C -40°C MAX7033 toc02 +105°C 6.0 5.5 5.0 +85°C +25°C 4.0 4.4 4.2 6.5 4.5 3.2 3.3 1 fRF = 315MHz 0.1 -40°C 0.01 3.0 3.1 fRF = 433MHz 10 3.5 4.0 3.0 100 BIT-ERROR RATE (%) SUPPLY CURRENT (mA) +105°C SUPPLY CURRENT (mA) 5.8 5.4 7.0 MAX7033 toc01 6.0 5.6 BIT-ERROR RATE vs. PEAK RF INPUT POWER SUPPLY CURRENT vs. RF FREQUENCY MAX7033 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 250 300 350 400 RF FREQUENCY (MHz) 450 500 -130 -128 -126 -124 -122 -120 -118 -116 -114 PEAK RF INPUT POWER (dBm) _______________________________________________________________________________________ 5 MAX7033 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (Typical Application Circuit , AVDD = DVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) 2.2 MAX7033 toc06 2.4 2.0 3.5 2.2 2.5 2.0 1.5 1.8 0.5 -116 RSSI (V) fRF = 433MHz -114 RSSI (V) 1.8 VAC = 0V 1.6 1.6 -0.5 DELTA -118 1.4 -120 -1.5 1.4 fRF = 315MHz RSSI 1.2 -122 1.0 -124 -15 10 35 60 85 -80 -60 -40 -20 0 -90 -70 -50 -30 TEMPERATURE (°C) RF INPUT POWER (dBm) IF INPUT POWER (dBm) LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY IMAGE REJECTION vs. RF FREQUENCY IMAGE REJECTION vs. TEMPERATURE UPPER SIDEBAND 35 IMAGE REJECTION (dB) 45 49dB IMAGE REJECTION 25 LOWER SIDEBAND 15 FROM RFIN TO MIXOUT fRF = 315MHz 5 10 15 20 IF FREQUENCY (MHz) 25 45 40 fRF = 375MHz fRF = 315MHz fRF = 433MHz 30 45.0 fRF = 315MHz 44.5 10 44.0 43.5 43.0 fRF = 375MHz 42.5 42.0 fRF = 433MHz 41.5 35 -5 5 50 -10 MAX7033 toc09 55 55 IMAGE REJECTION (dB) 65 0 -3.5 1.0 -140 -120 -100 110 MAX7033 toc07 -40 -2.5 1.2 MAX7033 toc08 SENSITIVITY (dBm) -112 6 VAC = DVDD 30 41.0 40.5 280 300 320 340 360 380 400 420 440 460 480 RF FREQUENCY (MHz) -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 DELTA (%) IF BANDWIDTH = 280kHz MAX7033 toc05 PEAK RF INPUT POWER 0.2% BER IF BANDWIDTH = 280kHz -110 2.4 MAX7033 toc04 -108 RSSI AND DELTA vs. IF INPUT POWER RSSI vs. RF INPUT POWER SENSITIVITY vs. TEMPERATURE SYSTEM GAIN (dB) MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock NORMALIZED IF GAIN vs. IF FREQUENCY S11 LOG MAGNITUDE PLOT OF RFIN -5 -10 -15 30 -20 WITH INPUT MATCHING 10 500MHz 315MHz 0 -10 200MHz -20 315MHz -36dB -40 -50 -30 0 100 200 300 400 500 600 700 800 900 1000 IF FREQUENCY (MHz) FREQUENCY (MHz) REGULATOR VOLTAGE vs. REGULATOR CURRENT PHASE NOISE vs. OFFSET FREQUENCY 0 MAX7033 toc13 3.3 2.9 -40°C 2.7 +25°C 2.5 2.3 +85°C 2.1 -20 PHASE NOISE (dBc/Hz) 3.1 fRF = 315MHz +105°C -40 -60 -80 -100 -120 1.9 1.7 10 20 30 40 REGULATOR CURRENT (mA) 50 60 fRF = 433MHz -20 -40 -60 -80 -100 -120 -140 0 0 PHASE NOISE (dBc/Hz) 3.5 PHASE NOISE vs. OFFSET FREQUENCY MAX7033 toc15 100 MAX7033 toc14 10 1 REGULATOR VOLTAGE (V) MAX7033 toc12 20 -30 -25 S11 SMITH CHART PLOT OF RFIN MAX7033 toc11 40 S11 MAGNITUDE (dB) 0 NORMALIZED IF GAIN (dB) 50 MAX7033 toc10 5 -140 10 100 1k 10k 100k OFFSET FREQUENCY (Hz) 1M 10M 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX7033 Typical Operating Characteristics (continued) (Typical Application Circuit , AVDD = DVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033 Pin Description PIN 8 TSSOP THIN QFN 1 29 NAME FUNCTION XTAL1 Crystal Input 1 (See the Phase-Locked Loop section) Positive Analog Supply Voltage. For +5V operation, AVDD is connected to an on-chip +3.2V low-dropout regulator. Both AVDD pins must be externally connected to each other. Bypass each pin to AGND with a 0.01µF capacitor as close to the pin as possible (see the Typical Application Circuit). 2, 7 4, 30 AVDD 3 31 LNAIN 4 32 LNASRC 5, 10 2, 7 AGND Low-Noise Amplifier Input (See the Low-Noise Amplifier section) Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set the LNA input impedance (see the Low-Noise Amplifier section). Analog Ground Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (see the LowNoise Amplifier section). 6 3 LNAOUT 8 5 MIXIN1 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT. 9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to AVDD side of the LC tank. 11 8 IRSEL Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = VDD5 to center image rejection at 433MHz. 12 9 MIXOUT 13 10 DGND Digital Ground 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter. 14 11 DVDD Positive Digital Supply Voltage. Connect to AVDD. Bypass to DGND with a 0.01µF capacitor as close to the pin as possible. 15 12 AC Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100kΩ resistor. 16 14 XTALSEL 17 15 IFIN1 1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF capacitor as close to the pin as possible. 18 16 IFIN2 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. 19 17 DFO Data Filter Output 20 18 DSN Negative Data Slicer Input 21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter 22 20 DFFB Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. 23 22 DSP Positive Data Slicer Input 24 23 VDD5 +5V Supply Voltage. For +5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output drives AVDD. 25 24 26 26 Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to select divider ratio of 32. DATAOUT Digital Baseband Data Output PDOUT Peak-Detector Output _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock PIN NAME FUNCTION TSSOP THIN QFN 27 27 SHDN Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a 100kΩ resistor. 28 28 XTAL2 Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal Oscillator section.) — 1, 13, 21, 25 N.C No Connection Functional Diagram LNASRC 4 LNAIN AVDD VDD5 DVDD DGND AGND 3 AC 15 LNAOUT 6 MIXIN1 MIXIN2 8 9 Q IMAGE REJECTION 2, 7 3.2V REG 14 DIVIDE BY 64 VCO PHASE DETECTOR LOOP FILTER 5, 10 28-PIN TSSOP PACKAGE IFIN2 18 IF LIMITING AMPS ∑ 90˚ 24 13 IFIN1 17 0˚ AUTOMATIC GAIN CONTROL LNA MIXOUT 12 IRSEL 11 I MAX7033 RSSI DATA FILTER RDF1 100kΩ RDF2 100kΩ ÷1 ÷2 CRYSTAL DRIVER 16 1 XTALSEL XTAL1 XTAL2 28 DATA SLICER POWERDOWN 27 SHDN 25 DATAOUT Detailed Description The MAX7033 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 33kbps Manchester (66kbps NRZ) can be achieved. The MAX7033 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. Voltage Regulator For operation with a single +3.0V to +3.6V supply voltage, connect AVDD, DVDD, and VDD5 to the supply voltage. 20 23 19 DSN DSP DFO 26 21 22 PDOUT OPP DFFB For operation with a single +4.5V to +5.5V supply voltage, connect VDD5 to the supply voltage. An on-chip voltage regulator drives one of the AV DD pins to approximately +3.2V. For proper operation, DVDD and both AVDD pins must be connected together. Bypass DV DD and both AV DD pins to AGND with 0.01µF capacitors placed as close to the pins as possible. Low-Noise Amplifier The LNA is an nMOS cascode amplifier with off-chip inductive degeneration, with a 3.0dB noise figure and an IIP3 of -12dBm. The gain and noise figures are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. _______________________________________________________________________________________ 9 MAX7033 Pin Description (continued) MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical PC board trace antenna. A nominal value for this inductor with a 50Ω input impedance is 15nH, but is affected by PC board trace. The LC tank filter connected to LNAOUT comprises L3 and C2 (see the Typical Application Circuit). Select L3 and C2 to resonate at the desired RF input frequency. The resonant frequency is given by: fRF = 1 2π L TOTAL × CTOTAL where: LTOTAL = L3 + LPARASITICS. CTOTAL = C2 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PC board traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. Automatic Gain Control When the AC pin is low, the automatic gain-control (AGC) circuit monitors the RSSI output. As the RSSI output reaches 1.98V, which corresponds to RF input level of -62dBm, the AGC switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.39V (approximately -70dBm at RF input) for 1ms. The AGC has a hysteresis of 8dB. With the AGC function, the MAX7033 can reliably produce an ASK output for RF input levels up to 0dBm with modulation depth of 18dB. When the AC pin is high and SHDN goes high, the AGC circuit is disabled and the LNA is always in highgain mode. The AGC function can be resumed by bringing the AC pin low when SHDN is high. The MAX7033 features an AGC lock function that is asserted when the level at the AC pin transitions from low to high while SHDN is high. Locking the AGC locks the LNA in the current gain state. As shown in Figure 1, the AGC lock function can be enabled or disabled as long as the SHDN pin is high. Changing the state of AC when SHDN is low has no effect. Mixer A unique feature of the MAX7033 is the integrated image rejection of the mixer. This device eliminates the need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF fIF). The image-rejection circuit then combines these signals to achieve 44dB of image rejection. Low-side VIH SHDN PIN VIL VIH AC PIN VIL AGC LOCK AGC UNLOCK AGC LOCK AGC ENABLED AGC UNLOCK NO EFFECT NO EFFECT AGC DISABLED NO EFFECT AGC ENABLED Figure 1. AGC Lock Activation Cycles 10 ______________________________________________________________________________________ AGC DISABLED 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Phase-Locked Loop The PLL block contains a phase detector, charge pump, integrated loop filter, VCO, asynchronous 64x clock divider, and crystal oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates a low-side LO. The relationship between the RF, IF, and reference frequencies is given by: f - f fREF = RF IF 32 × M where: M = 1 (VXTALSEL = VDD5) or 2 (VXTALSEL = 0V) To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal. Intermediate Frequency and RSSI The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass-filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB (see the Typical Operating Characteristics). Applications Information Crystal Oscillator The crystal oscillator in the MAX7033 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals Table 1. Component Values for Typical Application Circuit COMPONENT VALUE FOR fRF = 433MHz VALUE FOR fRF = 315MHz DESCRIPTION L1 56nH 120nH TOKO LL1608-FH L2 15nH 15nH Murata LQP11A L3 15nH 27nH Murata LQP11A C1 100pF 100pF 5% C2 2pF 4pF ± 0.1pF C3 100pF 100pF 5% C4 100pF 100pF 5% C5 1500pF 1500pF 10% C6 220pF 220pF 5% C7 470pF 470pF 5% C8 0.47µF 0.47µF 20% C9 220pF 220pF 10% C10 0.01µF 0.01µF 20% C11 0.01µF 0.01µF 20% C12 15pF 15pF Depends on XTAL C13 15pF 15pF Depends on XTAL R1 5.1kΩ 5.1kΩ 5% X1 6.5984MHz 4.7547MHz — X2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series ______________________________________________________________________________________ 11 MAX7033 injection is required due to the on-chip image-rejection architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330Ω; this provides a good match to the off-chip 330Ω ceramic IF filter. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz. VIRSEL = VDD5 / 2 tunes the image rejection to 375MHz, and VIRSEL = VDD5 tunes the image rejection to 433MHz. The IRSEL pin is internally set to VDD5 / 2 (image rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external VDD5 / 2 voltage. MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock designed to operate with higher differential load capacitance always pull the reference frequency higher. For example, a 4.7547MHz crystal designed to operate with a 10pF load capacitance oscillates at 4.7563MHz with the MAX7033, causing the receiver to be tuned to 315.1MHz rather than 315.0MHz, an error of about 100kHz, or 320ppm. In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: C fP = M 2 1 1 6 C × 10 + C C + C CASE LOAD CASE SPEC where: fP is the amount the crystal frequency pulled in ppm. CM is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero. It is possible to use an external reference oscillator in place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive XTAL2 with a signal level of approximately -10dBm. ACcouple XTAL1 to ground with a 1000pF capacitor. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of C5 and C6, use the following equations, along with the coefficients in Table 2: C5 = b a(100k)( π )(fC ) C6 = a 4(100k)( π )(fC ) where fC is the desired 3dB corner frequency. For example, to choose a Butterworth filter response with a corner frequency of 5kHz: C5 = C6 = 1.000 ≈ 450pF (1.414)(100kΩ)(3.14)(5kHz) 1.414 (4)(100kΩ)(3.14)(5kHz) ≈ 225pF Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the Typical Application Circuit. Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data Table 2. Coefficents to Calculate C5 and C6 FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 Data Filter The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 2 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. 12 MAX7033 RSSI RDF1 100kΩ RDF2 100kΩ 22 DFFB 21 OPP 19 DFO C6 C5 Figure 2. Sallen-Key Lowpass Data Filter ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033 filter output. Both comparator inputs are accessible offchip to allow for different methods of generating the slicing threshold, which is applied to the second comparator input. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 3). This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R1 and C4 affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. Note that a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. MAX7033 DATA SLICER 20 DSN 25 DATAOUT 19 DFO 23 DSP R1 C4 Figure 3. Generating Data Slicer Threshold To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise, add hysteresis to the data slicer as shown in Figure 4. MAX7033 DATA SLICER Peak Detector The peak-detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. For faster data slicer response, use the circuit shown in Figure 5. 25 DATAOUT 20 DSN 23 DSP R4 19 DFO R1 R3 R2 C4 *OPTIONAL Layout Considerations A properly designed PC board is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PC board trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all VDD connections. Figure 4. Generating Data Slicer Hysteresis MAX7033 DATA SLICER 25 DATAOUT 20 DSN 23 DSP 19 DFO 26 PDOUT 25kΩ 47nF Figure 5. Using PDOUT for Faster Startup ______________________________________________________________________________________ 13 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033 Typical Application Circuit +3.3V C12 C13 C11 1 RF INPUT 2 C1 +3.3V X1 L1 3 4 L2 5 6 +3.3V 7 L3 C3 8 C2 9 C4 10 C9 11 12 13 14 XTAL1 XTAL2 AVDD SHDN LNAIN PDOUT MAX7033 LNASRC DATAOUT AGND VDD5 LNAOUT DSP AVDD DFFB MIXIN1 OPP MIXIN2 DSN AGND DFO IRSEL IFIN2 MIXOUT IFIN1 DGND XTALSEL DVDD AC 28 TO/FROM µP POWER-DOWN DATA OUT 27 26 25 R2 24 R3 23 22 21 C7 20 19 18 17 R1 16 15 C5 X2 C6 C8 IF FILTER C10 IN OUT GND COMPONENT VALUES IN TABLE 1 Chip Information TRANSISTOR COUNT: 3208 PROCESS: CMOS 14 ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock TSSOP4.40mm.EPS ______________________________________________________________________________________ 15 MAX7033 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) D2 0.15 C A D b C L 0.10 M C A B D2/2 D/2 k 0.15 C B MARKING QFN THIN.EPS MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock XXXXX E/2 E2/2 C L (NE-1) X e E E2 k L DETAIL A PIN # 1 I.D. e PIN # 1 I.D. 0.35x45∞ (ND-1) X e DETAIL B e L1 L C L C L L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- COMMON DIMENSIONS A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 A3 b D E L1 0 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. e k L 0.02 0.05 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 - - - - - - N ND NE 16 4 4 20 5 5 JEDEC WHHB WHHC - 1 2 EXPOSED PAD VARIATIONS PKG. 32L 5x5 16L 5x5 20L 5x5 28L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A1 F - - - 28 7 7 WHHD-1 - - 32 8 8 WHHD-2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. D2 L E2 PKG. CODES MIN. NOM. MAX. MIN. NOM. MAX. ±0.15 T1655-1 T1655-2 T1655N-1 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 3.10 3.20 T2055-2 T2055-3 T2055-4 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.10 3.10 3.20 3.20 3.20 ** ** ** ** T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 ** ** 0.40 DOWN BONDS ALLOWED NO YES NO NO YES NO Y ** NO NO YES YES NO ** ** 0.40 ** ** ** ** ** NO YES Y N NO YES NO NO ** ** ** ** ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- F 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.