www.fairchildsemi.com ML4826 PFC and Dual Output PWM Controller Combo Features General Description • Internally synchronized PFC and PWM in one IC • Low total harmonic distortion • Low ripple current in the storage capacitor between the PFC and PWM sections • Average current, continuous boost, leading edge PFC • High efficiency trailing edge PWM with dual totem-pole outputs • Average line voltage compensation with brown-out control • PFC overvoltage comparator eliminates output “runaway” due to load removal • Current-fed multiplier for improved noise immunity • Overvoltage protection, UVLO, and soft start The ML4826 is a high power controller for power factor corrected, switched mode power supplies. PFC allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specifications. The ML4826 includes circuits for the implementation of a leading edge, average current “boost” type power factor correction and a trailing edge, pulse width modulator (PWM) with dual totem-pole outputs. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brown-out protection. The PWM section can be operated in current or voltage mode at up to 250kHz and includes a duty cycle limit to prevent transformer saturation. Block Diagram 20 11 VEAO VFB VEA - 19 17 1 IEAO AGND POWER FACTOR CORRECTOR OVP + IEA 3.5kΩ - 2.5V VCC VCCZ 2.7V + + 13.5V - + IAC - 2 4 -1V 8V GAIN MODULATOR VRMS S Q R Q S Q R Q VREF 18 + - PFC OUT 3.5kΩ ISENSE 7.5V REFERENCE PFC ILIMIT 15 3 RAMP 1 8 RTCT OSCILLATOR 7 VCC2 RAMP 2 S DUTY CYCLE LIMIT 9 PWM 2 8V VDC 6 14 Q - PGND + VCC SS T 1.5V 16 Q S - 50µA 5 + VFB - 2.5V + Q VIN OK VCC2 PWM 1 1V 8V + R 13 Q PGND DC ILIMIT 12 DC ILIMIT 10 PULSE WIDTH MODULATOR VCCZ UVLO REV. 1.0.5 2/14/02 ML4826 PRODUCT SPECIFICATION Pin Configuration ML4826 20-Pin PDIP (P20) IEAO 1 20 VEAO IAC 2 19 VFB ISENSE 3 18 VREF VRMS 4 17 VCC2 SS 5 16 VCC1 VDC 6 15 PFC OUT RTCT 7 14 PWM 1 RAMP 1 8 13 PWM 2 RAMP 2 9 12 PGND DC ILIMIT 10 11 AGND TOP VIEW Pin Description 2 PIN NAME FUNCTION 1 IEAO 2 IAC 3 ISENSE 4 VRMS 5 SS 6 VDC PWM voltage feedback input 7 RTCT Connection for oscillator frequency setting components 8 RAMP 1 PFC ramp input 9 RAMP 2 When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM input from the PFC output (feedforward ramp) 10 DC ILIMIT PWM current limit comparator input 11 AGND Analog signal ground 12 PGND Return for the PWM totem-pole outputs 13 PWM 2 PWM driver 2 output 14 PWM 1 PWM drive 1 output 15 PFC OUT 16 VCC2 Positive supply for the PWM drive outputs 17 VCC1 Positive supply (connected to an internal shunt regulator). 18 VREF Buffered output for the internal 7.5V reference 19 VFB 20 VEAO PFC transconductance current error amplifier output PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PFC driver output PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output REV. 1.0.5 2/14/02 PRODUCT SPECIFICATION ML4826 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter Min Max. Units 55 mA –3 5 V GND – 0.3 VCCZ + 0.3 V VCC Shunt Regulator Current ISENSE Voltage Voltage on Any Other Pin IREF 20 mA IAC Input Current 10 mA Peak PFC OUT Current, Source or Sink 500 mA Peak PWM OUT Current, Source or Sink 500 mA PFC OUT, PWM 1, PWM 2 Energy Per Cycle 1.5 mJ 150 °C 150 °C Lead Temperature (Soldering, 10 sec) 260 °C Thermal Resistance (θJA) Plastic DIP 67 °C/W Min. Max. Units 0 70 °C Junction Temperature Storage Temperature Range –65 Operating Conditions Parameter Temperature Range ML4826CP2 Electrical Characteristics Unless otherwise specified, ICC = 25mA, RRAMP 1 = RT = 52.3kΩ, CRAMP1 = CT = 180 pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Conditions Min. Typ. Max. Units Voltage Error Amplifier Transconductance 0 VNON INV = VINV, VEAO = 3.75V Feedback Reference Voltage Input Bias Current V 50 85 120 µΩ 2.4 2.5 2.6 V –0.3 –1.0 µA Note 2 Output High Voltage 7 Ω Input Voltage Range 6.0 Output Low Voltage 6.7 0.6 V 1.0 V Source Current ∆VIN = ±0.5V, VOUT = 6V –40 –80 µA Sink Current ∆VIN = ±0.5V, VOUT = 1.5V 40 80 µA 60 75 dB VCCZ – 3V < VCC < VCCZ – 0.5V 60 75 dB Open Loop Gain Power Supply Rejection Ratio Current Error Amplifier Transconductance Input Offset Voltage Input Bias Current REV. 1.0.5 2/14/02 -1.5 VNON INV = VINV, VEAO = 3.75V 130 2 V 310 µΩ ±3 ±15 mV –0.5 –1.0 µA 195 Ω Input Voltage Range 3 ML4826 PRODUCT SPECIFICATION Electrical Characteristics (continued) Unless otherwise specified, ICC = 25mA, RRAMP 1 = RT = 52.3kΩ, CRAMP1 = CT = 180 pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Conditions Output High Voltage Min. Typ. 6.0 6.7 Output Low Voltage 0.6 Max. Units V 1.0 V Source Current ∆VIN = ±0.5V, VOUT = 6V –40 –90 µA Sink Current ∆VIN = ±0.5V, VOUT = 1.5V 40 90 µA 60 75 dB 60 75 dB Threshold Voltage 2.6 2.7 2.8 V Hysteresis 80 115 150 mV Threshold Voltage –0.8 –1.0 –1.15 V ∆(PFC ILIMIT - Gain Modulator Output) 100 190 Open Loop Gain Power Supply Rejection Ratio VCCZ – 3V < VCC < VCCZ – 0.5V OVP Comparator PFC ILIMIT Comparator Delay to Output mV 150 300 ns 1.0 1.1 V Input Bias Current ±0.3 ±1 µA Delay to Output 150 300 ns DC ILIMIT comparator Threshold Voltage 0.9 VIN OK Comparator Threshold Voltage 2.4 2.5 2.6 V Hysteresis 0.8 1.0 1.2 V Gain Modulator Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V 0.36 0.55 0.66 IAC = 50µA, VRMS = 1.2V, VFB = 0V 1.20 1.80 2.24 IAC = 50µA, VRMS = 1.8V, VFB = 0V 0.55 0.80 1.01 IAC = 100µA, VRMS = 3.3V, VFB = 0V 0.14 0.20 0.26 Bandwidth IAC = 100µA 10 MHz Output Voltage IAC = 250µA, VRMS = 1.15V, VFB = 0V 0.72 0.82 0.95 V Initial Accuracy TA = 25°C 180 190 200 kHz Voltage Stability VCCZ – 3V < VCC < VCCZ – 0.5V Oscillator Temperature Stability Total Variation Line, Temp 1 % 2 % 170 Ramp Valley to Peak Voltage 210 V ns Dead Time PFC Only 250 500 CT Discharge Current VRAMP 1 = 0V, V(RTCT) = 2.5V 4.5 7.5 RAMP 1 Discharge Current kHz 2.5 9.5 5 mA mA Reference 4 Output Voltage TA = 25°C, I(VREF) = 1mA Line Regulation VCCZ – 3V < VCC < VCCZ – 0.5V 7.4 7.5 7.6 V 2 10 mV REV. 1.0.5 2/14/02 PRODUCT SPECIFICATION ML4826 Electrical Characteristics (continued) Unless otherwise specified, ICC = 25mA, RRAMP 1 = RT = 52.3kΩ, CRAMP1 = CT = 180 pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Conditions Min. Typ. 7 Max. Units Load Regulation 1mA < I(VREF) < 20mA Total Variation Line, Load, Temp Long Term Stability TJ = 125˚C, 1000 Hours Minimum Duty Cycle ML4826-2, VIEAO > 5.7V Maximum Duty Cycle VIEAO < 1.2V Output Low Voltage IOUT = –20mA 0.4 0.8 V IOUT = –50mA 0.6 3.0 V 0.7 1.5 V 7.25 5 20 mV 7.65 V 25 mV 0 % PFC 90 IOUT = 10mA, VCC = 8V Output High Voltage Rise/Fall Time 95 % IOUT = 20mA 9.5 10.5 V IOUT = 50mA 9.0 10 V 50 ns CL = 1000pF PWM Duty Cycle Range Output Low Voltage Output High Voltage Rise/Fall Time 0-48 0-50 % IOUT = –20mA 0-47 0.4 0.8 V IOUT = –50mA 0.6 3.0 V IOUT = 10mA, VCC = 8V 0.7 1.5 V IOUT = 20mA 9.5 IOUT = 50mA 9.0 CL = 1000pF 10.5 V 10 V 50 ns Supply Shunt Regulator Voltage (VCCZ) 12.8 13.5 14.2 V ±150 ±300 mV 14.6 V VCCZ Load Regulation 25mA < ICC < 55mA VCCZ Total Variation Load, temp Start-up Current VCC = 11.2V, CL = 0 0.7 1.1 mA Operating Current VCC < VCCZ – 0.5V, CL = 0 22 28 mA 12.4 Undervoltage Lockout Threshold 12 13 14 V Undervoltage Lockout Hysteresis 2.65 3.0 3.35 V Notes: 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1. REV. 1.0.5 2/14/02 5 ML4826 PRODUCT SPECIFICATION 250 200 200 Ω Transconductance (µ ) 250 Ω Transconductance (µ ) Typical Performance Characteristics 150 100 150 100 50 50 0 -500 0 0 1 3 2 5 4 0 500 IEA Input Voltage (mV) VFB (V) Voltage Error Amplifier (VEA) Transconductance (gm) Current Error Amplifier (IEA) Transconductance (gm) Variable Gain Block Constant - K 400 300 200 100 0 0 1 2 3 4 5 VRMS (mV) Variable Gain Control Transfer Characteristic 20 VFB 19 VEA - 17 1 VCC IEAO VEAO OVP + IEA 3.5kΩ - 2.5V ISENSE 13.5V - -1V 8V GAIN MODULATOR 7.5V REFERENCE - + 2 4 2.7V + + IAC VRMS VCCZ S Q R Q S Q R Q VREF 18 + - PFC OUT 3.5kΩ PFC ILIMIT 15 3 RAMP 1 8 RTCT 7 OSCILLATOR x2 VCCZ UVLO Figure 1. PFC Section Block Diagram. 6 REV. 1.0.5 2/14/02 ML4826 Functional Description The ML4826 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailingedge duty cycle modulation, while the PFC uses leadingedge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4826 runs at twice the frequency of the PFC, which allows the use of small PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components. In addition to power factor correction, a number of protection features have been built into the ML4826. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and undervoltage lockout. Power Factor Correction Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of a most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect which occurs on the input filter capacitor in such a supply causes brief highamplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with, and proportional to, the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4826 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line agrees with the instanta7 PRODUCT SPECIFICATION neous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level) from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4826 PFC is of the current-averaging type, no slope compensation is required. PFC Section Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4826. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over to limit power dissipation of the circuit components under heavy brown-out conditions). The relationship between VRMS and gain is designated as K, and is illustrated in the Typical Performance Characteristics. 3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. REV. 1.0.5 2/14/02 ML4826 PRODUCT SPECIFICATION The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: I AC × VEAO - × 1V I GAINMOD ≅ ------------------------------2 V RMS More exactly, the output current of the gain modulator is given by: I GAINMOD ≅ K × ( VEAO – 1.5V ) × I AC (1) pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. Overvoltage Protection The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.7V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 125mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.58V. The VFB should be set at a level where the active and passive external power components and the ML4826 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. VREF where K is in units of V-1. Note that the output current of the gain modulator is limited to ≅ 200µA. PFC OUTPUT 20 Current Error Amplifier The current error amplifier’s output controls the PFC duty cycle to keep the current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE ≅ VSENSE/3.5kΩ). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feed- back loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this 8 VEAO VFB 19 11 1 IEAO AGND VEA - IEA - 2.5V + + + IAC - 2 VRMS 4 GAIN MODULATOR ISENSE 3 Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 3 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the ML4826’s voltage error amplifier has a specially shaped REV. 1.0.5 2/14/02 PRODUCT SPECIFICATION ML4826 nonlinearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This increases the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC. Main Oscillator (RTCT) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: f OSC 1 = --------------------------------------------------t RAMP + t DEADTIME (2) The deadtime of the oscillator is derived from the following equation: 2.5V t DEADTIME = ------------------ × C T = 490 × C T 5.1mA = 1.1 × R RAMP1 × C RAMP1 t RAMP = C T × R T × 0.51 = 1 × 10 Solving for RT x CT yields 2 x 10-4. Selecting standard components values, CT = 1000pF, and RT = 8.63kΩ. The deadtime of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator deadtime, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. PFC RAMP (RAMP1) The intersection of RAMP1 and the boost current error amplifier output controls the PFC pulse width. RAMP1 can be generated in a similar fashion to the RTCT ramp. The current error amplifier maximum output voltage has a minimum of 6V. The peak value of RAMP1 should not exceed that voltage. Assuming a maximum voltage of 5V for RAMP1, Equation 6 describes the RAMP1 time. With a 100kHz PFC frequency, the resistor tied to VREF, and a 150pF capacitor, Equation 7 solves for the RAMP1 resistor. V REF t RAMP1 = C RAMP1 × R RAMP1 × In --------------------------- V REF – 5V t RAMP1 10µs - = -------------------------------- = 60kΩ R RAMP1 = ----------------------------------1.1 × C RAMP1 1.1 × 150pF VREF 60kΩ The ramp of the oscillator may be determined using: f OSC (4) (5) For proper reset of internal circuits during dead time, values of 1000pF or greater are suggested for CT. EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: V REF t RAMP1 = C RAMP1 × R RAMP1 × In --------------------------- V REF – 5V REV. 1.0.5 2/14/02 ML4826 RAMP1 150pF The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: 1 = ---------------t RAMP (7) (3) 1 f OSC = 200kHz = ---------------t RAMP t RAMP (6) = 1.1 × R RAMP1 × C RAMP1 at VREF = 7.5V: V REF – 1.25 = C T × R T × In ------------------------------- V REF – 3.75 –5 Figure 3. PMW SECTION Pulse Width Modulator The PWM section of the ML4826 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing (at twice the PFC frequency in the ML4826-2). The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or 9 ML4826 current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycle-bycycle current limiting, is typically connected to RAMP 2 in such applications. For voltage-mode operation or certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input would be used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4826, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.5V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start commences. RAMP2 The RAMP2 input is compared to the feedback voltage (VDC) to set the PWM pulse width. In voltage mode it can be generated using the same method used for the RTCT input. In current mode the primary current sense and slope compensation are fed into the RAMP2 input. Peak current mode control with duty cycles greater than 50% requires slope compensation for stability. Figure 4 displays the method used for the required slope compensation. The example shown adds the slope compensation signal to the current sense signal. Alternatively, the slope compensation signal can also be subtracted form the feedback signal (VDC). In setting up the slope compensation first determine the down slope in the output inductor current. To determine the actual signal required at the RAMP2 input, reflect 1/2 of the inductor downslope through the main transformer, current sense transformer to the ramp input. Internal to the IC is a 1.5V offset in series with the RAMP2 input. In the example show the positive input to the PWM comparator is developed from VREF (7.5V), this limits the RAMP2 input (current sense and slope compensation) to 6 Volts peak. The composite waveform feeding the RAMP2 10 PRODUCT SPECIFICATION pin for the PWM consists of the reflected output current signal along with the transformer magnetizing current and the slope compensation signal. Equation 8 describes the composite signal feeding RAMP2, consisting of the primary current of the main transformer and the slope compensation. Equation 9 solves for the required slope compensation peak voltage. 1 V OUT N S 1 V RAMP2 = I PRI + --- × -------------- × ------- × T S × ---------- ≤ V FB – 1.5V (8) L N 2 n S CT V SC 1 V OUT N S R SENSE 471Ω 1 48V 14 = --- × ----------------- × -------- × T × -------------------------- = --- × --------------- × ------ × 5µ sec --------------- = 2.2V S 200 L N n 2 20µH 90 2 P CT (9) Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 50µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.5V. Start-up delay can be programmed by the following equation: 50µA C SS = t DELAY × -------------1.5V (10) where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: 50µA C SS = 5ms × -------------- = 167nF 1.5V (11) Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0µF soft start capacitor will allow time for VFB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. VCC The ML4826 is a current-fed part. It has an internal shunt voltage regulator, which is designed to regulate the voltage internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at the PWM OUT and PFC OUT outputs. It is important to limit the current through the part to avoid overheating or destroying the part. REV. 1.0.5 2/14/02 PRODUCT SPECIFICATION ML4826 17 VCC 18 VREF Q14 PN2222 4 x IN4148 ISENSE x Former 7 RTCT R21 8.63kΩ D1 T3 200:1 9 C26 220pF R16 471Ω C11 1000pF 1.5V RAMP2 PWM CMP – + R40 47.0kΩ 11 AGND 1V DC ILIMIT – R13 2.2kΩ U2 10 R38 10.0kΩ 6 DC ILIMIT + VDC Figure 4. Slope Compensation and Current Sense There are a number of different ways to supply VCC to the ML4826. The method suggested in Figure 5, is one which keeps the ML4826 ICC current to a minimum, and allows for a loosely regulated bootstrap winding. By feeding external gate drive components from the base of Q1, the constant current source does not have to account for variations in the gate drive current. This helps to keep the maximum ICC of the ML4826 to a minimum. Also, the current available to charge the bootstrap capacitor from the bootstrap winding is not limited by the constant current source. The circuit guarantees that the maximum operating current is available at all times and minimizes the worst case power dissipation in the IC. Other methods such as a simple series resistor are possible, but can very easily lead to excessive ICC current in the ML4826. Figures 6 and 7 show other possible methods for feeding VCC. Leading/Trailing Modulation Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the REV. 1.0.5 2/14/02 level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 8 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 9 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. 11 ML4826 PRODUCT SPECIFICATION 20V VBIAS RECTIFIED VAC 22kΩ T1 Q2 MJE200 39kΩ VCC 1µF ML4826 Q1 PN2222 RTN 18Ω 1500µF VCC ML4826 Figure 6. GATE DRIVE 1µF RTN VBIAS Figure 5. VCC Bias Circuitry VCC ML4826 RTN Figure 7. 12 REV. 1.0.5 2/14/02 PRODUCT SPECIFICATION ML4826 SW2 L1 I3 I2 I1 + I4 VIN RL SW1 DC C1 RAMP VEAO REF U3 + EA – TIME DFF + – RAMP OSC R Q D U2 Q CLK U1 CLK U4 VSW1 TIME Figure 8. Typical Trailing Edge Control Scheme. SW2 L1 I2 I1 + I3 I4 VIN RL SW1 DC RAMP C1 VEAO REF U3 + EA – RAMP OSC U4 CLK VEAO + – CMP U1 TIME DFF R Q D U2 Q CLK VSW1 TIME Figure 9. Typical Leading Edge Control Scheme. REV. 1.0.5 2/14/02 13 14 C103 2.2nF R8 10Ω BR2 4x1N4148 T3 200:1 R112 471Ω C114 220pF R115 R114 8.63kΩ 52.3kΩ C113 C112 150pF 1nF C101 470nF R17 500kΩ R105 10kΩ R101 10.2kΩ C116 1.0µF D5 MUR860 FERRITE BEAD IN B TC4427 VFB PWM 2 P GND RAMP 2 DC ILIMIT A GND PWM 1 RAMP 1 PFC OUT VCC2 VCC RTCT VDC SS VRMS VREF IAC ISENSE VEAO IEAO C105 100pF R116 10kΩ IN A NC VS RTN OUT B VS OUT A NC R110 2.37kΩ Q8 CR4 FQP9N50 1N4747 R10 10kΩ D9 1N5818 R11 10Ω R113 47kΩ C106 3.3nF C3 1µF D8 1N5818 R6 10Ω R15 100mΩ 5W R1 10kΩ Q7 FQP9N50 L1 420µH D1 1N4747 F1 8A FERRITE BEAD R16 500kΩ R102 100kΩ 1N4148 Q104 PN2222 C102 100nF R19 453kΩ R18 453kΩ R103 100Ω GBU6J 6A, 600V R2 R7 470kΩ 470kΩ C2 470nF X AC INPUT 85 TO 265VAC C110 1µF C109 1nF R12 381kΩ D105 1N5818 R46 200Ω Q5 PN2907 Q3 PN2222 R21 200Ω R34 10Ω Q2 PN2222 R3 18Ω Q1 MJE200 R23 2.2kΩ C5 100µF R31 150Ω C8 1nF C9 C16 1µF 1µF T1 D16 1N5818 T2 T1 T1 C104 1nF R104 2.2kΩ R39 220Ω R40 220Ω C18 470pF C17 470pF R26 10kΩ D25 EGP20J D15 EGP20J D25 EGP20J D24 EGP20J R25 10Ω D21B L2 20µH D21A MBR20100CT-ND T1 R38 10kΩ Q8 FQP9N50 D10 1N4747 D26 1N5818 Q9 PN2907 R29 10Ω D20 1N5818 Q1 FQP9N50 D17A Q11 1N4747 PN2907 D17B 1N4747 R41 10Ω Q12 PN2222 D12 1N5819 R44 200Ω D19 1N5819 C4 3300µF Q4 2N2907 R20 200Ω D104 1N5818 C111 1µF R106 225kΩ C108 680nF C107 66nF R14B 39kΩ 2W R14A 39kΩ 2W C21 47nF Y T2 C1 330µF C15 4.7µF TL431 C7 1nF C6 R22 3.3kΩ 100nF R28 330Ω D13 20V R36 10Ω C14 820µF C13 820µF L3 100nH R33 10kΩ R30 10Ω Q10 D23B PN2907 1N4747 D23A 1N4747 R42 10Ω R27 1kΩ R32 2.37kΩ C10 10nF R45 20kΩ 2W C11 1µF C12 1µF R24 200Ω D11 1N5819 R37 200Ω D18 1N5819 R35 43.2kΩ C20 C19 100nF 100nF Q6 D14 PN2907 1N4747 Q7 FQP9N50 D27 1N5818 T1 R43 10kΩ Q2 FQP9N50 D22 1N5818 RTN 48VDC T2 ML4826 PRODUCT SPECIFICATION Figure 10. 48V 300W Power Factor Corrected Power Supply REV. 1.0.5 2/14/02 PRODUCT SPECIFICATION ML4826 Mechanical Dimensions inches (millimeters) Package: P20 20-Pin PDIP 1.010 - 1.035 (25.65 - 26.29) 20 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 0.060 MIN (1.52 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) REV. 1.0.5 2/14/02 0.100 BSC (2.54 BSC) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) 15 ML4826 PRODUCT SPECIFICATION Ordering Information Part Number PWM Frequency Temperature Range Package ML4826CP2 2 x PFC 0°C to 70°C 20-Pin PDIP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 2/14/02 0.0m 003 Stock#DS30004826 © 2001 Fairchild Semiconductor Corporation