19-0154; Rev 2; 11/05 Nonvolatile RAM Controller The MXD1210 nonvolatile RAM controller is a very lowpower CMOS circuit that converts standard (volatile) CMOS RAM into nonvolatile memory. It also continually monitors the power supply to provide RAM write protection when power to the RAM is in a marginal (out-of-tolerance) condition. When the power supply begins to fail, the RAM is write-protected, and the device switches to battery-backup mode. Applications Microprocessor Systems Features ♦ Battery Backup ♦ Memory Write Protection ♦ 230µA Operating Mode Quiescent Current ♦ 2nA Backup Mode Quiescent Current ♦ Battery Freshness Seal ♦ Optional Redundant Battery ♦ Low Forward-Voltage Drop on VCC Supply Switch ♦ 5% or 10% Power-Fail Detection Options ♦ Tests Battery Condition During Power-Up Computers ♦ 8-Pin SO Available Embedded Systems Ordering Information Pin Configurations TOP VIEW VCCO 1 8 VBATT1 2 VCCI 7 VBATT2 3 6 CEO GND 4 5 CE MXD1210 TOL DIP/SO TEMP RANGE PIN-PACKAGE MXD1210C/D PART 0°C to +70°C Dice* MXD1210CPA 0°C to +70°C 8 PDIP MXD1210CSA 0°C to +70°C 8 SO MXD1210CWE 0°C to +70°C 16 Wide SO MXD1210EPA -40°C to +85°C MXD1210ESA -40°C to +85°C 8 PDIP 8 SO MXD1210EWE -40°C to +85°C 16 Wide SO MXD1210MJA -55°C to +125°C 8 CERDIP *Contact factory for dice specifications. Devices in PDIP and SO packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. Typical Operating Circuit +5V N.C. 1 16 N.C. VCCO 2 15 VCCI N.C. 3 14 N.C. VBATT1 4 MXD1210 13 VBATT2 N.C. 5 12 N.C. TOL 6 11 CEO N.C. 7 10 N.C. GND 8 9 CE VCCI VCCO 1 8 2 VBATT1 VCC MXD1210 CE FROM DECODER 7 5 6 4 3 VBATT2 CMOS RAM CE GND WIDE SO ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MXD1210 General Description MXD1210 Nonvolatile RAM Controller ABSOLUTE MAXIMUM RATINGS 8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW Operating Temperature Range C Suffix.................................................................0°C to +70°C E Suffix ..............................................................-40°C to +85°C M Suffix ...........................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C VCCI to GND ..........................................................-0.3V to +7.0V VBATT1 to GND.....................................................-0.3V to +7.0V VBATT2 to GND.....................................................-0.3V to +7.0V VCCO to GND ................................................-0.3V to (VS + 0.3V) (VS = greater of VCCI, VBATT1, VBATT2) Digital Input and Output Voltages to GND.....................................-0.3V to (VCCI + 0.3V) Continuous Power Dissipation (TA = +70°C) 8-Pin PDIP (derate 9.09mW/°C above +70°C)..............727mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Battery Voltage SYMBOL VCCI CONDITIONS MIN TYP TOL = GND 4.75 5.50 TOL = VCCO 4.50 5.50 VIH 2.2 1 or 2 batteries (Note 1) UNITS V V VIL VBATT1 VBATT2 MAX 2.0 0.8 V 4.0 V ELECTRICAL CHARACTERISTICS—Normal Supply Mode, TOL = VCCO (VCCI = +4.75V to +5.5V, TOL = GND; or VCCI = +4.5V to +5.5V, TOL = VCCO; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Supply Current Output Supply Voltage SYMBOL ICCI VCCO CONDITIONS MIN VCCO, CEO open, VBATT1 = VBATT2 = 3V ICCO1 = 80mA (Note 2) MXD1210C VCCI 0.20 MXD1210E VCCI 0.21 MXD1210M VCCI 0.25 TYP MAX UNITS 0.23 0.5 mA V MXD1210C Output Supply Current ICCO VCCI - VCCO ≤ 0.2V (Note 2) 80 MXD1210E 0.23 75 MXD1210M 0.23 65 mA Input Leakage Current IIL ±1.0 µA Output Leakage Current IOL ±1.0 µA High-Level Output Voltage VOH IOH = -1mA Low-Level Output Voltage VOL IOL = 4mA VCCI Trip Point 2 VCCTP 2.4 V 0.4 TOL = GND 4.50 4.74 TOL = VCCO 4.25 4.49 _______________________________________________________________________________________ V V Nonvolatile RAM Controller (VCCI < VBATT, positive edge rate at VBATT1, VBATT2 > 0.1V/µs, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MXD1210C/E Quiescent Current (Note 1) IBATT VCCO, CEO open, VCCI = 0V Output Supply Current ICCO2 VBATT - VCCO ≤ 0.2V (Notes 3, 4) CEO Output Voltage VO MIN TYP MAX 2 100 nA 5 µA 300 µA MXD1210M VBATT 0.2 Output open UNITS V CAPACITANCE (TA = TMIN to TMAX, unless otherwise noted.) (Note 5) PARAMETER Input Capacitance Output Capacitance SYMBOL MAX UNITS CIN CONDITIONS MIN TYP 5 pF COUT 7 pF VCC POWER TIMING CHARACTERISTICS (VCCI = +4.75V to +5.5V, TOL = GND; or VCCI = +4.5V to +5.5V, TOL = VCCO, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS CE Propagation Delay tPD RL = 1kΩ, CL = 50pF CE High to Power-Fail tPF (Note 5) MIN TYP MAX MXD1210C 5 10 20 MXD1210E 5 10 22 MXD1210M 5 10 25 0 UNITS ns ns TIMING CHARACTERISTICS (VCCI < +4.75V to +5.5V, TOL = GND; or VCCI < +4.5V, TOL = VCCO, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Recovery at Power-Up VCC Slew-Rate Power-Down SYMBOL CONDITIONS MIN TYP MAX UNITS 2 5 20 ms tF To out-of-tolerance condition 300 tFB Tolerance to battery power 10 tREC VCC Slew-Rate Power-Up tR CE Pulse Width tCE Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: µs 0 (Note 6) µs 1.5 µs Only one battery input is required. Unused battery inputs must be grounded. ICCO1 is the maximum average load current the MXD1210 can supply to the memories. ICCO2 is the maximum average load current the MXD1210 can supply to the memories in battery-backup mode. CEO can sustain leakage current only in battery-backup mode. Guaranteed by design. tCE max must be met to ensure data integrity on power loss. _______________________________________________________________________________________ 3 MXD1210 ELECTRICAL CHARACTERISTICS—Battery-Backup Mode Nonvolatile RAM Controller MXD1210 Pin Description PIN NAME FUNCTION 8-PIN PDIP/SO 1 16-PIN WIDE SO 2 2 4 3 6 TOL Tolerance Select Pin 4 8 GND Ground 5 9 CE 6 11 CEO 7 13 VBATT2 8 15 VCCI 5V Power Supply to Chip — 1, 3, 5, 7, 10, 12, 14, 16 N.C. No Connection. Not internally connected. VCCO VBATT1 Backed-Up Supply to RAM Battery 1 Positive Connection Chip-Enable Input Chip-Enable Output Battery 2 Positive Connection VCCI P VCCO VBATT1 P P FRESHNESSSEAL MODE VBATT2 N P GND BATTERY SELECT GND MXD1210 BATTERY TEST VOLTAGE LEVEL DETECTION CE CEO CONTROL TOL Figure 1. Block Diagram 4 _______________________________________________________________________________________ CEO Nonvolatile RAM Controller Main Functions The MXD1210 executes five main functions to perform reliable RAM operation and battery backup (see the Typical Operating Circuit and Figure 1): 1) RAM Power-Supply Switch: The switch directs power to the RAM from the incoming supply or from the selected battery, whichever is at the greater voltage. The switch control uses the same criterion to direct power to MXD1210 internal circuitry. 2) Power-Failure Detection: The write-protection function is enabled when a power failure is detected. The power-failure detection range depends on the state of the TOL pin as follows: CONDITION VCCTP RANGE (V) TOL = GND 4.75 to 4.50 TOL = VCCO 4.50 to 4.25 Power-failure detection is independent of the battery-backup function and precedes it sequentially as the power-supply voltage drops during a typical power failure. 3) Write Protection: This holds the chip-enable output (CEO) to within 0.2V of VCCI or of the selected battery, whichever is greater. If the chip-enable input (CE) is low (active) when power failure is detected, then CEO is held low until CE is brought high, at which time CEO is gated high for the duration of the power failure. The preceding sequence completes the current RD/WR cycle, preventing data corruption if the RAM access is a WR cycle. 4) Battery Redundancy: A second battery is optional. When two batteries are connected, the stronger battery is selected to provide RAM backup and to power the MXD1210. The battery-selection circuitry remains active while in the battery-backup mode, selecting the stronger bat- tery and isolating the weaker one. The batteryselection activity is transparent to the user and the system. If only one battery is connected, the second battery input should be grounded. 5) Battery-Status Warning: This notifies the system when the stronger of the two batteries measures ≤ 2.0V. Each time the MXD1210 is repowered (VCCI > VCCTP) after detecting a power failure, the battery voltage is measured. If the battery in use is low, following the MXD1210 recovery period, the device issues a warning to the system by inhibiting the second memory cycle. The sequence is as follows: First access: read memory location n, loc(n) = x Second access: write memory location n, loc(n) = complement (x) Third access: read memory location n, loc(n) = ? If the third access (read) is complement (x), then the battery is good; otherwise the battery is not good. Return to loc(n) = x following the test sequence. Freshness-Seal Mode The freshness-seal mode relates to battery longevity during storage rather than directly to battery backup. This mode is activated when the first battery is connected, and is defeated when the voltage at VCCI first exceeds VCCTP. In the freshness-seal mode, both batteries are isolated from the system; that is, no current is drained from either battery, and the RAM is not powered by either battery. This means that batteries can be installed and the system can be held in inventory without battery discharge. The positive edge rate at VBATT1 and VBATT2 should exceed 0.1V/µs. The batteries will maintain their full shelf life while installed in the system. Battery Backup The Typical Operating Circuit shows the MXD1210 connected to write-protect the RAM when VCC is less than 4.75V, and to provide battery backup to the supply. _______________________________________________________________________________________ 5 MXD1210 Detailed Description MXD1210 Nonvolatile RAM Controller tCE CE VIL VIH CE VIH tPF tPD VBATT - 0.2V VIH CEO VIH VBATT - 0.2V tCE VIL CEO tF tPD tREC VCCI 4.75V 4.75V 4.5V 4.25V 4.5V 4.25V 3V VCCI tR tFB Figure 2. Power-Up Timing Diagram 6 Figure 3. Power-Down Timing Diagram _______________________________________________________________________________________ Nonvolatile RAM Controller MXD1210 Chip Topography VCCI VBATT2 VCCO VBATT1 0.121" (3.073mm) CEO TOL CE GND 0.080" (2.032mm) TRANSISTOR COUNT: 1436; LEAVE SUBSTRATE UNCONNECTED. _______________________________________________________________________________________ 7 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) DIM A A1 B C e E H L N E H INCHES MILLIMETERS MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050 MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 SOICN .EPS MXD1210 Nonvolatile RAM Controller 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D MIN 0.189 0.337 0.386 MAX 0.197 0.344 0.394 MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC D A B e C 0∞-8∞ A1 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .150" SOIC APPROVAL DOCUMENT CONTROL NO. 21-0041 8 _______________________________________________________________________________________ REV. B 1 1 Nonvolatile RAM Controller PDIPN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MXD1210 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)