Revised March 1999 74VHC393 Dual 4-Bit Binary Counter General Description The VHC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It contains two independent counter circuits in one package, so that counting or frequency division of 8 binary bits can be achieved with one IC. This device changes state on the negative going transition of the CLOCK pulse. The counter can be reset to “0” (Q0–Q3 = “L”) by a HIGH at the CLEAR input regardless of other inputs. age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: fMAX = 170 MHz (typ) at TA = 25°C ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Pin and function compatible with 74HC393 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- Ordering Code: Order Number Package Number 74VHC393M 74VHC393SJ 74VHC393MTC 74VHC393N M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names CLR1, CLR2 © 1999 Fairchild Semiconductor Corporation Description Clear Inputs CP1, CP2 Clock Pulse Inputs QA, QB, QC, QD Outputs DS011571.prf www.fairchildsemi.com 74VHC393 Dual 4-Bit Binary Counter March 1993 74VHC393 Truth Table Inputs Outputs CP CLR QA QB QC QD X H L L L L L Count Up L No Change X: Don’t Care System Diagram Timing Chart www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC/GND Current (ICC) ±75 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL VCC (V) TA = 25°C Min Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 Conditions V 3.0 − 5.5 Output Voltage Units V VIN = V IH IOH = −50 µA V or VIL IOH = −4 mA V IOH = −8 mA VIN = V IH IOL = 50 µA LOW Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND IIN Input Leakage Current ICC Quiescent Supply Current 3 V V or VIL IOL = 4 mA IOL = 8 mA www.fairchildsemi.com 74VHC393 Absolute Maximum Ratings(Note 1) 74VHC393 AC Electrical Characteristics Symbol Parameter tPLH Propagation tPHL Delay Time Propagation tPHL Delay Time 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 (CP -QB) tPLH Propagation tPHL Delay Time 3.3 ± 0.3 5.0 ± 0.5 (CP -QC) tPLH Propagation tPHL Delay Time 3.3 ± 0.3 5.0 ± 0.5 (CP -QD) tPLH Propagation tPHL Delay Time 3.3 ± 0.3 5.0 ± 0.5 (CLR-Qn) fMAX TA = 25°C Min 3.3 ± 0.3 (CP -QA) tPLH V CC (V) Maximum TA = −40°C to +85°C Typ Max Min Max 8.6 13.2 1.0 15.5 11.1 16.7 1.0 19.0 5.8 8.5 1.0 10.0 7.3 10.5 1.0 12.0 10.2 15.8 1.0 18.5 12.7 19.3 1.0 22.0 6.8 9.8 1.0 11.5 8.3 11.8 1.0 13.5 11.7 18.0 1.0 21.0 14.2 21.5 1.0 24.5 7.7 11.2 1.0 13.0 9.2 13.2 1.0 15.0 13.0 19.7 1.0 23.0 15.5 23.2 1.0 26.5 8.5 12.5 1.0 14.5 10.0 14.5 1.0 16.5 7.9 12.3 1.0 14.5 10.4 15.8 1.0 18.0 5.4 8.1 1.0 9.5 6.9 10.1 1.0 11.5 3.3 ± 0.3 75 45 65 35 5.0 ± 0.5 125 170 105 85 115 75 Clock 120 CIN Input Capacitance 4 CPD Power Dissipation 23 Units Conditions CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF 65 CL = 50 pF MHz CL = 15 pF CL = 50 pF 10 10 pF VCC = Open pF (Note 3) Capacitance Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average operating current can be obtained by the equation: ICC(opr.) = CPD*VCC*fIN + ICC/2 (per Counter) AC Operating Requirements Symbol Parameter TA = 25°C VCC (V) Typ T A = − 40°C to +85°C Guaranteed Minimum tW(L) Minimum Pulse 3.3 ± 0.3 5.0 5.0 tW(H) Width (CP) 5.0 ± 0.5 5.0 5.0 tW(H) Minimum Pulse 3.3 ± 0.3 5.0 5.0 Width (CLR) 5.0 ± 0.5 5.0 5.0 Minimum Removal 3.3 ± 0.3 5.0 5.0 Time 5.0 ± 0.5 4.0 4.0 tREM www.fairchildsemi.com 4 Units ns ns ns 74VHC393 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74VHC393 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC393 Dual 4-Bit Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued)