July 1999 FDG6304P Dual P-Channel, Digital FET General Description Features -25 V, -0.41 A continuous, -1.5 A peak. RDS(ON) = 1.1 Ω @ VGS= -4.5 V, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SuperSOTTM-6 SOT-23 SC70-6 D1 G2 SO-8 SuperSOTTM-8 SOT-223 S2 .04 S1 SC70-6 G1 D2 1 or 4 * 6 or 3 2 or 5 5 or 2 3 or 6 4 or 1 * *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter FDG6304P Units VDSS Drain-Source Voltage -25 V VGSS Gate-Source Voltage -8 V ID Drain/Output Current - Continuous -0.41 A - Pulsed -1.5 PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range ESD Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100 pF / 1500 Ω) (Note 1) 0.3 W -55 to 150 °C 6.0 kV 415 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1) FDG6304P Rev.E1 Electrical Characteristics (TA = 25 OC unless otherwise noted) Symbol Parameter Conditions Min -25 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25oC IDSS Zero Gate Voltage Drain Current VDS = -20 V, VGS = 0 V V TJ = 55°C IGSS Gate - Body Leakage Current mV / oC -22 VGS = -8 V, VDS = 0 V -1 µA -10 µA -100 nA ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA ∆VGS(th)/∆TJ Gate Threshold Voltage Temp.Coefficient ID = -250 µA, Referenced to 25oC -0.65 RDS(ON) Static Drain-Source On-Resistance VGS = -4.5 V, ID = -0.41 A -0.82 -1.5 TJ =125°C VGS = -2.7 V, ID = -0.25 A V mV / oC 2 0.85 1.1 1.2 1.9 1.15 1.5 -1.5 Ω ID(ON) On-State Drain Current VGS = -4.5 V, VDS = -5 V A gFS Forward Transconductance VDS = -5 V, ID = -0.41 A 0.9 S VDS = 10 V, VGS = 0 V, f = 1.0 MHz 62 pF 34 pF 10 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -5 V, ID = -0.5 A, VGS = -4.5 V, RGEN = 6 Ω VDS = -5 V, ID = -0.41 A, VGS = -4.5 V 7 15 ns 8 16 ns 55 80 ns 35 60 ns 1.1 1.5 nC 0.31 nC 0.29 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Source Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.25 A (Note 2) -0.85 -0.25 A -1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4 board in still air. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDG6304P Rev.E1 Typical Electrical Characteristics 2.5 VGS =-4.5V -3.0V -2.7V R DS(ON), NORMALIZED -2.5V 0.9 0.6 -2.0V 0.3 -1.5V DRAIN-SOURCE ON-RESISTANCE -ID , DRAIN-SOURCE CURRENT (A) 1.2 VGS = -2.0V 2 -2.5V 1.5 -2.7V -3.0V -3.5V -4.5V 1 0.5 0 0 1 2 3 0 4 0.2 0.4 Figure 1. On-Region Characteristics. R DS(ON),ON-RESISTANCE(OHM) R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE V GS = -4.5V 1.2 1.2 1 0.8 -25 0 25 50 75 100 125 150 I D = -0.2A 4 3 2 TJ = 125 ° C 1 25° C 0 1 TJ , JUNCTION TEMPERATURE (°C) 2 3 4 5 -VGS , GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 1 -I S , REVERSE DRAIN CURRENT (A) 1 TJ = -55°C VDS = -5V 25°C -ID , DRAIN CURRENT (A) 1 5 I D = -0.41A 0.6 -50 0.8 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 1.4 0.6 -I D , DRAIN CURRENT (A) -VDS , DRAIN-SOURCE VOLTAGE (V) 0.8 125°C 0.6 0.4 0.2 0 0.5 1 1.5 2 2.5 -VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 3 VGS = 0V TJ = 125°C 0.1 25°C 0.01 -55°C 0.001 0.0001 0.2 0.4 0.6 0.8 1 1.2 -VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDG6304P Rev.E1 Typical Electrical Characteristics 200 I D = -0.41A VDS = -5V -10V 4 80 CAPACITANCE (pF) -V GS , GATE-SOURCE VOLTAGE (V) 5 -15V 3 2 Ciss 30 10 1 5 0.4 0.8 1.2 1.6 Crss f = 1 MHz V GS = 0 V 3 0.1 0 0 Coss 0.3 1 2 5 Figure 7. Gate Charge Characteristics. 25 Figure 8. Capacitance Characteristics. 50 3 1m 0.5 S RD (O N) LI s 10 ms T MI 10 0m s 1s 10 s DC 0.1 VGS = -4.5V SINGLE PULSE RθJA = 415°C A TA = 25°C 0.05 0.01 0.1 0.2 0.5 SINGLE PULSE R θJA=415°C/W TA= 25°C 40 POWER (W) 1 30 20 10 1 2 5 10 25 0 0.0001 40 0.001 0.01 0.1 1 10 200 SINGLE PULSE TIME (SEC) - V DS , DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. TRANSIENT THERMAL RESISTANCE 1 r(t), NORMALIZED EFFECTIVE -I D , DRAIN CURRENT (A) 10 -VDS , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 0.01 R θJA (t) = r(t) * R θJA R θJA =415 °C/W 0.1 P(pk) 0.05 t1 0.02 0.01 t2 TJ - TA = P * R θJA (t) Single Pulse Duty Cycle, D = t 1/ t 2 0.005 0.002 0.0001 0.001 0.01 0.1 1 10 100 200 t 1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1. Transient thermalresponse will change depending on the circuit board design. FDG6304P Rev.E1 SC70-6 Tape and Reel Data and Package Dimensions SC70-6 Packaging Configuration: Figure 1.0 Packaging Description: Customized Label SC70-6 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 3,000 units per 7" or 177cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13" or 330cm diameter reel. This and some other options are described in the Packaging Information table. Antistatic Cover Tape These full reels are individually barcode labeled and placed inside a pizza box (illustrated in figure 1.0) made of recyclable corrugated brown paper with a Fairchild logo printing. One pizza box contains three reels maximum. And these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. F63TNR Static Dissipative Label Embossed Carrier Tape 21 21 21 21 21 SC70-6 Packaging Information Packaging Option Packaging type Standard (no flow code) TNR Pin 1 D87Z SC70-6 Unit Orientation TNR Qty per Reel/Tube/Bag 3,000 Reel Size 7" Dia 13" 184x187x47 343x343x64 Max qty per Box 9,000 30,000 Weight per unit (gm) 0.0055 0.0055 Weight per Reel (kg) 0.1140 0.3960 Box Dimension (mm) 10,000 343mm x 342mm x 64mm Intermediate box for D87Z Option F63TNR Barcode Label Note/Comments F63TNR Label F63TNR Label sample 184mm x 187mm x 47mm Pizza Box for Standard Option F63TNR Label LOT: CBVK741B019 QTY: 3000 FSID: FDG6302P SPEC: D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F (F63TNR)3 SC70-6 Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Components Trailer Tape 300mm minimum or 75 empty pockets Leader Tape 500mm minimum or 125 empty pockets August 1999, Rev. C SC70-6 Tape and Reel Data and Package Dimensions, continued SC70-6 Embossed Carrier Tape Configuration: Figure 3.0 P0 D0 T E1 F K0 Wc W E2 B0 Tc A0 D1 P1 User Direction of Feed Dimensions are in millimeter Pkg type A0 B0 SC70-6 (8mm) 2.24 +/-0.10 2.34 +/-0.10 W 8.0 +/-0.3 D0 D1 E1 E2 1.55 +/-0.05 1.125 +/-0.125 1.75 +/-0.10 F 6.25 min 3.50 +/-0.05 P1 P0 4.0 +/-0.1 4.0 +/-0.1 K0 T 1.20 +/-0.10 0.255 +/-0.150 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). Wc 5.2 +/-0.3 0.06 +/-0.02 0.5mm maximum 20 deg maximum Typical component cavity center line B0 Tc 0.5mm maximum 20 deg maximum component rotation Typical component center line Sketch A (Side or Front Sectional View) A0 Component Rotation Sketch C (Top View) Component lateral movement Sketch B (Top View) SC70-6 Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max See detail AA Dim N 7" Diameter Option B Min Dim C See detail AA W3 13" Diameter Option Dim D min W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size Reel Option Dim A Dim B 8mm 7" Dia 7.00 177.8 0.059 1.5 0.512 +0.020/-0.008 13 +0.5/-0.2 Dim C 0.795 20.2 Dim D 2.165 55 Dim N 0.331 +0.059/-0.000 8.4 +1.5/0 Dim W1 Dim W2 0.567 14.4 0.311 – 0.429 7.9 – 10.9 Dim W3 (LSL-USL) 8mm 13" Dia 13.00 330 0.059 1.5 0.512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 4.00 100 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 – 0.429 7.9 – 10.9 July 1999, Rev. C SC70-6 Tape and Reel Data and Package Dimensions, continued SC70-6 (FS PKG Code 76) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0055 September 1998, Rev. A1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.