TI BQ77910DBT

bq77910
SLUSA07B – AUGUST 2010 – REVISED MAY 2011
www.ti.com
Stand-Alone Multi-Cell Lithium-Ion/Polymer Precision Protectors
Check for Samples: bq77910
FEATURES
1
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•
•
•
•
•
•
•
•
4-, 5-, 6-, 7-, 8-, 9-, or 10 Series Cell Protection
Individual Cell-Voltage Monitoring
Low-Side NMOS FET Drive for Charge and
Discharge Control
Compatible With 1-mΩ Current-Sense Resistor
Supply-Voltage Range From 5.6 V to 50 V
Integrated 3.3-V Micro-Power LDO Regulator
Low Supply Current
– Normal Mode: 50 µA, Typical
– Shutdown Mode, LDO OFF: 3 µA, Typical
38-Pin TSSOP Package
Internal 50-mA Automatic Cell Balancing
APPLICATIONS
•
•
•
•
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Cordless Power Tools
Cordless Lawn Equipment
Electric Bikes
UPS
Medical Equipment
Light Electric Vehicles (LEV)
DESCRIPTION
The bq77910 precision protector is a complete
stand-alone, self-contained battery-protection and
cell-balancing device intended for Li-ion/polymer
battery packs.
The bq77910 monitors 4 to 10 series individual cell
voltages and provides fast-acting outputs which may
be used to drive N-channel MOSFETs to interrupt the
power path. Activation delays and recovery methods
for each safety condition are fully programmable in
non-volatile memory.
Automatic cell balancing is provided using internal
50-mA cell circuits. A robust balancing algorithm
ensures optimum performance by maintaining all cell
voltages in balance. Balancing may be configured to
operate at all times, only during charge, or can be
disabled completely.
Additional advanced safety features of the bq77910
include the ability to control split power-path
MOSFETs, an open-cell sense-line detection
mechanism, and the ability to detect an open or
shorted external temperature sensor.
Programmable Protection Functions
• Wide range of programmable detection thresholds
and delay times
• Configurable for multiple cell types and application
requirements:
– Cell overvoltage
– Cell undervoltage
– Pack discharge overcurrent
– Pack discharge short circuit
– Pack charge short-circuit current
• Variable gain (×1 or ×5) current-sense circuit
– Compatible with a wide range of current-sense
resistors (1 mΩ to 5 mΩ typical) sized for
application requirements
Fixed Hardware Protection Functions
• Preset overtemperature protections
• Open-cell detection
• Open and shorted thermistor detection
• Brownout protection quickly shuts off FETs under
low battery conditions to avoid FET overheating
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
bq77910
SLUSA07B – AUGUST 2010 – REVISED MAY 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN DETAILS
PIN FUNCTIONS (38-Pin Package)
PIN
NAME
DESCRIPTION
NO.
BAT
31
Power supply voltage, tied to highest cell(+)
CCAP
20
Energy storage capacitor for charge FET drive
CHG
21
Charge FET (n-channel) gate drive
CHGST
14
Charger-status input, used to detect charger connection/wakeup
CPCKN
19
Pack – charger negative terminal (charger return)
DCAP
16
Energy storage capacitor for discharge FET drive
DPCKN
18
Pack – discharge negative terminal (load return)
DSG
17
Discharge FET (n-channel) gate drive
EEPROM
28
EEPROM programming voltage input. Connect to VSS for normal operation.
GND
23, 24, 25
2, 4, 30, 35,
37
NC
Logic ground (not for power return or analog reference). Tie to VSS.
No connect (DO NOT CONNECT) externally. Failure to leave NC pins open can cause faulty operation.
SCLK
27
Serial-communication clock input used for EEPROM programming
SDATA
26
Serial-communication data input/output used for EEPROM programming (open-drain)
SENSE(+)
10
Current-sense input
SENSE(–)
9
Current-sense input
TS
13
Temperature sensing input
VC1
32
Sense-voltage input terminal for most-positive cell
VC2
33
Sense-voltage input terminal for second-most-positive cell
VC3
34
Sense-voltage input terminal for third-most-positive cell
VC4
36
Sense-voltage input terminal for fourth-most-positive cell
VC5
38
Sense-voltage input terminal for fifth-most-positive cell
VC6
1
Sense-voltage input terminal for sixth-most-positive cell
VC7
3
Sense-voltage input terminal for seventh-most-positive cell
VC8
5
Sense-voltage input terminal for eighth-most-positive cell
VC9
6
Sense-voltage input terminal for ninth-most-positive cell
VC10
7
Sense-voltage input terminal for tenthmost-positive (most-negative) cell
VC11
8
Most-negative cell(–) terminal (BAT–)
VREG
12
Integrated 3.3-V regulator output
VSS1
29
Analog ground (substrate reference)
VSS2
11
Analog ground (substrate reference)
VTSB
15
Thermistor bias supply (sourced from VREG)
ZEDE
22
Zero Delay test mode pin. Enables serial communications interface and minimizes protection delay times
when connected to logic high. Connect to VSS for normal operation. A strong connection is recommended.
2
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PIN DIAGRAM – bq77910 – 38-Pin SSOP DBT PACKAGE
DBT PACKAGE
(TOP VIEW)
VC6
1
38
VC5
NC
2
37
NC
VC7
3
36
VC4
NC
4
35
NC
VC8
5
34
VC3
VC9
6
33
VC2
VC10
7
32
VC1
VC11
SENSE(–)
8
31
BAT
9
30
NC
SENSE(+)
10
29
VSS1
VSS2
11
28
EEPROM
VREG
12
27
SCLK
TS
13
26
SDATA
CHGST
14
25
GND
VTSB
15
24
GND
DCAP
16
23
GND
DSG
17
22
ZEDE
DPCKN
18
21
CHG
CPCKN
19
20
CCAP
P0034-04
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FUNCTIONAL BLOCK DIAGRAM
BAT
VC1
3.3 V LDO
VREG
VC2
POR / STARTUP UVLO
MULTI-LEVEL
TEMP
COMPARATOR
VC3
VTSB
TS
VC4
VCELL_X
PROGRAMMABLE
UV COMPARATOR
PROGRAMMABLE
DELAY
EEPROM
1 mA
VC5
CELL
SELECTION
SWITCHES
VC6
NTC/ Charger
Disable
PROGRAMMABLE
OV COMPARATOR
Thermistor
Check
PROGRAMMABLE
DELAY
VC7
CELL SAMPLING SELECTION CONTROL
( 1– 10)
VC8
PROGRAMMABLE
DISCHARGE
OVERCURRENT
COMPARATOR
VC9
CONTROL
LOGIC
SCLK
I2 C SERIAL
INTERFACE
SDATA
EEPROM R/W
EEPROM
TESTMODE
CONTROL
PROGRAMMABLE
DELAY
ZEDE
VC10
PROGRAMMABLE
DISCHARGE
SHORT CIRCUIT
COMPARATOR
VC11
SENSE(+)
SENSE(- )
PROGRAMMABLE
CHARGE SHORT
CIRCUIT
COMPARATOR
COMP
CHGST
WAKEUP
CIRCUIT
PROGRAMMABLE
DELAY
COMP
OC / SC
RECOVERY
CIRCUIT
PROGRAMMABLE
DELAY
COMP
VSS
DSG FET
NMOS DRIVER
DCAP DSG
CHG FET
NMOS DRIVER
DPCKN CCAP CHG
CPCKN
ORDERING INFORMATION
4
PART NUMBER
PACKAGE TYPE
bq77910DBT
TSSOP
50-piece tube
bq77910DBTR
TSSOP
2000-piece reel
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PACKAGING
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
DC supply-voltage range, VMAX
–0.3 to (5 × N) V, N = number of cells
implemented in pack
BAT
DPCKN
–0.3 V to 50 V
CPCKN
(BAT – 50) V to (BAT + 0.9) V
Cell-to-cell differential, VCx to VC(x+1), x = 1 to 10
Input voltage range, VIN
SENSE(+)
–3 V to 3 V
SENSE(–)
–0.3 V to 50 V
SCLK, SDATA, ZEDE
TS, CHGST
(2)
–0.3 V to 7 V
(3) (4)
–0.3 V to BAT V
EEPROM
–0.3 V to 15 V
Cell input VCx, x = 1–10
(11 – x) × 5 V
–3 V to 3 V
Cell input VC11
Output voltage range, VO
–0.3 V to 9 V
CHG referenced to CPCKN
– 0.3 V to 15 V
DSG referenced to VSS
–0.3 V to 15 V
VTSB (2)
–0.3 V to 5 V
Current for cell balancing, ICB
70 mA
Regulator current, IREG
45 mA
–65°C to 150°C
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All signal / logic pins which may be connected to the pack external terminals are internally clamped to a maximum voltage of 5 V. If the
external source driving these signals exceeds the clamp threshold, series resistance from the pin to the pack terminal is required to
avoid overstress on the clamping circuit.
CHGST and TS pins are tolerant of applied overvoltage as noted to allow for charger single-fault tolerance. Normal operating range is
typically 3.3 V or less at this pin; thus, high voltage seen here may correspond to a fault condition.
Although no damage results when CHGST = VSS – 0.3 V, for proper operation at power up, CHGST must be ≥ VSS – 0.25 V.
THERMAL INFORMATION
bq77910
THERMAL METRIC (1)
DBT
UNIT
38 PINS
Junction-to-ambient thermal resistance, non-LDO (2)
θJA
(2) (3)
71.7
°C/W
θJA2
Junction-to-ambient thermal resistance, LDO
115.8
°C/W
θJCtop
Junction-to-case (top) thermal resistance (4)
18.5
°C/W
θJB
Junction-to-board thermal resistance (5)
33.9
°C/W
1
°C/W
38.9
°C/W
ψJT
Junction-to-top characterization parameter, non-LDO
ψJT2
Junction-to-top characterization parameter, LDO (6)
(1)
(2)
(3)
(4)
(5)
(6)
(6)
(3)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
These metrics should be used only for calculating junction temperature due to power dissipation resulting from the IOUT load on VREG.
Junction temperature calculations for all other sources of power dissipation should use the standard values θJA and ψJT.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
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THERMAL INFORMATION (continued)
bq77910
THERMAL METRIC (1)
DBT
UNIT
38 PINS
ψJB
θJCbot
(7)
(8)
Junction-to-board characterization parameter (7)
33.2
°C/W
(8)
N/A
°C/W
Junction-to-case (bottom) thermal resistance
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
BAT
(1)
5.6
Cell differential, VCx to VC(x + 1),
(x = 1 to 10 )
TYP
(2)
MAX
V
4.375
V
43.75
1.4
UNIT
(3)
(11 – x) ×
4.375 V
VI
Input voltage range
VIH
Logic-level input, high
VIL
Logic-level input, low
VSENSE(+)
VSENSE(–)
Voltage applied at SENSE(±)
pins
RVCX
Recommended VCx nominal
input resistance
IREG
Regulator current
10
mA
ICB
Cell balancing current
50
mA
CVCX
Recommended VCx nominal
input filter capacitance
1
µF
RCPCKN,
RDPCKN
Recommended isolation-pin
input resistance
RLDRM_DET
Pulldown for load-removal
detection
CVREG
External 3.3-V REG capacitor
Cell input VCx, x = 1 – 10
Cell input VC11
SCLK, SDATA, EEPROM, ZEDE
–1
1
0.8 × VREG
V
0.2 × VREG
V
VSS – 1
VSS + 1
V
–0.2
BAT
V
1000
Ω
50
100
100
Ω
50
kΩ
µF
1
EEPROM number of writes
3
times
Operating temperature
Meeting all specification limits
–25
85
°C
TFUNC
Functional temperature
Operational but may be out of spec limits,
no damage to part
–40
100
°C
CCCAP,
CDCAP
External capacitance on CCAP
and DCAP pins (4)
RP
Serial communication interface
SCLK, SDATA
pullup resistance
TOPR
(1)
(2)
(3)
(4)
6
0.1
1
µF
2.2
kΩ
The voltage rate of change at the BAT pin should be limited to a maximum of 1 V per µs in order to prevent unwanted device shutdown.
Minimum voltage assumes 4-cell connection at 1.4 V/cell.
Maximum voltage assumes 10-cell connection at 4.375 V/cell.
CCCAP and CDCAP act as charge reservoirs for the CHG and DSG pins when driving large protection FETs. Minimum value is required
for stability, independent of the CHG and DSG loading.
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ELECTRICAL CHARACTERISTICS
Vcell(n) = 1.4 to 4.375 for all cells, TA = –25°C to 85ºC, BAT = 5.6 to 43.75 V; Typical values stated where TA = 25°C and
BAT = 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ICC
ISHUTDOWN_1
ISHUTDOWN_2
(1)
Normal-mode average supply
current
CHG, DSG = on (no dc load), VREG = on,
IREG = 0 mA, BAT = 36 V
50
75
µA
Shutdown mode, LDO on
Vcell < Vuv, VREG = on (EEPROM set)
µA
Shutdown mode, LDO off
45
70
Vcell < Vuv, VREG = off (EEPROM set), CPCKN = 0.3 V
5
17
Vcell < Vuv, VREG = off (EEPROM set), CPCKN = 0.5 V
20
60
µA
INTERNAL POWER CONTROL (STARTUP, SHUTDOWN, GATE DRIVE UNDERVOLTAGE)
VSTARTUP
Minimum voltage for initial power
up (2)
Measured at BAT pin
VPOR (3)
LDO POR voltage – voltage on
LDO that initiates a POR
ILDO = 2 mA
2.7
VGATE_UV
FET gate shutdown threshold
(voltage falling)
Measured at CCAP / DCAP pins
4.5
VGATE_UV_H
FET gate shutdown hysteresis
voltage
Measured at CCAP / DCAP pins
0.45
FET DRIVE
Gate drive voltage at DSG and
CHG pins for FET ON (enabled)
conditions
BAT voltage = 10 V (gate-drive circuit in dropout mode), no
dc load
BAT voltage = 6.4 V (gate-drive circuit in dropout mode),
no dc load
V(FETOFF)
Gate drive voltage at DSG and
CHG pins for FET OFF
(disabled) conditions
tr
Rise time, measured at IC pin
(CHG or DSG)
3.2
V
5.3
V
0.7
V
Fall time, measured at IC pin
(CHG or DSG)
11
12
14
9
V
>VGATE_UV
VO(FETOFFDSG) = V(DSG) – VGND
0.2
VO(FETOFFCHG) = V(VHG) – Vpack–
0.2
CL = 50 nF, BAT = 43.75
V
CL = 50 nF, BAT = 6.4 V
tf
V
(4)
BAT voltage = 43.75 V (gate-drive circuit in regulation
mode), no dc load
V(FETON)
4.9
7
CL = 50 nF, BAT = 43.75
V
CL = 50 nF, BAT = 6.4 V
V
VDSG: 10% to 90%
90
140
VCHG: 10% to 90%
90
140
VDSG: 10% to 90%
90
140
VCHG: 10% to 90%
90
140
VDSG : 90% to 10%
10
20
VCHG: 90% to 10%
20
40
VDSG : 90% to 10%
50
100
VCHG: 90% to 10%
50
100
µs
µs
VREG, INTEGRATED 3.3-V LDO
Output-voltage regulation under
all line, load, temperature
conditions
IOUT = 10 mA (maximum dc load) (5)
3.1
3.3
3.55
VREG
IOUT = 0.2 mA
3.1
3.3
3.55
ISC
Short-circuit current limit
VREG = 0 V, forced external short (thermally protected) (6)
20
(1)
(2)
(3)
(4)
(5)
(6)
45
V
V
mA
For predictable shutdown current, the voltage at CPCKN with respect to VSS must be controlled. In the parallel FET case, CPCKN is
clamped through the body diode of the charge FET. In the series FET case, external circuitry is required to keep CPCKN from floating.
Contact TI for recommended application circuits.
At this voltage, the LDO has sufficient voltage to maintain regulation. The POR then enables the charger-detect logic. Logic is held in
reset until inserted into charger and LDO has reached VPOR. The part still operates below 7 V to the spec limit of 5.6 V.
VPOR and VREG are derived from the same internal reference, so that the MAX value of VPOR and the MIN value of VREG do not occur
at the same time.
FET drive is disabled if voltage at CCAP or DCAP pins < VGATE_UV. Turnoff due to gate-drive undervoltage condition meets the same
timing requirements as logic-initiated gate turnoff.
ELECTRICAL CHARACTERISTICS assume that IOUT = 0 so that the internal junction temperature (TJ) is effectively equal to the
ambient temperature (TA). For larger non-zero values of IOUT, TJ can be significantly higher than TA. In these cases, TJ should be
substituted for TA in the test and operating conditions. TJ can be calculated from the device power dissipation as described under
THERMAL CHARACTERISTICS. The device power dissipation due to IOUT is (VBAT – VREG) × IOUT.
Regulator shuts down prior to current-limit maximum specification if junction temperature exceeds safe range.
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ELECTRICAL CHARACTERISTICS (continued)
Vcell(n) = 1.4 to 4.375 for all cells, TA = –25°C to 85ºC, BAT = 5.6 to 43.75 V; Typical values stated where TA = 25°C and
BAT = 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TS TEMPERATURE SENSING
VTSB pin pullup resistance
IOUT = –1 mA at VTSB pin, rDS(on) = (VREG – VVTSB) / 1 mA
50
150
TS pin fault-signal pulldown
resistance
OV_TS_CTRL = 1, Vcell > Vov
50
150
ITS_PD
TS pin thermistor check
pulldown current
TS = 3.3 V (externally driven)
2
4
tTHERM_CHECK
Thermistor fault sampling interval
VEXT_BIAS_DET
Thermistor external-bias
supply-detection threshold
Internal VTSB supply off
13
VHOT
Overtemperature-detection
threshold (ratiometric to VTSB)
Internal VTSB supply on, no external bias
VTH_SHORT
Thermistor short-detection trip
threshold (ratiometric to VTSB)
VTH_HYST
VTH_OPEN
rDS(on)
Ω
1
4
15
µA
s
17
%VREG
17
21
%VREG
Internal VTSB supply on, no external bias
1
10
%VREG
TS comparator hysteresis
Hysteresis for short, open, and overtemperature
comparators
3
8
%VREG
Thermistor open detection
(ratiometric to VTSB)
Internal VTSB supply on, no external bias
90
98
%VREG
Cell-balance internal
resistance (7)
rDS(on) for internal FET
switch, TA = 0°C to 50°C
CELL BALANCE
RBAL
tCELL_BAL_CHECK
VCELL = CBVMAX = 3.9
–50%
10
50%
VCELL = CBVMAX = 3.2
–50%
20
50%
VCELL = CBVMAX = 2.5
–50%
30
50%
Cell balancing update interval
7.5
Ω
min
OPEN CELL CONNECTION
ILOAD_OPEN_CELL (8)
Cell loading during open-cell
detect
tOPEN_CELL_CHECK
Open-cell fault-sampling interval
(N = total number of cells in
pack)
ROPEN_CELL
Minimum impedance from cell
terminal to VCx input that is
interpreted as an open condition
75
450
4×N
µA
s
100
kΩ
BATTERY-PROTECTION-THRESHOLD TOLERANCES (9)
OV detection threshold accuracy
for VOV = 4.2 V (10)
TA = 0°C to 50°C
–25
25
TA = –25°C to 85°C
–50
50
OV detection threshold accuracy
for VOV = 3.2 V (10)
TA = 0°C to 50°C
–50
50
TA = –25°C to 85°C
–75
75
ΔVUV
UV detection threshold accuracy
TA = –25°C to 85°C
–100
100
ΔVSCD
ΔVOCD
OCC/SCD detection threshold
accuracy
TA = –25°C to 85°C
–20%
20%
ΔVOV
ΔVSCC
SCC detection threshold
accuracy
VSCC from 10 mV to 15 mV
VSCC > 15 mV
mV
–3
3
–20%
20%
–15%
15%
–15%
15%
–15%
15%
–15%
15%
mV
mV
BATTERY PROTECTION DELAY-TIME TOLERANCES (9)
ΔtOV
OV detection delay time
accuracy
ΔtUV
UV detection delay time
accuracy
ΔtSCD
OCD/SCD detection delay time
accuracy
ΔtSCC
SCD detection delay time
accuracy
Default EEPROM setting
tSCD Max
(7)
Balance current is not internally limited. External series resistance must be used to ensure balance current is below 50 mA maximum to
limit IC internal power dissipation.
(8) This current is sufficient to detect an open-cell condition down to 100 kΩ across the cell from circuitry outside of the bq77910. The
average current from this loading is less than 1 µA for a 10-cell configuration.
Application Note: When using this part with other devices that connect to the battery cells, care must be taken to avoid excessive
parallel capacitances on the cell input pins.
(9) Nominal values are set by EEPROM programming; see EEPROM table for possible values.
(10) Standard production parts are calibrated at 4.2 V. An additional OV threshold accuracy shift of 25 mV per volt of OV set point is
possible. Contact TI for calibration options at set point voltages other than 4.2 V.
8
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ELECTRICAL CHARACTERISTICS (continued)
Vcell(n) = 1.4 to 4.375 for all cells, TA = –25°C to 85ºC, BAT = 5.6 to 43.75 V; Typical values stated where TA = 25°C and
BAT = 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGER DETECTION (11)
Voltage at CHGST pin,
referenced to VSS, to determine
charger present (charger
insertion detected when voltage
at CHGST pin > VCHG_DET1)
5.6 V < BAT < 43.75 V
0.3
0.65
0.85
V
VOPEN_LOAD
Voltage at DPCKN, referenced
to VSS, with DSG FET disabled
to detect load removal (load
removal detected when voltage
at DPCKN < VOPEN_LOAD)
5.6 V < BAT < 43.75 V
1.5
2
2.5
V
RDSG_GND
Internal resistance between
DPCKN and VSS
5.6 V < BAT < 43.75 V
1000
1500
3000
kΩ
Data retention
5.6 V < BAT < 43.75 V
10
VCHG_DET1
LOAD REMOVAL DETECTION
EEPROM LIFETIME
TDR
years
(11) Alternate charger detection options are available using the CPCKN pin. Contact TI for additional configuration versions.
SERIAL COMMUNICATION INTERFACE (for Configuration Only)
BAT = 5.6 V to 43.75 V, TA = –25°C to 85°C
MAX
UNIT
tr
SCLK, SDATA　rise time
PARAMETER
MIN
1000
ns
tf
SCLK, SDATA　fall time
300
ns
tw(H)
SCLK pulse duration, high
8
µs
tw(L)
SCLK pulse duration, low
10
µs
tsu(STA)
Setup time for START condition
9.4
µs
th(STA)
START condition hold time after which first clock pulse is generated
8
µs
tsu(DAT)
Data setup time
250
ns
th(DAT)
Data hold time
0
µs
tsu(STOP)
Setup time for STOP condition
8
µs
tsu(BUF)
Time the bus must be free before new transmission can start
tV
Clock low to data out valid
th(CH)
Data out hold time after clock low
0
fSCL
Clock frequency
0
µs
9.4
900
ns
ns
50
kHz
tsu(BUF)
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GENERAL OPERATIONAL OVERVIEW
POWER MODES
The bq77910 has the following power modes: active, shutdown (LDO enabled), and shutdown (LDO disabled).
The following table outlines the operational functions in the different power modes.
POWER MODE
MODE DESCRIPTION
Active
The IC is operating with internal LDO enabled and battery monitoring functions available and operating. The active
power mode includes normal operation, i.e., all cell voltages, load current, and temperature are within range, and
DSG and CHG FETs are enabled. The active power mode also includes any fault detection / protection states
which do not require the IC to drop to a low-power state.
Shutdown – LDO
enabled
Under certain fault conditions (see Table 2), the bq77910 enters a reduced-power state to minimize current drain
on the battery pack. The LDO output and other critical circuitry remain active. All other functions of the IC are
inactive until a recovery condition is met.
Shutdown – LDO
disabled
Under certain fault conditions (see Table 2), the bq77910 enters the lowest possible power state to minimize
current drain on the battery pack. The LDO output is turned off. All functions of the IC are inactive until a charger
recovery condition is detected.
NORMAL OPERATION MODE
When no cell voltage, pack current, temperature, open cell, or thermistor faults are present, the CHG and DSG
FETs are turned ON, allowing normal operation of the system.
The architecture of the bq77910 allows the customer to implement different arrangements of power FET
components within the battery pack. Some examples of different power FET arrangements are shown in the
Application Information section.
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PROGRAMMABLE PROTECTION FUNCTIONS
The bq77910 provides the following types of protection functions:
• Cell overvoltage
• Cell undervoltage
• Discharge overcurrent
• Discharge-current short circuit
• Charge-current short circuit
All of the voltage/current and time-delay thresholds can be adjusted for a specific application by programming the
EEPROM settings of the IC. The ranges available are shown in Table 1.
CAUTION
Only a maximum of three EEPROM write cycles per byte should performed to ensure
long-term data retention stability. (For circuit development purposes, the EEPROM
may be rewritten many times.)
Table 1. Detection Voltage, Detection Delay Time Summary
PARAMETER
Overvoltage
Undervoltage
RANGE
(EEPROM Selected)
Cell voltage
2.8 V
4.375 V
25 mV
0.5 s
2.25 s
0.25 s
0 mV
300 mV
25 mV or 50 mV
Cell voltage
SENSE(–) pin voltage with
respect to SENSE(+)
SENSE(–) pin voltage with
respect to SENSE(+)
Delay
SENSE(–) pin voltage with
respect to SENSE(+)
1.4 V
2.9 V
100 mV
500 ms
32 s
Binary spacing
400 mV
400 mV
1600 mV
Low
25 mV
100 mV
5 mV
High
125 mV
500 mV
25 mV
Delay
Charge short circuit
STEP
Hysteresis
Hysteresis
Discharge short circuit
MAX
Delay
Delay
Discharge overcurrent
MIN
20 ms
300 ms
20 ms
400 ms
2000 ms
100 ms
Low
40 mV
190 mV
10 mV
High
200 mV
950 mV
50 mV
Fast
60 µs
960 µs
60 µs
Slow
50 ms
1500 ms
50 ms or 100 ms
Low
–10 mV
–85 mV
5 mV
High
–50 mV
–425 mV
25 mV
60 µs
960 µs
60 µs
Delay
Cell Overvoltage Detection and Recovery
The CHG FET is turned off if any one of the cell voltages remains higher than VOV for a period greater than tOV.
As a result, the cells are protected from an overcharge condition. After an overvoltage event occurs, the all cells
must relax to less than (VOV – VHYST) to allow recovery.
The VOV, tOV, and VHYST values are settable via EEPROM bits OVT, OVD and OVH.
Cell Undervoltage Detection and Recovery
When any one of the cell voltages falls below VUV, for a period of tUV, the bq77910 enters the undervoltage
protection state. The DSG FET is turned off, and depending on configuration, the device could enter the
SHUTDOWN mode. Both VUV and tUV can be configured via EEPROM bits UVT and UVD.
The recovery (fault release) is controlled by the EEPROM configuration bit UV_REC.
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If UV_REC = 0, the DSG FET is re-enabled when all the cell voltages increase back above the VUV threshold
level plus the hysteresis value; there is no time-delay part of the recovery. In this case, when UV_REC = 0 and
under high load currents, the Vcell voltages could recover to >UV + hyst very quickly, re-enabling the FETs and
allowing the high load current to persist. Care should be taken when using this UV_REC = 0 mode, as the power
MOSFETs could oscillate rapidly.
CAUTION
Care should be taken to properly set overcurrent and cell undervoltage trip thresholds,
because it is possible that a fully charged pack with a continuous high discharge load
can oscillate in and out of the undervoltage condition. This may result in overheating of
the cells or protection MOSFETs due to the potentially high-duty-cycle operation.
If UV_REC = 1, the DSG FET is re-enabled when all the cell voltages increase back above the VUV threshold
level plus the hysteresis value AND the load is removed.
Current is interrupted by opening the FETs, and at this point the cell voltages may quickly recover above the UV
+ hyst levels if the battery pack is not completely depleted. However, the external load may remain attached.
When the external load is removed, the IC detects load removal and reconnects the DSG FET.
If UV_REC_DLY = 1 and any cell remains below the VUV threshold level plus the hysteresis for longer than 8
seconds, the device enters SHUTDOWN mode. If UV_REC_DLY = 0, the device does not enter the
SHUTDOWN mode from the cell undervoltage fault condition.
The power state of the device is determined by the SHTDIS bit. If the SHTDIS bit = 1, then the LDO remains
active during the SHUTDOWN mode. If the SHTDIS bit = 0, then the LDO is turned off during the SHUTDOWN
mode. In both cases, insertion into a charger is required to recover from the SHUTDOWN mode.
Charger detection methods are discussed in later sections, such as Application Information.
Overcurrent in Discharge (OCD) Detection
The OCD detection feature senses an overload current by measuring the voltage across the sense resistor.
When an overload condition is detected, both of the power FETS are disabled to prevent damage to the cells and
FET components. Criteria for fault recovery depend on the state of the SOR (EEPROM bit). Overcurrent trip level
(VOCD) and blanking time delay (tOCD) are programmable via EEPROM bits OCDT and OCDD to match individual
application requirements.
Short Circuit in Discharge (SCD) Detection
The SCD detection function senses severe discharge current by measuring the voltage across the sense
resistor. When a short circuit is detected, both of the power FETs are disabled to prevent damage to the cells
and FET components. Criteria for fault recovery depend on the state of the of the SOR (EEPROM bit).
Short-circuit trip level (VSCD) and blanking time delay (tSCD) are programmable via EEPROM bits SCDT and
SCDD to match individual application requirements.
Load Removal Detection/OCD and SCD Fault Recovery
The part includes an internal high-impedance connection between the DPCKN and VSS pins of approximately
1.5 MΩ
. An external load (for example power tool motor winding), if still connected to the pack
terminals, would present a very low impedance relative to the high internal pulldown resistance.
NOTE
If the external load presents additional capacitance, then an external pulldown may be
required between the DPCKN and VSS pins. This extra pulldown does not increase
battery load current when the external load is removed.
If the DSG power FET is disabled after an overload or short-circuit event, the voltage at the DPCKN is
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approximately equivalent to the BAT voltage potential while an external load (e.g., power tool motor) is present at
the pack terminals. When the external load is removed, the high-value internal resistance pulls down the DPCKN
potential to the internal VSS level. An internal comparator monitors the DPCKN terminal voltage during the
protection state. When the DPCKN voltage falls to < VOPEN_LOAD (approximately 2 V), the load removal is
detected. Fault recovery from an OCD or SCD event depends on the state of the SOR EEPROM bit.
If SOR = 0, the FETs are re-enabled only after the external load removal is detected.
If SOR = 1, the FETs are re-enabled after the load is removed and a charger insertion is detected.
(Details of charger presence detection methods are discussed in later sections.)
Short Circuit in Charge (SCC) Detection
The SCC detection function senses severe charge current by measuring the voltage across the sense resistor. In
this case, the voltage is negative (opposite polarity of OCD and SCD detection). When a short circuit is detected,
both of the power FETS are disabled to prevent damage to the cells and FET components. Short-circuit trip level
(VSCD) and blanking time delay (tSCD) are programmable via EEPROM bits SCCT and SCCD to match individual
application requirements.
NOTE
The current sensing element must be located along a common charge and discharge path
in order to protect against both charge and discharge current faults. This is particularly
important to note for parallel FET configurations or configurations that combine the FET
with the sense element.
Short Circuit in Charge Recovery
An SCC fault is cleared after charger removal is detected. (See later sections for details of charger insertion and
removal detection methods).
FIXED HARDWARE FAULT-PROTECTION FUNCTIONS
The bq77910 provides a number of fixed protection settings for hardware faults as listed:
• Open cell connection
• Pack voltage Brownout condition – power FET protection
• Charger-enable temperature range
• Open thermistor connection
• Shorted thermistor connection
• Overtemperature protection
Open Cell Connection
A mechanical or assembly fault in the pack can cause a high-impedance or broken connection between the IC
cell sense pins and the actual cells. During operation, the bq77910 periodically checks the validity of the
individual cell voltage reading by applying a micropower pulsed load across each cell. If the connection between
the pin and the cell is opened, the apparent cell voltage will collapse and a fault (permanent failure) condition is
detected. The open cell detection reading is taken at a time interval of tOPEN_CELL_CHECK, as specified in the
parametric tables. Recommended external filter-capacitor maximum value is also listed in the Recommended
Operating Conditions. Because an open-cell fault may be considered as a permanent failure, the fault detection
logic must detect two consecutive open-cell conditions prior to activating the protection condition for an open-cell
fault. Due to the nature of open-cell fault conditions, other apparent faults may be observed during an open-cell
condition.
Summary of open-cell detection-logic operation:
• For an N-cell battery pack, the bq77910 always protects (by opening the FETs) in some manner within the 2
× N × tOPEN_CELL_CHECK time frame (sampling interval is tOPEN_CELL_CHECK, and two successive open cell faults
are required to avoid nuisance tripping).
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•
•
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Because an open cell connection results in a floating VCx input, a UV or an OV fault may be detected before
the open-cell fault due to their shorter fault filter times. Furthermore, the OV or UV condition may not be
stable and the fault may recover during the open-cell check interval (i.e., the FETs may toggle). In all cases
the open-cell fault is detected within the open-cell fault filter time and the FETs are shut off until the recovery
conditions are satisfied.
If SHTDIS = 1, an open-cell fault is permanent until the battery is disconnected from the chip.
If SHTDIS = 0, the LDO shuts down following the detection of an open-cell fault, provided that a charger is
not detected. When the pack is awakened following this, the open-cell fault is initially cleared (FETs closed)
and must be re-evaluated over the filter time before the fault is again registered. Charger detection inhibits
LDO shutdown; however, once the charger is disconnected, the LDO then shuts down, provided that the
recovery conditions have not yet been satisfied.
Additional Fault Protection Functions
The brownout protection functionality is discussed in the IC Internal Power Control section of this document.
Thermistor fault detection, charger/thermistor interface and control are discussed in the Application Information
section.
IC INTERNAL POWER CONTROL
Power-On Reset/UVLO
On initial application of power to the BAT pin, the IC internal power supply rail begins to ramp up. The IC
contains an internal undervoltage lockout (UVLO)/power-on reset (POR) circuit that prevents operation until the
BAT voltage is sufficient to ensure predictable start-up and operation. All power for the IC internal circuitry is
derived from the BAT pin. The UVLO/POR start-up threshold is specified in the parametric table as VSTARTUP.
Once the BAT voltage has exceeded this level, the internal LDO regulator and control circuitry are enabled and
continue to operate even if BAT falls below VSTARTUP. If the BAT pin falls below the operational range given
under Recommended Operating Conditions, the device powers down.
On initial power up, the state of the output MOSFET drive pins (CHG and DSG) is indeterminate until the voltage
on BAT reaches the VSTARTUP threshold. No load should be applied during this period.
BAT Holdup/Brownout Protection Functionality
The BAT pin is used to power the IC internal circuitry, and should be supplied through a diode and held up with a
capacitor (1) placed near the IC as shown in the application diagrams (see Figure 2 CELL BALANCING
FUNCTION). The external diode prevents discharge of the IC power rail during external transients on the
PACK(+) node.
This allows the bq77910 to maintain proper control of the pack and system during brownout conditions.
Brownout is defined as a situation during which the stack voltage collapses to a voltage below the minimum
operating voltage of the IC (~5.6 V) for a short duration (~1 s). A typical application case is shown below.
Additional examples are provided in the Application Information section later in this document.
If there are short-duration sags in the PACK(+) voltage (typically due to high load transients), the operating
current for the IC is momentarily provided by the external capacitor. Assuming that there is no external load on
the VREG (LDO output) pin, the IC draws approximately 50-µA average current from the capacitor. The holdup
time before the IC goes into shutdown mode depends on the initial pack voltage. For a normal low battery initial
condition using a 4-cell stack, the cells may be in the range of 3 V/cell or 12 V total for the pack voltage. If a load
transient occurs at this point, and the pack voltage sags down to below the IC POR threshold, the voltage at the
BAT pin is held above 5 V for slightly greater than one second using a 10-µF capacitor.
Waveforms typical of a load transient during low pack voltage conditions are shown as follows. In the first load
transient, the PACK(+) rail momentarily collapses but the load is disconnected before the holdup time limit is
exceeded. In the second load transient, the load is left on for a duration exceeding the holdup capability, so when
the IC operating voltage reaches the gate-drive undervoltage limit, the external power FETs are disabled to
disconnect the load.
(1)
14
The capacitor should be sized according to the application requirements. A typical value would be 10 µF.
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Load Disconnect (Gate Drive Shutoff)
80
I_LOAD
60
40
20
14
12
V_PACK(+)
10
8
Minimum
Operating
Voltage
(5.6 V)
6
4
14
12
10
V_BAT
(at IC PIN) 8
6
4
T_holdup ~ 1 s
Minimum
Operating
Voltage
(5.6 V)
Time (s)
Figure 1. Load Transient Examples
BAT Voltage Peak Detection/Transient Suppression
The use of an external diode and holdup capacitor allows the IC to provide controlled operation during brownout
conditions. However, when the battery pack is at a high level, a different issue must be considered.
During normal operation of power equipment, load transients may induce high-voltage pulses on the PACK(+) rail
that exceed the steady-state dc voltage output of the battery pack. In some cases, these transient voltages can
exceed the battery rail by several volts. The voltage at the BAT pin may be held up to these higher voltages for a
longer duration because the diode prevents the capacitor from discharging back into the cell stack after the
transient pulses decay. When the dc level of the battery pack voltage is near 43.75 Vdc, high-current load
disconnection may cause transients that would exceed the absolute maximum ratings of the device.
The BAT pin incorporates an internal Zener clamp that dissipates any transient voltage at the BAT pin that
exceeds 50 V. This internal clamp has very limited energy absorption ability. Therefore, additional external
circuitry is required for transient suppression, depending on the application environment. A Zener or equivalent
rated at <5 Ω and >3 W is recommended.
BAT Voltage Rate of Change
In addition to providing the holdup function, the filter components at the BAT pin serve to limit the maximum
voltage rate of change. The voltage rate of change at the BAT pin should be limited to a maximum of 1 V per µs
in order to prevent unwanted device shutdown.
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PACK(+)
BAT
VREG
3.3-V LDO
VTSB
VC6
RVCX
TS
CVCX
VC7
1 mA
RVCX
Thermistor
Check
NTC / Charger
Disable
CVCX
VC8
bq77910
Cell Monitoring and Control Subsystems
RVCX
CVCX
VC9
RVCX
CVCX
CHG_DET
VC10
CHGST
RVCX
1000 W
COMP
CVCX
RVCX
VC11
COMP
1 kW
REF
(AGND)
1 mW
PWR
(PGND)
SENSE (+)
COMP
0.1 mF
SENSE (–)
1 kW
DSG FET
NMOS DRIVER
0.1 mF
RLDRM_DET
RDPCKN
CHG
REF
(AGND)
CPCKN
CCAP
DPCKN
DSG
DCAP
VSS
CHG FET
NMOS DRIVER
RCPCKN
PACK(–)
Figure 2. Example 5-Cell, Series FET Configuration Schematic Using bq77910
Waveforms illustrative of load transients during high pack voltage conditions are shown here.
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80
I_LOAD
60
40
20
60
50
40
V_PACK(+)
30
20
10
60
50
V_BAT
(at IC PIN)
VCLAMP THRESHOLD
40
30
20
10
Time mS
Figure 3. High-Voltage Load-Transient Waveforms
FET Gate Drive Control
As noted in the previous section, the BAT voltage at the IC pin is held up slightly longer than the external
PACK(+) voltage using the external diode/capacitor to feed the BAT rail. Thus, if the BAT pin voltage at the IC
sags, the external voltage sag will have exceeded the holdup time, and the IC is no longer able to operate for an
extended period of time. At this point, the DSG and CHG gate drive outputs are actively driven low. The FET
driver stages use two additional external capacitors (connected at the CCAP and DCAP pins) to maintain a local
power reservoir dedicated to the gate drive circuitry, as the system (BAT) voltage may be collapsing during the
time that the FETs are being turned off. The FETs are turned off when the voltage at the CCAP and/or DCAP
pins falls below VGATE_UV.
By turning off the FETs quickly, the system avoids the condition of insufficient gate drive due to low battery
voltage. (If the FET gate drive is not high enough, the power components may not be in their linear operating
region, and could overheat due to resistive losses at high load currents).
In the case of a system undervoltage condition, both FETs are disabled within 500 µs maximum; in all cases the
FET fall time is less than fall time specified in the Electrical Characteristics section (FET Drive). During initial
power up, once the UVLO threshold has been reached and the IC powers up fully, the rise time of the FET gate
drive signal is also < 200 µs. This assumes a nominal gate capacitance of 50 nF as specified in the Electrical
Characteristics tables.
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NOTE
Selection of power FETs should consider the resistive losses that may occur during the
undefined voltage range during power up from a complete collapse of battery voltage and
holdup capacitance.
INITIAL POWER UP
Cell Connection
The IC design allows connection of the cells in any order. For EEPROM programming, only the VSS and BAT
terminals must be connected to allow the device to communicate using the serial communication interface.
For normal pack assembly, the recommended connection procedure is to start with the VSS connection, followed
by the (+) terminal of the lowest (most negative) cell, and continuing up the stack to the top (most positive) cell.
The BAT voltage shown in Start-Up Timing assumes this connection sequence is used.
Power-Up Sequence and Continuous Fault-Detection Logic
The bq77910 goes through a fixed set of safety checks on each power-up sequence. The same checks are
performed on each recovery cycle from the SHUTDOWN state (after a charger is detected).
For each power up, the following tests are made. If any of the conditions indicate a fault, the IC goes into the
appropriate protection state. In some cases, in shutdown mode, the IC internal logic remains powered up with the
LDO ON, and the fault can be cleared automatically. In other cases, external connections may be required (such
as load removal or insertion into charger). The device goes through a power-up sequence in < 100 ms, assuming
no faults exist.
After the release of the internal digital reset, the logic begins a power-up safety check. Two internal signals,
designated PWRUP_SAFE_CHK and PWRUP_DONE, control the sequence.
When PWRUP_DONE is low, the following conditions are forced:
1. CHG and DSG external pins / gate drive signals are low.
2. UV_HYST = HI (internal logic signal – use hysteresis level above UV threshold to clear fault)
3. OV_HYST = HI (internal logic signal – use hysteresis level below OV threshold to clear fault)
After 50 ms of time has elapsed, a pulse of PWRUP_SAFE_CHK performs a check of each of the following
circuits (with all time delays disabled):
1. UV comparator
2. OV comparator
3. OCD comparator
4. SCD comparator
If a fault condition was found for any of the circuits, an internal fault status bit is set. For another 50 ms, the
circuit has a chance to recover if the sample was corrupted. At the end of 100 ms, the PWRUP_DONE signal is
released. If no faults exist, the CHG, DSG, UV_HYST, and OV_HYST return to their normal-mode state.
Several of the protection circuits were not included in the power-up sequence (SCC, OT, TS, TO, OC). These
faults are checked after the power-up sequence is completed. Note: Because the digital logic is not reset in
shutdown mode with LDO on, this check is only performed on a power up from LDO-off or a digital reset
occurring (i.e., POR state).
Start-Up Timing
The following timing diagrams refer to signals at the device pins as well as to the following INTERNAL logic
signals.
• BAT_UVLO = HI when the BAT pin is below the POR threshold (undervoltage lockout).
• WAKEUP = HI whenever a charger is attached.
• UV_STATUS = HI when n UV condition has been detected.
• OV_STATUS = HI when an OV condition has been detected.
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EEPROM CONFIG SHTDIS = 0 (LDO off in SLEEP mode)
5.6 V
BAT
• BAT voltage rises as individual cells are connected
from stack bottom to top.
• In this example, one (arbitrary) cell is below the cell
UV threshold on initial connection.
BAT_UVLO
WAKEUP
CHG_DETECT
VREG
UV_HYST
OV_HYST
PWRUP_SAFE_CHK
PWRUP_DONE
UV_STATUS
UV fault condition detected ~50 ms after power up
OV fault not detected
OV_STATUS
DSG
CHG
DSG FET remains off until UV condition is no longer present
CHG FET enabled ~100 ms after power up with no OV fault
Figure 4. Initial Power Up With Single-Cell UV Fault
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Initial power up with normal conditions (no fault)
EEPROM CONFIG SHTDIS = 0 (LDO off in SLEEP mode)
5.6 V
• BAT voltage rises as individual cells are connected
from stack bottom to top
BAT
BAT_UVLO
WAKEUP
CHG_DETECT
VREG
UV_HYST
OV_HYST
PWRUP_SAFE_CHK
PWRUP_DONE
UV_STATUS
OV_STATUS
DSG
CHG
• DSG and CHG FETs enabled ~100 ms after power up
Figure 5. Initial Power Up With Normal Conditions (No Fault)
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Table 2. Fault Detection, Action, and Recovery Condition Summary
Action Taken
Fault Condition
CELL
OVERVOLTAGE
CELL UNDERVOLTAGE
Fault Detection
Parameter
Any cell > VOV
Any cell < VUV
Filter Time
FET
MODE
tOV
CHG
DSG
OFF
ON
EEPROM Config
(if Applicable)
OV FAULT protection state
OV_TS_CTRL = 0
EXT CHGR DISABLE
(TS pin→low)
OV_TS_CTRL = 1
All cells < OV-hyst
OFF (1) (2)
OFF
UV FAULT protection
state (3)
UV_REC bit = 0
1) Both FETS ON when all cells >UV +
hyst (4)
2) CHG FET enabled immediately if
charger detected
OFF (5) (2)
OFF
UV FAULT protection
state (3)
UV_REC bit = 1
1) Both FETs enabled when all cells
>UV + hyst AND load removed
2) CHG FET enabled immediately if
charger detected
OFF
OFF
TMP_REC bit = 0
VTS > VHOT + hysteresis (6)
TMP_REC bit = 1
VTS > VHOT + hysteresis (6) and load
removed
SOR bit = 0
Both ON when load removed
SOR bit = 1
Both ON when load removed AND
charger detected
SOR bit = 0
Both ON when load removed
SOR bit = 1
Both ON when load removed AND
charger detected
tUV
PACK OVERTEMPERATURE
Pack temperature out
of range,
VTS < VHOT
(1-2) × tTHERM_CHECK
OVERCURRENT
IN DISCHARGE
(VSC – VSS) > VOCD
SHORT CIRCUIT
IN DISCHARGE
Recovery Conditions
OT FAULT protection state
OFF
OFF
tOCD
OFF
OFF
(VSC – VSS) > VSCD
tSCD
OFF
SHORT CIRCUIT
IN CHARGE
(VSS – VSC) > VSCC
tSCC
OFF
OFF
SCD FAULT protection
state
N/A
Charger removed
OPEN
THERMISTOR
VTS > VTH_OPEN
(1 to 2) × tTHERM_CHECK
OFF
OFF
OPEN THERM /
UNDERTEMP protection
state
N/A
VTS < VTH_OPEN – VTH_HYST (6)
VTS < VTH_SHORT
(1 to 2) × tTHERM_CHECK
SHUTDOWN (low-power
state)
SHTDIS = 0
SHORTED
THERMISTOR
OFF
OFF
Charger detected and VTS > VTH_SHORT
+ VTH_HYST (6) (7) (8)
SHORTED THERM
protection state
SHTDIS = 1
Charger detected and
VTS > VTH_SHORT + VTH_HYST (6) (9)
SHUTDOWN (low-power
state)
SHTDIS = 0
Charger detected and open-cell
condition absent > filter time (10)
PERMANENT FAILURE
protection state (force FETs
OFF)
SHTDIS = 1
Complete power cycle (disconnection
of BAT and all cell voltages)
OPEN CELL
INPUT
Cell-to-pin impedance
> ROPEN_CELL
(1 to 2) ×
tOPEN_CELL_CHECK
OFF
OFF
OFF
OCD FAULT protection
state
SCD FAULT protection
state
(1)
The LDO is turned off in the SHUTDOWN mode if the SHTDIS bit = 0. The LDO function remains active during SHUTDOWN mode if the
SHTDIS bit = 1. When the LDO is disabled, the CHG FET drive output is OFF by default, as all outputs of the device are disabled.
(2) Regardless of EEPROM setting, if a battery pack in the UV protection state is inserted into a charger, (charger presence is detected),
the CHG FET is turned ON to allow recharge of the pack. The DSG FET is turned on after UV recovery, as noted in Table 2 (conditions
based on EEPROM setting).
(3) a) If UV_REC_DLY = 1 and any cell remains < UV + hyst for longer than 8 seconds, the device enters SHUTDOWN mode and requires
insertion into charger to recover. If UV_REC_DLY = 0, the device does not enter SHUTDOWN mode from the UV FAULT protection
state.
b) The LDO is turned off in the SHUTDOWN mode if the SHTDIS bit = 0. The LDO function remains active during SHUTDOWN mode if
the SHTDIS bit = 1. In both cases, charger insertion is required to recover from the SHUTDOWN mode.
CAUTION: Care should be taken when using UV_REC = 0, because the power MOSFETs can oscillate when high load currents cause
repeated cell UV conditions, which could result in overheating of cells or MOSEFETs.
(4) If the UV_HYST_INH bit = 1, then the hysteresis threshold is inhibited and recovery occurs whenever the cells exceed the UV threshold
(without hysteresis). If UV_HYST_INH = 1, the UV_REC bit should also be configured = 1. Otherwise, UV fault / recovery modes may
chatter without hysteresis.
(5) If the LDO is left ON, the CHG FET is disabled when the fault condition occurs and re-enabled as soon as a charger is attached. The
DSG FET does not re-enable until the UV condition is cleared (Vcell > Vuv + hysteresis).
(6) Recovery occurs within tTHERM_CHECK after recovery conditions are met.
(7) If a thermistor short occurs while charger is not detected, the FETs initially are re-enabled when charger is detected. If short condition is
still present tTHERM_CHECK after charger detection and CHG_TMP_DIS = 0, the FETs re-open until the short condition is removed. If
CHG_TMP_DIS = 1, the FETs remain enabled regardless of the short condition.
(8) If a charger is presently detected when the shorted thermistor fault is registered, the LDO does not shut off. Within 0 to 4 seconds after
the short is removed, the FETs re-enable and the device recovers. However, if the charger is disconnected after the short is removed,
but before the FETs are re-enabled, the device will shut down with the LDO off and require charger detection for recovery.
(9) If CHG_TMP_DIS = 1, the FETs are re-enabled immediately on charger insertion.
(10) If an open-cell fault occurs while a charger is detected, the device does not shut down. However, the device does shut down if the
charger is later disconnected while the open-cell condition is still present. If the charger is disconnected after the open-cell condition is
removed, the device recovers (i.e., FETs are re-enabled). Following a shutdown caused by an open-cell condition, the FETs initially
re-enable when a charger is detected. However, if the open-cell condition is still present, the FETs re-open after the filter time.
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CELL-BALANCING FUNCTION
The bq77910 implements an internal cell-balance control circuit and power FET structure. Because no CPU is
available to manage a complex algorithm, a simple and robust hardware algorithm is implemented.
Overview
•
•
•
•
•
Uses a separate comparator to check if cells have reached the balancing threshold to start balancing (i.e.,
does not use the OV trip comparator)
Balance and charge can run concurrently – no charge-time extension
Compare cell voltages – cell with highest voltage is bled off for time tCELL_BAL_CHECK.
Balancing current set by RVCX – effect of balancing current on cell-to-cell voltage differential depends on cell
capacity and tCELL_BAL_CHECK.
Cell-balancing options programmable – balancing threshold, when to balance (always, only during charge, or
never), and how long to balance
Control Algorithm Description
•
•
•
•
Potential balancing action is updated (latched) every minimum dwell time tCELL_BAL_CHECK
1. Action = bleed highest cell above cell-balance start voltage [Note: no hysteresis]
2. Only one cell is bled at a time
3. A minimum dwell time of 7.5 minutes equates to <0.5% capacity at 2 Ah and 50 mA balancing current)
4. Calculation of potential balancing action is reset/inhibited when timer is expired to minimize current draw
on the cell stack in case of charger termination
Balancing action is suppressed if any of the following are true:
1. Highest cell voltage < cell-balance start voltage
2. Balance timer has expired (when configured for balancing time-out)
3. Charger is not detected when configured to balance only in charger
4. Cell-voltage measurement is active
Balancing action inhibited during cell measurement
1. Measure for 50 ms, balance for 200 ms per each 250-ms cycle (80% utilization)
2. Cell measurements are frozen when balancing output is asserted
3. OV, UV protection delay time is constrained to be 500 ms or longer
4. Cell balancing is suspended when an OV/UV condition is present and is being timed for fault
determination (maximum time for OV = 2.25 s; UV = 32 s).
5. Cell balancing is resumed after the fault checking has been completed, whether faults are cleared or
latched
Recommended system design – charger continues to top up the pack when connected
1. This may not be the case with certain chargers which shut down once charge current taper limit is
reached.
2. Timer should be enabled to prevent balancing from discharging the pack (maximum balance time is
limited).
3. Timer value is selectable via EEPROM (1, 2, 4, or 8 hours).
4. Timer value of 4 hours limits discharge of 4-cell pack to ~2.5% at 2 Ah and 50-mA balance current;
10-cell pack to ~1% at 2 Ah and 50-mA balance current.
5. Initialize timer when balancing action starts (first cell voltage > cell balance-start threshold).
6. Suspend balancing immediately if charger is disconnected.
Balancing Algorithm Configurable Parameters
•
•
•
22
Cell-balance start voltage: 4 bits, 3.9 V–2.4 V in 0.1-V increments, default = 3.9 V
Cell-balance enable / control: based on charger present, timer expiration, or both (See EEPROM map for
details)
Time-out value (optional): 2 bits: 1, 2, 4, 8 hours
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External Connections for Cell Balancing
Multiple options are supported for different cell-balancing requirements. These are summarized in the following
sections. These diagrams do NOT show the other external connections such as BAT, TS, CHGST, or power FET
arrangements. See subsequent sections for more complete application diagrams showing all external
connections.
Normal Configuration – Balancing With Internal FETs
The basic cell balancing-configuration is shown here. Balance current must be limited using external resistance.
Resistive component sizes limit the balance current as the return current flows through the VCx pins. Because
resistor values are relatively low (to allow sufficient balance current), it may be necessary to maximize external
capacitor sizes, depending on the filtering requirements.
50 W
VC1
CB1
1µF
50 W
VC2
CB2
1µF
50 W
VC3
Cell Measurement /
Interface Circuits
50 W
VC9
CB9
1µF
50 W
VC10
CB10
1µF
50 W
VC11
Figure 6. Typical Balancing Configuration (~50 mA)
Low-Current Cell Balancing – External Filtering for Cell-Voltage Readings
To limit balancing current further, the external series resistance can be increased as shown. Balancing can be
fully disabled by setting EEPROM bit CB_EN = 0 if desired.
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VC1
CB1
0.1 mF
1000 W
VC2
CB2
0.1 mF
1000 W
VC3
Cell Measurement /
Interface Circuits
1000 W
VC9
CB9
0.1 mF
1000 W
VC10
CB10
0.1 mF
1000 W
VC11
Figure 7. Typical Low-Current Balancing Configuration (~2 mA)
High Current (Approximately 100 mA–150 mA) Balancing Using External Power FETs
In this example, external PMOS devices are driven from the IC internal NMOS balance FETs. Current limiting is
controlled by the external resistors and is on the order of 100 to 150 mA, depending on cell voltage. Contact TI
for application example.
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APPLICATION INFORMATION
Internal Voltage Regulator
The bq77910 has an integrated low-power linear regulator that provides power to both internal and any optional
user-defined external circuitry. The input for the regulator is derived from the BAT terminals. VREG nominal
output value is 3.3 V and is also internally current-limited. The minimum output capacitance for stable operation
is 1 µF.
When the SHTDIS bit = 1, the LDO regulator remains enabled when the part enters the SHUTDOWN mode.
When SHTDIS bit = 0, the regulator (and the IC internal circuitry) is disabled during the SHUTDOWN mode.
When the regulator circuit is disabled (including the time during the power-up sequence of the IC) the DSG and
CHG FETs are driven OFF.
Charger Detection and Wake-Up
The bq77910 contains a mechanism to detect the presence of an external charger and allow the device to wake
up from the low-power shutdown mode when the LDO has been turned off. A low-power wake-up circuit monitors
the CHGST pin to determine the charger connection event.
CHGST Pin Detection
Because the bq77910 is designed to use low-side NMOS FETs to control current flow to / from the battery pack,
charger presence detection cannot be determined simply by checking the positive terminal voltage. To allow
detection of the presence / absence of an external charger under any operating conditions, the bq77910
implements a charger sense pin, designated CHGST. If a voltage of greater than (nominally) 0.5 V is detected at
the CHGST pin, the bq77910 logic assumes that a charger has been connected. The voltage monitoring circuit at
the CHGST pin is an always-on subsystem within the chip. When the proper voltage appears at the CHGST pin,
the IC wakes up from the SHUTDOWN mode after a charger is connected. If fault conditions exist, the part may
re-enter a low-power or SHUTDOWN state, depending on the configuration.
The means of connecting the CHGST pin is user- and application-dependent, and may vary with the external
contact structure of the battery pack.
For example, a dedicated CHARGER(+) contact with attenuating resistors can be used such that the CHGST pin
is pulled high whenever the pack is inserted into a charger.
For a system/application which uses a charge-protection FET to disconnect the charger (–) during a fault
condition, it is recommended that the connection to the CHGST pin be pulled up to the charger (+) potential
(using a pullup resistor) on the charger side to prevent this signal from going negative with respect to the pack
internal reference (VSS pin) when the charge FET in the battery pack may be open.
If the system does not use a charge FET within the battery pack, the VSS (internal) reference and CPCKN
(charger reference) are the same, which allows CHGST to be pulled up to any logic-high level above VCHG_DET1
to detect charger insertion.
A timing diagram corresponding to the UV fault/recovery condition using the CHGST signal is shown in Figure 8.
CPCKN Pin Detection
When the device is shut down with LDO off, a potential less than approximately VSS – 2 V applied to CPCKN
causes the LDO to turn on and the power-up sequence to commence. However, the power-up state is not
latched, and if CPCKN falls above the VSS – 2 V threshold, the device again shuts down.
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Normal Operation
UV Fault on VCELLx
Charger connection
(SHTDIS = 0)
VCx
UV Threshold + Hysteresis
UV Threshold
UV_HYST
Fast turnoff of discharge FET
Discharge FET re-enabled after cell voltage rises
above UV Threshold + Hysteresis
DSG
Go to SLEEP state after UV fault
WAKEUP
Fast turnoff of charge FET before disabling LDO
CHG
Charge FET re-enabled after charger detection
Disable VREG after entering Power Down Sleep
VREG
IC wakeup re-enable VREG LDO when charger detected
UV_STATUS
UV fault cleared after cell rises
above UV Threshold + Hysteresis
Charger Insertion
CHGST
Figure 8. Normal Operation, UV Fault on VCELLx, Then Charger Connection
Temperature Sensing
TS and VTSB Pin Interface
The bq77910 uses the TS pin input to read the voltage on an external thermistor to determine the pack/system
temperature. The VTSB pin allows the IC to generate its own bias voltage to drive the thermistor. To save power,
the VTSB bias supply is pulsed ON only when the temperature readings are being taken. The VTSB pin is
powered by the LDO output (VREG) and with a maximum output impedance of 150 Ω.
VREG
3.3 V LDO
R T_PU
VTSB
COMP
TS
RT
NTC
THERMISTOR
CT
1 mA
Thermistor
Check
NTC/ Charger
Disable
Figure 9. TS and VTSB Pin Interface
26
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A negative-temperature-coefficient thermistor in the topology shown in Figure 9 is assumed. With this
arrangement, the voltage at the TS will be lower for high temperature, and higher for low temperature. If the
voltage measured at the TS pin is below the VHOT threshold, a pack overtemperature condition is detected.
In the extreme fault cases, an open (disconnected) thermistor indicates a voltage at the TS pin equivalent to the
VREG pullup voltage, and a shorted thermistor indicates a voltage close to 0 (VSS). An open-thermistor fault
recovers within the fault filter time following removal of the open condition. Shorted-thermistor detection places
the device into the low-power SHUTDOWN mode, requiring re-insertion into a charger for wakeup.
External Bias Supply Detection
During the time period in which the bq77910 checks the thermistor status, a weak (nominal 1-µA) current is
applied from the TS pin to VSS. If V_TS > V_EXT_PU, then the IC operates as if an external supply is present
and does not enable the VTSB internal supply. A sequence of operations is performed to determine the
existence of shorted thermistor, open thermistor, or pack overtemperature faults as listed in the following section.
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Temperature Measurement / Fault Detection Logic Flow Diagram
Initialize threshold selector
Disable VTSB
Enable CHGST detection
Release delay timer
Update otherm_hit with
comparator output.
Clear open thermistor status
if necessary.
Turn on 1-mA pulldown
Wait 50 ms
Increment threshold selector
Restart delay timer
Wait 50 ms
Is VTS <
VEXT_BIAS_DET ?
NO
Is VTS < VTH_SHORT
AND previous
check (stherm_hit)
=1?
YES
Set the VTSB enable on
disable CHGST detection
logic
NO
YES
Set short thermistor status
Wait to complete cycle time
Increment threshold selector
Restart delay timer
Update otherm_hit with
comparator output.
Clear open thermistor status
if necessary.
Wait 50 ms
Increment threshold selector
Restart delay timer
Wait 50 ms
Is VTS > VTH_OPEN
AND previous
check (otherm_hit)
=1?
YES
Set open thermistor status
Wait to complete 4-s cycle
time
NO
Is VTS< VTH_HOT
AND previous
check (otemp_hit) =
1?
NO
YES
Set overtemperature status
28
Update otherm_hit with
comparator output.
Clear open thermistor status
if necessary.
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Battery Pack / Charger Shared-Thermistor Functionality
The pulsing of the VTSB pin is enabled ONLY when the IC determines that there is no external supply (e.g., from
the charger) already driving the thermistor. This allows a single thermistor to be used by both the bq77910 and
the external charger to measure pack temperature. This can also be used as a method of charger presence
detection in case a dedicated charger-detect pin is not implemented in the end-equipment pack design.
By connecting the CHGST pin to the TS pin on the battery-pack internal circuit board, a three-terminal
battery-pack design with (+), (–) and (T) (thermistor) contacts is compatible with the charger-detection
mechanism of the bq77910. Because the external charger normally applies a bias voltage to the TS pin from an
external source, there is a voltage present on the CHGST pin whenever the pack is inserted into the charger.
NOTE
VTH_xxx (thresholds) are ratiometric based upon VREG. Care should be taken if using an
external pullup to a voltage other than the VREG voltage to account for the difference in
these detection thresholds.
Depending on the arrangement of the power FETs within the pack, the sharing of a
common thermistor between the BMU and the external charger may not be feasible.
Applications which do not use a CHG disconnection FET are supported, because there is
a common ground reference between the external charger and the internal IC ground.
In case of applications which do use a CHG FET, the following issues should be understood from the system
point of view:
• When the CHG FET is disabled (as in a fault condition), the internal reference (VSS pin of the IC) is
disconnected from the external reference (CPCKN connected to charger return path).
• When a charger is connected and powered on, the CPCKN voltage is negative, and it is possible that the
CHGST pin is negative with respect to the IC VSS pin.
• The CHGST and TS pins are not internally protected from negative voltages.
• If an external clamp circuit is used to prevent the CHGST voltage from going below 0 V with respect to VSS,
and the CHGST/TS pins are connected within the pack, the TS pin indicates an invalid temperature range (or
perceived thermistor-shorted fault) until the CHG FET is closed.
• If a charger is connected and not powered on, the CHGST pin may be pulled up to the PACK+ rail. This pin is
internally clamped to a safe voltage; however, series resistance is required to avoid overcurrent damage to
the internal clamping circuit. If the CHGST and TS pins are tied together within the pack, this resistance
affects the reading of the pack internal thermistor by the external device.
• Ideally, the external charger should be designed such that a negative voltage (with respect to the pack
internal VSS) cannot be imposed on the CHGST/TS pin when a charger is connected.
• In the case of the CHG FET ON and current flowing, the CPCKN potential may be a few hundred millivolts
below the IC VSS pin (depending on charge current level and charge FET on-resistance). This also affects
the accuracy of the thermistor voltage as read by the external charger. A suggested approach is for the
external charger to momentarily interrupt charge current flow while taking the pack temperature reading when
a CHG FET is implemented.
Charge / Discharge Enable Operating Thresholds
If the voltage measured at the TS pin is below VTH_HOT, a pack overtemperature condition is detected. The
bq77910 disables the charge and discharge FETs (but remains in the active mode). Using a standard 103AT
thermistor and 10-kΩ pullup resistor, this corresponds to approximately 60°C. The temperature level is chosen to
be slightly above the normal charge disable level implemented by an external charger, and would not normally
activate during charge unless the charger's own overtemperature shutdown did not trigger before this level. The
external charger typically also has a cold-temperature charge inhibit (roughly between 0°C and 10°C) as shown
in Figure 10.
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3.5
V_OPENTHERM/UNDERTEMP
3
V_TS
V_COLDDELAY
(typical - set by charger)
2.5
2
VTSB = 3.3 V,
pullup = 10 k
1.5
V_HOTDELAY
V_SHORTED
1
0.5
0
-40
-20
0
20
40
60
80
100
Figure 10. Typical Thermistor Response and Protection Thresholds (VTSB = 3.3 V, Pullup = 10 kΩ)
The bq77910 limits pack operation in the case of an overtemperature, undertemperature, open, or shorted
thermistor. An overtemperature fault opens the protection FETs only; a shorted-thermistor fault also puts the
device into low-power / fault protection mode. Due to the range of resistance values available with a typical
thermistor, an undertemperature fault is indistinguishable from an open-thermistor fault and has the same
protection mechanism (enter protection state, but device stays awake). The VTH_OPEN, VHOT, and VTH_SHORT
thresholds are ratiometric to the VTSB pin bias voltage. Typical values are shown; see the parametric tables for
details.
OV_TS_CTRL (EEPROM Bit) Interface
In the case of a battery pack which implements a CHG pass FET, the charging function can be disabled by
opening the FET during fault conditions. However, in the case of a design which does not implement a CHG
pass FET, use of the EEPROM bit OV_TS_CTRL can allow the bq77910 to communicate an overvoltage fault
condition to the external charger.
Assuming that the charger uses the thermistor located within the battery pack (which is also connected to the TS
pin), if the OV_TS_CTRL bit is set to 1, the TS pin is pulled to VSS whenever an OV fault occurs. The result is
that the external charger reads a thermistor value equivalent to a hot battery condition and suspends charging.
When the bq77910 is pulling the TS pin to ground, the CHGST detection function is momentarily disabled as
noted in the Temperature Measurement / Fault Detection Logic Flow Diagram section. If the OV_TS_CTRL bit is
set to 1, the TS line is pulled to ground regardless of the state of the CHG_TMP_DIS bit (the TS pulldown
functionality is implemented based on OV fault condition, even if internal temperature monitoring is disabled).
When TS is pulled down, charger-presence detection still operates on a sampled basis. The TS pin is released
for 200 ms out of every 4 seconds to test for an external charger connection.
UV Fault – Secondary Delay Function (See Also Cell Undervoltage Detection and Recovery)
When an undervoltage fault occurs (any cell voltage < VUV) and remains for a time exceeding the UV fault delay
timer (tUV), then the discharge FET is disabled (opened) to stop the discharge current.
Recovery depends on the configuration of the UV_REC bit: If UV_REC = 0, then recovery occurs when all the
cell voltages are > VUV + hysteresis, which could be almost instantaneously if the load current is high and the
cells still contain capacity. Care should be taken when using UV_REC = 0, as it can cause the FETs and
cells to overheat if threshold settings are not properly considered.
If UV_REC = 1, then all the cell voltages must be >VUV + hysteresis, AND the load must also be removed.
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Additionally, if UV_REC_DLY = 1 and all the cell voltages remain <VUV + hysteresis for more than 8 seconds,
then the bq77910 enters the SHUTDOWN mode.
If UV_REC_DLY = 0, the part does not enter SHUTDOWN mode from a UV fault condition.
Once in the SHUTDOWN mode, insertion into a charger is required to exit the SHUTDOWN mode.
When in the SHUTDOWN mode, the SHTDIS bit sets the operation of the onboard LDO (VREG output): SHTDIS
= 1 keeps the LDO on, whereas SHTDIS = 0 turns the LDO off.
This recovery criterion is described in the fault summary of Table 2 and the Cell Undervoltage Detection and
Recovery section.
Pack/System Connection Arrangements
The architecture and fault detection/recovery logic allows the system developer to implement multiple types of
battery-pack topologies using the bq77910. A few basic application cases are illustrated here; however, others
are also possible as long as the external connections and host-equipment interface are compatible with the fault
detection and recovery signaling methods.
Notes regarding the application schematics:
• A five-cell configuration is shown for simplicity. All unused cell inputs (not shown) are tied to the PACK(+)
positive terminal.
• For configurations which do not implement a CHG FET, it is assumed that the CHGST pin (in bq77910A) is
pulled up inside the charger equipment (nominally VCHG_DET1).
• Gate-source pulldown resistances are recommended for the power FETs to prevent parasitic turnon when the
bq77910 is in shutdown mode. This may have a slight impact on operating current when FETs are enabled;
however, very large resistances (~ 5 MΩ) may be used to minimize this effect.
• Series resistance between the CHG/DSG pins and FET gates should be sized to assure quick turnoff of the
FETs used.
• High-current (pack discharge/charge) flow paths are indicated by wide traces; low-current signal paths use
narrow traces in the following schematics.
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Series CHG and DSG FET Configuration
Use of a separate contact (i.e., CHGST) for charger detection is preferred if the cell-balancing function is used.
This is to allow balancing to occur only while charging. Otherwise, if the part cannot detect the presence of a
charger, balancing must be enabled to occur at all times or not at all. The CHGST pin should be protected from
possible negative voltage inputs which may occur if connected to a charger with the CHG FET open.
Note that in shutdown with the LDO off, the specified shutdown currents require that the voltage at
CPCKN with respect to VSS is controlled. In the parallel FET case, CPCKN is clamped through the body
diode of the charge FET. In the series FET case, external circuitry is required to keep CPCKN from
floating. Contact TI for recommended application circuits.
If current is able to flow from CPCKN through the charge FET (e.g., through the body diode), the resistor
RLDRM_DET is required to discharge DPCKN for proper detection of load removal. When the FETs are open and a
load is present, the PACK– terminal and consequently DPCKN is pulled up to PACK+. When the load is
removed, DPCKN is discharged through RLDRM_DET. Detection of load removal occurs when the voltage at
DPCKN (referenced to VSS) falls below 2 V (typical).
PACK(+)
BAT
VREG
3.3-V LDO
VTSB
VC6
RVCX
TS
CVCX
VC7
1 mA
RVCX
Thermistor
Check
NTC / Charger
Disable
CVCX
VC8
bq77910
Cell Monitoring and Control Subsystems
RVCX
CVCX
VC9
RVCX
CVCX
CHG_DET
VC10
CHGST
RVCX
1000 W
COMP
CVCX
RVCX
VC11
COMP
REF
(AGND)
1 kW
1 mW
PWR
(PGND)
SENSE (+)
COMP
0.1 mF
SENSE (–)
1 kW
DSG FET
NMOS DRIVER
0.1 mF
CHG FET
NMOS DRIVER
RLDRM_DET
RDPCKN
CHG
REF
(AGND)
CPCKN
CCAP
DPCKN
DSG
DCAP
VSS
RCPCKN
PACK(–)
Figure 11. Example Series FET Configuration Using the CHGST Pin
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Separate CHG(–) and DSG(–) Return Paths With Both FETs
In this configuration, if the charge current is typically much lower than the discharge current, a lower-cost
component can be used for the charge control FET than in the series configuration previously shown.
Use of a separate contact (CHGST pin) is preferred if the cell balancing function is used. This is to allow
balancing to occur only while charging. Otherwise, if the part cannot detect the presence of a charger, balancing
must be enabled to occur at all times or not at all.
The CHGST pin should be protected from possible negative voltage inputs which may occur if connected to a
charger with the CHG FET open.
PACK(+)
BAT
3.3-V LDO
VREG
VTSB
VC6
RVCX
TS
CVCX
VC7
1 mA
RVCX
NTC / Charger
Disable
CVCX
Thermistor
Check
VC8
bq77910
Cell Monitoring and Control Subsystems
RVCX
CVCX
VC9
RVCX
CVCX
CHG_DET
VC10
CHGST
RVCX
1000 W
COMP
CVCX
RVCX
VC11
COMP
REF
(AGND)
1 kW
1 mW
PWR
(PGND)
SENSE(+)
COMP
0.1 mF
SENSE(–)
1 kW
DSG FET
NMOS DRIVER
0.1 mF
CHG FET
NMOS DRIVER
CHG
N
REF
(AGND)
CPCK
CCAP
DPCKN
DSG
DCAP
VSS
RDPCKN
RCPCKN
DSG(–)
CHG(–)
Figure 12. Example Parallel (Split) Power Path FET Configuration Using CHGST Pin
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Separate CHG(–) and DSG(–) Return Paths With DSG FET Only
In this configuration, no charge-control FET is implemented. As a result, the bq77910 is unable to interrupt
charge current when an overvoltage condition occurs. The suggested method to stop the charger in an
overvoltage event is to use the thermistor signal to indicate a fault condition. The system should configure the
OV_TS_CTRL bit high, so that when an overvoltage occurs, the charger detects that an overtemperature
condition has occurred, and halts charging. (See the OV_TS_CTRL (EEPROM Bit) Interface section.)
PACK(+)
BAT
3.3-V LDO
VREG
VTSB
VC6
RVCX
TS
CVCX
VC7
1 mA
RVCX
NTC / Charger
Disable
CVCX
Configure EEPROM OV_TS_CTRL
bit = 1 to disable charger if OV fault
condition occurs. External charger
shares battery pack thermistor for
temperature monitoring.
VC8
bq77910
Cell Monitoring and Control Subsystems
RVCX
Thermistor
Check
CVCX
VC9
RVCX
CVCX
CHG_DET
VC10
CHGST
RVCX
1000 W
COMP
CVCX
RVCX
VC11
COMP
1 kW
REF
(AGND)
1 mW
PWR
(PGND)
SENSE (+)
COMP
0.1 mF
SENSE (-)
1 kW
DSG FET
NMOS DRIVER
0.1 mF
RDPCKN
CHG
REF
(AGND)
CPCKN
CCAP
DPCKN
DSG
DCAP
VSS
CHG FET
NMOS DRIVER
RCPCKN
DSG(–)
CHG(–)
Figure 13. Example Split Power Path With No Charge FET Using the CHGST Pin
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Common Return Path With No FETs
If no internal FETs are implemented inside the battery pack, the only means of protection available is for the
bq77910 control signals to be used as signals to the external device (tool or charger). These signals must be
used by the external equipment to control the interruption of current flow in case of a fault condition. When no
charge FET is implemented, the CHGST signal interface must be used to indicate to the battery pack that a
charger has been connected.
In this configuration, an overvoltage fault is distinguished from an undervoltage fault by observing that during an
overvoltage fault only the DSG control switches low, while during an undervoltage fault, both the DSG and CHG
controls switch low.
If the OCD/SCD/SCC (overcurrent/short-circuit) protections are used in this configuration, the part cannot
interrupt current flow. The fault detection auto-recovers because the DPCKN pin is seen at ground potential
(which is the normal indication that the external load has been disconnected). The system may cycle into and out
of fault protection mode depending on external conditions, so the host-equipment designer should be aware of
this potential situation.
PACK(+)
BAT
3.3-V LDO
VREG
VTSB
VC6
RVCX
TS
CVCX
VC7
1 mA
RVCX
NTC / Charger
Disable
CVCX
Thermistor
Check
VC8
bq77910
Cell Monitoring and Control Subsystems
RVCX
CVCX
VC9
RVCX
CVCX
CHG_DET
VC10
CHGST
RVCX
1000 W
COMP
CVCX
RVCX
VC11
COMP
REF
(AGND)
1 kW
1 mW
PWR
(PGND)
CHG
SENSE (+)
COMP
0.1 mF
10 kW
SENSE (–)
1 kW
DSG FET
NMOS DRIVER
0.1 mF
CHG FET
NMOS DRIVER
RDPCKN
CHG
REF
(AGND)
DSG
CPCKN
CCAP
DPCKN
DSG
DCAP
VSS
10 kW
RCPCKN
PACK(–)
Figure 14. Single Power Path, No FETs
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4 to 10 Series Cell Configuration
All cell input pins of the device are used for a 10-cell battery pack application. The bq77910 supports pack
configurations ranging from 4 to 10 series cells. If fewer than 10 cells are used in an application, all unused VCx
cell input pins should be tied together and pulled up to the most-positive cell input. Pullup resistance value is not
critical; a 100 Ω–1000-Ω value is suggested. An example for a 5-cell application is shown here. Cell configuration
is programmable by EEPROM, using the SYS_CFG register bits CNF[2:0].
PACK(+)
BAT
VC1
10
µF
VC2
VC3
VC4
VC5
VREG
100 O
50 W
VTSB
VC6
TS
1µF
50 W
VC7
bq77910
1µF
50 W
VC8
1µF
50 W
VC9
CHG_DET
1µF
50 W
VC10
CHGST
1000 W
1µF
50 W
REF
(AGND)
VC11
SENSE (+)
1 kW
0.1 µF
0.1 µF
PWR
(PGND)
SENSE(-)
1 kW
CHG
CPCKN
100 W
CCAP
DPCKN
DSG
DCAP
VSS
REF
(AGND)
100 W
DSG(–)
CHG(–)
Figure 15. Unused VCELLx Pin Configuration
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Delay Time Zero
The ZEDE pin enables the EEPROM-programmed detection-delay times when connected to VSS (normal
operation). A strong pulldown to VSS is recommended to prevent external circuit noise from causing ZEDE to go
high. The detection delay time is set to minimum when this pin is connected to VREG. This is used in battery
manufacturing test. When programming the EEPROM, this pin should to be connected to VREG to enable the
serial communication interface.
Ship-Mode Equivalent Functionality
Because the BMU is designed for standalone-mode operation, it does not incorporate a programmable-entry ship
mode, which is intended for long-term storage of a battery pack after initial assembly.
The recommended method to allow an equivalent functionality is to cause the IC to enter into the low-power
shutdown state with the LDO disabled. When the end-user first receives the battery and system, the pack must
be (at least momentarily) inserted into a charger to wake up the BMU and allow normal operation. The following
procedure can be used:
1. Configure EEPROM bit SHTDIS = 0 to turn off all functions fully when entering low-power mode.
2. Simulate a fault condition by driving TS pin voltage < VTH_SHORT by either method:
(a) After pack assembly, connect the TS pin to VSS for > 8 seconds, or
(b) Disable delay time (pull ZEDE to logic high) AND connect TS to VSS for > 1 second.
3. As shown in the fault detection/recovery table, the device goes into low-power shutdown mode due to a
perceived shorted-thermistor fault. The LDO may be ON or OFF, depending on the configuration of the
SHTDIS bit.
For battery packs which allow the TS pin signal to be brought to an external contact, the above procedure can be
implemented after final pack mechanical assembly. Use of the TS pin to simulate a fault avoids the risks
associated with forcing a momentary cell UV or apparent OCD/SCD/SCC condition after the pack has been fully
or partially assembled.
SERIAL COMMUNICATION INTERFACE
Device Addressing and Protocol Overview
The bq77910 uses a subset of the I2C communication protocol to allow programming and test of internal
registers. The data is clocked via separate data (SDATA) and clock (SCLK) pins. The bq77910 acts as a slave
device and does not generate clock pulses; it must be addressed and controlled from an external I2C bus master
device. The slave address for the bq77910 has a 7-bit value of 0010 000.
The bq77910 communications protocol varies from the full I2C standard as follows:
• The bq77910 is always regarded as a slave.
• The bq77910 does not support the general code of the I2C specification.
• The bq77910 does not support address auto-increment, which allows continuous reading and writing.
• The bq77910 allows data to be written or read from the same location without re-sending the location
address.
I2C Address +R/W bit
I2C Address
(MSB)
(MSB)
Write
Read
0
0
1
0
0
(LSB)
(LSB)
0
0
0
1
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Bus Write Command to bq77910
SCLK
…
SDATA
A6
…
A5 A4 … A0 R/W ACK
0
0
R7
R5 … R0 ACK
0
R6
Slave Address
Start
…
D7
D6
D5
… D0 ACK
0
Register Address
Stop
Data
Note: Slave = bq77910
bq77PL910
Bus Read Command from bq77910 (Protocol A)
SCLK
…
SDATA
A6
Start
…
A5 … A0 R/W ACK
0
0
R7
…
R6 … R0 ACK
0
A6
Register Address
Slave Address
…
A0
R/W ACK D7
1
0
NACK
Slave Drives
Data
Slave Address
Repeated
Start
Note: SLAVE = bq77910
D6 … D0
Master
Drives
NACK and
Stop
Stop
Bus Read Command from bq77910 (Protocol B)
SCLK
…
SDATA
A6
…
A5 … A0 R/W ACK
0
Start
Slave Address
R7
…
R6 … R0 ACK
0
A6
…
A5 … A0
Register Address
R/W ACK D7 … D0
1
0
Stop
Start
Slave Address
0
Slave Drives
Data
NACK
Master
Drives
NACK and
Stop
Stop
Note: Slave = bq77910
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REGISTER SET AND PROGRAMMING
Memory Map
The bq77910 has 10 programmable EEPROM registers and one RAM register used to access / write the
EEPROM data. The EEPROM bits are used to program the various threshold, delay, configuration, and recovery
control settings. The address, register names, and individual control bit names are shown in the following table.
Descriptions of each individual register and available programming options are provided in the subsequent
sections. Bits labeled RSVDx (gray) are unused and left for future options.
Address
Register Name
0x00
EE_PROG (1)
0x01
SYS_CFG
CNF2
CNF1
CNF0
CHG_TMP_DIS
TMPEN
OT_REC
SHTDIS
SOR
0x02
OV_CFG1
RSVD2
RSVD3
OVT5
OVT4
OVT3
OVT2
OVT1
OVT0
0x03
OV_CFG2
OV_TS_CTRL
OVH2
OVH1
OVH0
RSVD4
OVD2
OVD1
OVD0
0x04
UV_CFG1
UV_HYST_INH
RSVD6
RSVD7
RSVD8
UVT3
UVT2
UVT1
UVT0
0x05
UV_CFG2
UV_REC
UV_REC_DLY
UVH1
UVH0
RSVD10
UVD2
UVD1
UVD0
0x06
OCD_DELAY
RSVD11
RSVD12
RSVD13
OCDD4
OCDD3
OCDD2
OCDD1
OCDD0
0x07
SCD_DELAY
RSVD14
RSVD15
ISNS_RNG
SCDD_RNG
SCDD3
SCDD2
SCDD1
SCDD0
0x08
OCD_SCD_TRIP
SCDT3
SCDT2
SCDT1
SCDT0
OCDT3
OCDT2
OCDT1
OCDT0
0x09
SCC_CFG
SCCD3
SCCD2
SCCD1
SCCD0
SCCT3
SCCT2
SCCT1
SCCT0
0x0A
CELL_BAL_CFG
CB_EN1
CB_EN0
CBT1
CBT0
CBV3
CBV2
CBV1
CBV0
(1)
7
6
5
4
3
2
1
0
VGOOD (1)
Read-only bit.
System Configuration (SYS_CFG, Address 0x01)
Bit Number
Bit Name
7
6
5
4
3
2
1
0
CNF2
CNF1
CNF0
CHG_TMP_DIS (1) (2)
TMPEN
OT_REC
SHTDIS
SOR
If 0
If 1
(1)
(2)
8 possible settings to
determine pack
configuration (4 to 10
cells); see following
table
Default value – thermal
protection active in all
modes
Disable temperature
sensing
Thermal protection
enabled only when no
charger detected; thermal Enable temperature
protection DISABLED
sensing
when CHARGER
PRESENT
Recover from OT fault
when pack has cooled
below limit (incl.
hysteresis)
LDO OFF in
SHUTDOWN
mode
Recover from
OCD/SCD when
load removed
Recover from OT fault
when pack has cooled
below limit (incl.
hysteresis) AND LOAD
REMOVED
LDO ON in
SHUTDOWN
mode
Recover from
OCD/SCD when
load removed and
charger attached
If CHG_TMP_DIS = 1, all thermal faults are cleared when a pack is inserted into a charger.
CHG_TMP_DIS takes priority over OT_REC. If both are = 1, then thermal faults are cleared whenever inserted into a charger.
Pack Configuration (Number of Cells)
Various pack sizes between 4 and 10 series cells are configured using the CNF[2:0] bits as shown.
CNF[2:0]
Pack Configuration (# Cells)
000
10
001
9
010
8
011
7
100
6
101
5
110
4
111
Do not use
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OV Detection Configuration #1 (OV_CFG1, Address 0x02)
Bit Number
Bit Name
If 0
If 1
7
RSVD2
NOT USED
NOT USED
6
RSVD3
NOT USED
NOT USED
5
OVT5
4
OVT4
3
OVT3
2
OVT2
1
OVT1
0
OVT0
Overvoltage trip threshold (64 possible values); see following table.
Programmable Overvoltage Threshold Settings
Using the 5 bits OVT[5:0], up to 64 possible set points for overvoltage trip are possible, as shown. OVT setting is
chosen to match the cell type and application requirements.
40
OVT[5:0]
OV Trip (Volts)
OVT[5:0]
OV Trip (Volts)
0x00
2.800
0x20
3.600
0x01
2.825
0x21
3.625
0x02
2.850
0x22
3.650
0x03
2.875
0x23
3.675
0x04
2.900
0x24
3.700
0x05
2.925
0x25
3.725
0x06
2.950
0x26
3.750
0x07
2.975
0x27
3.775
0x08
3.000
0x28
3.800
0x09
3.025
0x29
3.825
0x0A
3.050
0x2A
3.850
0x0B
3.075
0x2B
3.875
0x0C
3.100
0x2C
3.900
0x0D
3.125
0x2D
3.925
0x0E
3.150
0x2E
3.950
0x0F
3.175
0x2F
3.975
0x10
3.200
0x30
4.000
0x11
3.225
0x31
4.025
0x12
3.250
0x32
4.050
0x13
3.275
0x33
4.075
0x14
3.300
0x34
4.100
0x15
3.325
0x35
4.125
0x16
3.350
0x36
4.150
0x17
3.375
0x37
4.175
0x18
3.400
0x38
4.200
0x19
3.425
0x39
4.225
0x1A
3.450
0x3A
4.250
0x1B
3.475
0x3B
4.275
0x1C
3.500
0x3C
4.300
0x1D
3.525
0x3D
4.325
0x1E
3.550
0x3E
4.350
0x1F
3.575
0x3F
4.375
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OV Detection Configuration #2 (OV_CFG2, Address 0x03)
Bit Number
Bit Name
If 0
If 1
7
OV_TS_CTRL
6
OVH2
Do not use TS line for external charger
control
Use TS line for external charger control
(if OV event, pull TS = low)
5
OVH1
4
OVH0
3
RSVD4
8 possible settings to control
OV hysteresis (see following
table)
2
OVD
2
1
OVD1
0
OVD0
NOT USED 8 possible settings to
control OV sense delay
NOT USED (see following table)
OV Hysteresis Settings
Eight possible hysteresis settings are selectable using the bits OVH[2:0] as shown in the following table.
OVH[2:0]
OV Hysteresis (mV)
000
300
001
250
010
200
011
150
100
100
101
50
110
25
111
0
OV Delay Settings
Eight possible OV trip time delay settings are selectable using the bits OVD[2:0]
OVH[2:0]
OV Delay (Seconds)
000
0.50
001
0.75
010
1.00
011
1.25
100
1.50
101
1.75
110
2.00
111
2.25
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UV Detection Configuration #1 (UV_CFG1, Address 0x04)
Bit Number
7
6
5
4
3
2
1
0
Bit Name
UV_HYST_INH
RSVD6
RSVD7
RSVD8
UVT3
UVT2
UVT1
UVT0
If 0
Use hysteresis threshold to allow recovery after UV
condition (DEFAULT)
NOT USED
NOT USED
NOT USED
If 1
Do not use (inhibit) hysteresis threshold to allow recovery
from UV threshold
NOT USED
NOT USED
NOT USED
Set one of 16 possible values; see
following table.
Undervoltage Trip Threshold Settings
The specific undervoltage trip point required by the cell type and application can be set using the UVT[3:0] bits
as shown here:
UVT[3:0]
UV Trip Level
(Volts)
UVT[3:0]
UV Trip Level
(Volts)
0000
1.4
1000
2.2
0001
1.5
1001
2.3
0010
1.6
1010
2.4
0011
1.7
1011
2.5
0100
1.8
1100
2.6
0101
1.9
1101
2.7
0110
2.0
1110
2.8
0111
2.1
1111
2.9
UV Detection Configuration #2 (UV_CFG2, Address 0x05)
Bit
Number
7
6
5
4
3
2
1
0
UV_REC_DLY
UVH1
UVH0
RSVD10
UVD2
UVD1
UVD0
Bit Name
UV_REC
If 0
Recover from UV fault when all cell voltages increase above
VUV threshold+hyst. CHG FET enabled immediately if
charger detected
Part does NOT enter SHUTDOWN mode from
the UV fault state
Recover from UV fault only when all cell voltages increase
above VUV threshold+hyst AND load is removed.
Part does enter SHUTDOWN mode if any cell
voltage remains <VUV+hyst for >8 seconds in
the UV fault state
If 1
1 of 4 possible
values, see
table below
NOT
USED
NOT
USED
1 of 8 possible values,
binary spacing, see
following table.
UV Hysteresis Level
The UV hysteresis is set using UVH[1:0] bits. Four possible values are available as shown; however, the
maximum recovery level is set to 3.5 V in the case of a combination of high UV trip point plus high UV hysteresis
values.
UVH[1:0]
Hysteresis (Volts)
00
0.4
01
0.8
10
1.2
11
1.6
Recovery Voltage (Combination of UVT + UVH settings)
UV Trip Level
42
Hysteresis
0.4 V
0.8 V
1.2 V
1.6 V
1.4
1.8
2.2
2.6
3.0
1.5
1.9
2.3
2.7
3.1
1.6
2.0
2.4
2.8
3.2
1.7
2.1
2.5
2.9
3.3
1.8
2.2
2.6
3.0
3.4
1.9
2.3
2.7
3.1
3.5
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Recovery Voltage (Combination of UVT + UVH settings) (continued)
UV Trip Level
Hysteresis
0.4 V
0.8 V
1.2 V
1.6 V
2.0
2.4
2.8
3.2
3.5
2.1
2.5
2.9
3.3
3.5
2.2
2.6
3.0
3.4
3.5
2.3
2.7
3.1
3.5
3.5
2.4
2.8
3.2
3.5
3.5
2.5
2.9
3.3
3.5
3.5
2.6
3.0
3.4
3.5
3.5
2.7
3.1
3.5
3.5
3.5
2.8
3.2
3.5
3.5
3.5
2.9
3.3
3.5
3.5
3.5
UV Delay Time
Eight possible time delay settings for the UV trip delay are selectable using the UVD[2:0] bits as shown.
UVH[2:0]
Delay (Seconds)
000
0.5
001
1
010
2
011
4
100
8
101
16
110
32
111
OFF
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Overcurrent in Discharge Delay Settings (OCD_DELAY, Address 0x06)
Bit Number
Bit Name
If 0
If 1
7
RSVD11
NOT USED
NOT USED
6
RSVD12
NOT USED
NOT USED
5
RSVD13
NOT USED
NOT USED
4
OCDD4
3
OCDD3
2
OCDD2
1
OCDD1
0
OCDD0
One of 32 possible delay settings, see following table.
Discharge Overcurrent Detection Delay Settings
44
OCDD[4:0]
(HEX)
OC Detection Delay
(mS)
OCDD[4:0 ]
(HEX)
OC Detection Delay
(mS)
0x00
20
0x10
500
0x01
40
0x11
600
0x02
60
0x12
700
0x03
80
0x13
800
0x04
100
0x14
900
0x05
120
0x15
1000
0x06
140
0x16
1100
0x07
160
0x17
1200
0x08
180
0x18
1300
0x09
200
0x19
1400
0x0A
220
0x1A
1500
0x0B
240
0x1B
1600
0x0C
260
0x1C
1700
0x0D
280
0x1D
1800
0x0E
300
0x1E
1900
0x0F
400
0x1F
2000
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Short Circuit in Discharge Delay Settings (SCD_DELAY, Address 0x07)
Bit Number
7
6
5
4
3
2
1
0
Bit Name
RSVD14
RSVD15
ISNS_RNG
SCDD_RNG
SCDD3
SCDD2
SCDD1
SCDD0
If 0
NOT USED
NOT USED
If 1
NOT USED
NOT USED
Use lower range of values for all
short-circuit and overcurrent-trip
thresholds
Use fast delay settings
Use higher range of values for all
short-circuit and overcurrent-trip
thresholds
Use slow delay settings
One of 16 possible delay settings in each
range, see following table.
SCD Delay Settings
Two separate ranges of 16 possible delay time values are selectable as shown here.
Fast Range (SCDD_RNG = 0)
SCDD[3:0]
Slow Range (SCDD_RNG = 1)
SC Detection Delay (µs)
SCDD[3:0]
SC Detection Delay
(ms)
0x00
60
0x00
50
0x01
120
0x01
100
0x02
180
0x02
200
0x03
240
0x03
300
0x04
300
0x04
400
0x05
360
0x05
500
0x06
420
0x06
600
0x07
480
0x07
700
0x08
540
0x08
800
0x09
600
0x09
900
0x0A
660
0x0A
1000
0x0B
720
0x0B
1100
0x0C
780
0x0C
1200
0x0D
840
0x0D
1300
0x0E
900
0x0E
1400
0x0F
960
0x0F
1500
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Discharge Overcurrent/Short-Circuit Trip Levels (OCD_SCD_TRIP, Address 0x08)
Bit Number
Bit Name
If 0
If 1
7
6
5
4
SCDT3
SCDT2
SCDT1
SCDT0
One of 16 possible SC trip settings (sense resistor voltage),
see following table.
3
OCDT3
2
OCDT2
1
OCDT1
0
OCDT0
One of 16 possible OC trip settings (sense resistor voltage),
see following table.
NOTE: SCD and OCD trip levels are controlled by current-sense gain-control bit ISNS_RNG located in
register 0x07. Trip levels measured at SENSE– are referenced to SENSE+.
Discharge Short-Circuit Trip-Level Settings (Sense-Resistor Voltage)
SCDT[3:0]
Discharge Short-Circuit Trip Level,
mV at SENSE (–),
With ISNS_RNG = 0
Discharge Short-Circuit Trip Level,
mV at SENSE(–),
With ISNS_RNG = 1
0000
40
200
0001
50
250
0010
60
300
0011
70
350
0100
80
400
0101
90
450
0110
100
500
0111
110
550
1000
120
600
1001
130
650
1010
140
700
1011
150
750
1100
160
800
1101
170
850
1110
180
900
1111
190
950
Discharge Overcurrent Trip-Level Settings (Sense-Resistor Voltage)
46
OCDT[3:0]
Discharge Overcurrent Trip Level,
mV at SENSE(–),
With ISNS_RNG = 0
Discharge Overcurrent Trip Level,
mV at SENSE(–),
With ISNS_RNG = 1
0000
25
125
0001
30
150
0010
35
175
0011
40
200
0100
45
225
0101
50
250
0110
55
275
0111
60
300
1000
65
325
1001
70
350
1010
75
375
1011
80
400
1100
85
425
1101
90
450
1110
95
475
1111
100
500
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Charge Short-Circuit Threshold and Delay Settings (SCC_CFG, Address 0x09)
Bit Number
Bit Name
If 0
If 1
7
6
5
4
SCCD3
SCCD2
SCCD1
SCCD0
One of 16 possible charger short-circuit sensing delay
settings, see following table.
3
SCCT3
2
SCCT2
1
SCCT1
0
SCCT0
One of 16 possible charger short-circuit sensing threshold
settings (sense resistor voltage), see following table.
NOTE: SCC trip-level range is controlled by current-sense gain-control bit ISNS_RNG, located in register
0x07. Trip levels measured at SENSE– are referenced to SENSE+.
Charge Short-Circuit Delay-Time Settings
SCCD[3:0]
Charge Short-Circuit
Delay (µs)
SCCD[3:0]
Charge Short-Circuit
Delay (µs)
0000
60
1000
540
0001
120
1001
600
0010
180
1010
660
0011
240
1011
720
0100
300
1100
780
0101
360
1101
840
0110
420
1110
900
0111
480
1111
960
Charge Short-Circuit Trip-Level Settings
SCCT[3:0]
Charge Short-Circuit Trip Level,
mV at SENSE(–),
With ISNS_RNG = 0
Charge Short-Circuit Trip Level,
mV at SENSE(–),
With ISNS_RNG = 1
0000
–10
0–50
0001
–15
0–75
0010
–20
–100
0011
–25
–125
0100
–30
–150
0101
–35
–175
0110
–40
–200
0111
–45
–225
1000
–50
–250
1001
–55
–275
1010
–60
–300
1011
–65
–325
1100
–70
–350
1101
–75
–375
1110
–80
–400
1111
–85
–425
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Cell-Balancing Configuration (CELL_BAL_CFG, Address 0x0A)
Bit Number
Bit Name
If 0
If 1
7
6
CB_EN1
CB_EN0
See 4 possible values
following
5
CBT1
4
CBT0
See 4 possible values
following
3
CBV3
2
CBV2
1
CBV1
0
CBV0
One of 16 possible settings for cell-balance threshold
(highest cell voltage to initiate balance action)
Cell-Balance Enable Control
CB_EN[1:0]
(1)
Cell Balance Function
00
Disable cell-balance function
01
Enable cell-balance function (1) at all times – start balancing (timer counting) whenever CBV threshold is reached, terminate
when timer expires. Balancing restarts once all cells have first fallen below the CBV threshold and then at least one cell again
reaches the CBV threshold.
10
Enable cell balance function (1) when charger detected, terminate when charger removed.
(Note: This is recommended only with chargers that keep the battery topped-off, i.e., maintenance charge implemented after
regular charge completion.)
11
Enable cell-balance function (1) when charger is detected, terminate when charger is removed OR when timer expires.
Following timer expiration, the charger must be disconnected then reconnected to restart balancing.
Enable cell balance function means that the logic checks cell voltages to decide if balancing action (current bleed/bypass) should occur.
Start balancing is defined as the time when the algorithm is active, i.e. actually diverting current around a cell. Timer initiation begins
when balancing action starts, not when charger is detected.
Cell-Balance Timer
Cell balancing, if enabled, begins when the charger is present and the first cell exceeds the CBV start threshold.
Cell balancing is terminated when the charger is removed, or after CBT timeout interval regardless of
charger-removal detection. This method is used to prevent continuous drain of the cells in the case where the
battery pack is stored in the charger after charge termination.
CBT[1:0]
Timeout Length (Hours)
00
1
01
2
10
4
11
8
Cell Balance Voltage Threshold Settings
When any cell reaches the programmed setting, the cell balance algorithm begins as discussed previously in the
operation / applications section. Cell balancing must be enabled via the CB_EN control bit, and in some cases
(see the Cell-Balance Enable Control section) the charger must be detected for the algorithm to initiate.
48
CBV[3:0]
Cell Voltage
0000
3.9
0001
3.8
0010
3.7
0011
3.6
0100
3.5
0101
3.4
0110
3.3
0111
3.2
1000
3.1
1001
3.0
1010
2.9
1011
2.8
1100
2.7
1101
2.6
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CBV[3:0]
Cell Voltage
1110
2.5
1111
2.4
EEPROM Control Register (EEPROM, Address 0x0B)
Bit Number
Bit Name
7
EEPROM7
6
EEPROM6
5
EEPROM5
4
EEPROM4
3
EEPROM3
2
EEPROM2
1
EEPROM1
0
EEPROM0
These bits enable data write to EEPROM locations (0x01–0x0A) when written with data 0100 0001 (0x41).
Pre-read of EEPROM data is available by setting these bits with 0110-0010 (0x62). Default is 0000-0000 (0x00).
EEPROM Write Sequence
EEPROM is written by I2C command. When ZEDE = H, the SCLK and SDATA lines are enabled to allow I2C
communication.
I2C Address +R/W bit
(MSB)
(MSB)
Write
Read
0
(LSB)
2
I C Address
0
1
0
(LSB)
0
0
0
0
1
The bq77910 has integrated configuration EEPROM for OV, UV, OCD, SCD, and SCC thresholds and delays.
The appropriate configuration data is programmed to the configuration registers and then 0x41 is sent to the
EEPROM register to enable programming
. By driving the EEPROM pin (set high and then low), the
data is written to the EEPROM. The recommended voltage at BAT for EEPROM writing is >7 V. A flowchart
showing the EEPROM write / check sequence is shown in Figure 16.
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Parity Check
The bq77910 uses EEPROM for storage of protection thresholds and delay times as previously described.
Additional EEPROM is also used to store internal trimming data. For safety reasons, the bq77910 uses a
column-parity error-checking scheme. If the column-parity bit is changed from the written data, both DSG and
CHG FETs are forced OFF as a fail-safe mechanism.
START
Wait 1 ms
Set BAT > 7
Set ZEDE and
CHGST High
(3.3 V ± 5%)
Set EEPROM pin
= 14 V ±0.5 V
Wait 16 ms
2
Send I C
commands to set
all device
configuration
registers
(0x01–0x0A) to
desired values
Write 0x62 to
EEPROM control
register (address
0x0B)
Read back and
verify all device
configuration
registers
Set EEPROM pin
= 0 V (VSS)
Wait 1 ms
Write 0x00 to
EEPROM control
register (address
0x0B)
Read back and
verify all device
configuration
registers
Write 0x41 to
EEPROM control
register (address
0x0B)
Set ZEDE and
CHGST Low
(0 V = VSS)
END
Figure 16. EEPROM Programming Flow Diagram
50
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REVISION HISTORY
Changes from Revision A (October 2010) to Revision B
Page
•
Deleted a Features bullet under Low Supply Current ........................................................................................................... 1
•
Changed high end of cell-to-cell differential to 9 V ............................................................................................................... 5
•
Added cell input rows to Absolute Maximum Ratings table .................................................................................................. 5
•
Added lower bound to maximum ratings for output voltage on pins CHG and DSG ........................................................... 5
•
Added row for regulator current ............................................................................................................................................ 5
•
Added note following Absolute Maximum Ratings table ....................................................................................................... 5
•
Deleted row "VC10 to VC1" from Recommended Operating Condidions input voltage range ............................................ 6
•
Changed ............................................................................................................................................................................... 6
•
Added cell input rows to Recommended Operating Conditions table .................................................................................. 6
•
Added VSENSE(+) and (–) rows to Recommended Operating Conditions table ................................................................. 6
•
Added "nominal" to parameter descriptions for RVCX and CVCX in Recommended Operating Conditions table ................... 6
•
Added IREG and ICB rows to Recommended Operating Conditions table .............................................................................. 6
•
Changed CREG to CVREG in Recommended Operating Conditions table ......................................................................... 6
•
Added 0.1 minimum value for CCCAP, CDCAP in Recommended Operating Conditions table ......................................... 6
•
Changed CCCAP and CDCAP note following Recommended Operating Conditions table ....................................................... 6
•
Changed ICC from supply current to average supply current and added "(no load)" to test conditions ................................ 7
•
Changed electrical characteristic values for ISHUTDOWN_1; changed ISHUTDOWN_2 row ............................................................. 7
•
Changed values for VGATE_UV and VGATE_UV_H in Electrical Charactreristics .......................................................................... 7
•
Added "no dc load" to test condition for V(FETON) in Electrical Characteristics ...................................................................... 7
•
Changed values in Electrical Characteristics for tf with test condition BAT = 6.4 ................................................................ 7
•
Changed values for ISC in Electrical Characteristics ............................................................................................................. 7
•
Changed values for VHOT in Electrical Characteristics .......................................................................................................... 8
•
Changed values for VTH_HYST in Electrical Characteristics .................................................................................................... 8
•
Deleted Current-Sense Amplifier Inputs row from Electrical Characteristics ........................................................................ 8
•
Changed description of ROPEN_CELL in Electrical Characteristics from "Impedance..." to "Minimum impedance..." and
changed value ....................................................................................................................................................................... 8
•
Changed maximum ΔVOV threshold accuracies from 40 mV to 50 mV and from 65 mV to 75 mV ..................................... 8
•
Changed text of "This current is sufficient..." note following Electrical Characteristics ........................................................ 8
•
Changed values for VCHG_DET1 .............................................................................................................................................. 9
•
Deleted Internal Oscillator section ...................................................................................................................................... 10
•
Changed first paragraph of Normal Operation Mode section ............................................................................................. 10
•
Made several changes inTable 1i ....................................................................................................................................... 11
•
Added names of EEPROM bits to Cell Overvoltage and Undervoltage Detectioin and Revovery sections ...................... 11
•
Corrected text in Caution statement and in second following paragraph ........................................................................... 12
•
Changed resistance in Load Removal Detection/OCD and SCD Fault Recovery section ................................................. 12
•
Deleted text from body of Note ........................................................................................................................................... 12
•
Added names of EEPROM bits to Short Circuit in Charge (SCC) Detection section ......................................................... 13
•
Deleted text from first paragraph ofBAT Voltage Peak Detection/Transient Suppression section ..................................... 15
•
Changed battery pack voltage from 40 V to 43.75 V .......................................................................................................... 15
•
Corrected second paragraph in FET Gate Drive Control section ....................................................................................... 17
•
Changed several entries in the Filter Time column of the Fault Detection, Action, and Recovery Condition Summary
table .................................................................................................................................................................................... 21
•
Added a NOTE following the Fault Detection, Action, and Recovery Condition Summary table ....................................... 21
•
Reworded text in Normal Configuration – Balancing With Internal FETs section .............................................................. 23
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•
Changed REG to VREG ..................................................................................................................................................... 25
•
Added a CPCKN Pin Detection section to the data sheet .................................................................................................. 25
•
Changed REG to VREG, 100 Ω to 150 Ω, and deleted a sentence in the TS and VTSB Pin Interface section ................ 26
•
Changed text of existing paragraphs and added a new paragraphj to the Series CHG and DSG FET Configuration ...... 32
•
Minor text changes to Separate CHG(–) and DSG(–) Return Paths With Both FETs section ........................................... 33
•
Changed "PACK(+) positive terminal" to "most-positive cell input" in the 4 to 10 Series Cell Configuration section ........ 36
•
Deleted a phrase from the last paragraph of the Ship-Mode Equivalent Functionality section .......................................... 37
•
Deleted text from second bullet in list of Device Addressing and Protocol Overview section ............................................ 37
•
Deleted text from note following Memory Map table .......................................................................................................... 39
•
Corrected Charge Short-Circuit Delay for SCCD[3:0] = 0010 ............................................................................................ 47
•
Deleted text in the paragraph following the table in the EEPROM Write Sequence section ............................................. 49
52
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PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
BQ77910DBT
ACTIVE
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ77910DBTR
ACTIVE
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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