10-Bit, 6-Channel Decimating LCD DecDriver® with Level Shifters AD8384 PRODUCT FEATURES High accuracy, high resolution voltage outputs 10-bit input resolution Laser trimmed outputs Fast settling, high voltage drive 30 ns settling time to 0.25% into a 150 pF load Slew rate 460 V/µs Outputs to within 1.3 V of supply rails High update rates Fast, 100 Ms/s 10-bit input data update rate Voltage controlled video reference (brightness), offset, and full-scale (contrast) output levels Flexible logic STSQ/XFR allow parallel AD8384 operation INV bit reverses polarity of video signal Output short-circuit protection 3.3 V logic, 9 V to 18 V analog supplies 18 V level shifters for panel timing signals Available in 80-lead 12 mm × 12 mm TQFP E-pad APPLICATIONS LCD analog column drivers FUNCTIONAL BLOCK DIAGRAM BYP VRH VRL DB(0:9) R/L CLK STSQ XFR BIAS 2 / SCALING CONTROL 10 2-STAGE LATCH / 4 6 / DACs VID0 VID1 VID2 VID3 VID4 VID5 SEQUENCE CONTROL / INV CONTROL INV V1 V2 TSTM SDI SCL SEN SVRH SVRL DYIN DXIN DIRYIN DIRXIN NRGIN ENBX1IN ENBX2IN ENBX3IN ENBX4IN CLXIN CLYIN 3 2 / 12-BIT SHIFT REGISTER VAO1 DUAL DAC VAO2 / 9 / 2 / 9 / DY DX DIRY DIRX NRG ENBX1 ENBX2 ENBX3 ENBX4 2 CLX CLY 2 CLXN CLYN / / R MONITI AD8384 04512-0-001 MONITO S Figure 1. PRODUCT DESCRIPTION The AD8384 DecDriver provides a fast, 10-bit, latched, decimating digital input that drives six high voltage outputs. 10-bit input words are loaded sequentially into six separate high speed, bipolar DACs. Flexible digital input format allows several AD8384s to be used in parallel in high resolution displays. The output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility. Integrated level shifters convert timing signals from a 3 V timing controller to high voltage for LCD panel timing inputs. Two serial input, 8-bit DACs are integrated to provide dc reference signals. DAC addresses and 8-bit data are loaded in one 12-bit serial word. The AD8384 is fabricated on the 26 V, fast, bipolar XFHV process developed by Analog Devices, Inc. This process provides fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. The AD8384 dissipates 1.1 W nominal static power. The AD8384 is offered in an 80-lead 12 mm × 12 mm TQFP E-pad package and operates over the 0°C to 85°C commercial temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8384 TABLE OF CONTENTS Specifications..................................................................................... 3 Functional Description.................................................................. 15 DecDriver ...................................................................................... 3 Accuracy ...................................................................................... 16 Level Shifters ................................................................................. 5 TSTM Control—Test Mode ...................................................... 16 Level Shifting Edge Detector ...................................................... 5 Grounded Output Mode ........................................................... 16 Serial Interface .............................................................................. 6 Overload Protection................................................................... 16 Power Supplies .............................................................................. 7 3-Wire Serial Interface............................................................... 16 Operating Temperature ............................................................... 7 Serial DACs ................................................................................. 16 Absolute Maximum Ratings............................................................ 8 Level Shifters ............................................................................... 16 Maximum Power Dissipation ..................................................... 8 Applications..................................................................................... 17 Operating Temperature Range ................................................... 8 Power Supply Sequencing ......................................................... 17 Overload Protection..................................................................... 8 VBIAS Generation—V1, V2 Input Pin Functionality ........... 18 Exposed Paddle............................................................................. 8 Applications Circuit ................................................................... 18 Pin Configuration and Function Descriptions............................. 9 PCB Design for Optimized Thermal Performance ............... 19 Timing Characteristics................................................................... 11 Thermal Pad Design .................................................................. 19 DecDriver Section ...................................................................... 11 Thermal Via Structure Design.................................................. 19 Level Shifter Section................................................................... 12 AD8384 PCB Design Recommendations ............................... 20 Level Shifting Edge Detector .................................................... 13 Outline Dimensions ....................................................................... 21 Serial Interface ............................................................................ 14 Ordering Guide .......................................................................... 21 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8384 SPECIFICATIONS DecDriver Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted Parameter VIDEO DC PERFORMANCE1 VDE VCME VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% Invert Switching Overshoot CLK and Data Feedthrough2 All-Hostile Crosstalk3 Amplitude Glitch Duration DAC Transition Glitch Energy VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage—Grounded Mode Data Switching Delay: t94 INV Switching Delay: t105 Output Current Output Resistance REFERENCE INPUTS V1 Range V2 Range V1 Input Current V2 Input Current VRL Range VRH Range (VRH–VRL) Range VRH Input Resistance VRL Bias Current VRH Input Current RESOLUTION Coding Conditions TA MIN to TA MAX DAC Code 450 to 800 DAC Code 450 to 800 TA MIN to TA MAX , VO = 5 V Step, CL = 150 pF 20% to 80% 20% to 80% Min Typ –7.5 –3.5 460 560 19 30 75 250 100 10 VO = 10 V Step VO = 10 V Step VO = 10 V Step Max Unit +7.5 +3.5 mV mV 24 50 120 500 200 10 30 0.3 DAC Code 511 to 512 AVCC – VOH, VOL – AGND 50 % of VIDx 50 % of VIDx 10 13 V2 ≥ (V1-0.25V) V2 ≥ (V1-0.25V) 5.25 5.25 1.1 0.25 12 15 100 22 mV p-p ns nV-s 1.3 14 17 AVCC – 4 AVCC – 4 –3 –14 VRH ≥ VRL VRH ≥ VRL VFS = 2(VRH – VRL) To VRL V1 – 0.5 VRL 0 Binary 10 1 AVCC – 1.3 AVCC 2.75 20 –0.2 125 VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 × (VRH – VRL). See the Accuracy section. Measured differentially on two outputs as CLK and DB(0:9) are driven and STSQ and XFR are held LOW. Measured differentially on two outputs as the other four are transitioning by 5 V. Measured for both states of INV. 4 Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV. 5 Measured from 50% of rising CLK edge to 50% of output change. Refer to Figure 7 for the definition. 2 3 Rev. 0 | Page 3 of 24 V/µs V/µs ns ns ns ns mV mV p-p V V ns ns mA Ω V V µA µA V V V kΩ µA µA Bits AD8384 DecDriver (continued) Parameter DIGITAL INPUT CHARACTERISTICS Max. Input Data Update Rate CLK to Data Setup Time: t1 CLK to STSQ Setup Time: t3 CLK to XFR Setup Time: t5 CLK to Data Hold Time: t2 CLK to STSQ Hold Time: t4 CLK to XFR Hold Time: t6 CLK High Time: t7 CLK Low Time: t8 CIN IIH IIL VIH VIL VTH Conditions Min Typ Max 100 0 0 0 3 3 3 3 2.5 3 0.05 –0.6 2 0.8 1.65 Rev. 0 | Page 4 of 24 Unit Ms/s ns ns ns ns ns ns ns ns pF µA µA V V V AD8384 LEVEL SHIFTERS Table 2. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted Parameter LEVEL SHIFTER LOGIC INPUTS CIN IIH IIL VTH VIH VIL LEVEL SHIFTER OUTPUTS VOH VOL LEVEL SHIFTER DYNAMIC PERFORMANCE Output Rise, Fall Times—tr, tf DX, CLX, CLXN, ENBX(1–4) DY, CLY, CLYN DIRX, DIRY NRG Propagation Delay Times—t11, t12, t13, t14 DX, CLX, CLXN, ENBX(1–4) DY, CLY, CLYN DIRX, DIRY NRG Output Skew ENBX(1–4)—t15, t16 DX to ENBX(1–4)—t16 DX to CLX—t15, t16, t17, t18 DY to CLY, CLYN—t15, t16, t17, t18 Conditions Min Typ Max Unit 3 DVCC 0.8 pF µA µA V V V AVCC – 0.25 0.25 0.45 V V CL = 40 pF CL = 40 pF CL = 40 pF CL = 200 pF CL = 300 pF 18.5 40 100 35 55 30 70 150 50 100 ns ns ns ns ns CL = 40 pF CL = 40 pF CL = 40 pF CL = 200 pF CL = 300 pF 20 29 60 25 32 50 50 100 55 ns ns ns ns ns 2 2 10 20 ns ns ns ns Max AGND + 2.75 AVCC Unit V V V V V V µA µA ns ns ns ns ns ns 0.05 –0.6 1.65 2.0 DGND RL ≥ 10 kΩ AVCC – 0.45 TA MIN to TA MAX CL = 40 pF CL = 40 pF CL = 40 pF CL = 40 pF LEVEL SHIFTING EDGE DETECTOR Table 3. CL = 10 pF, TA MIN to TA MAX, unless otherwise noted Parameter VIL VIH VTH LH VTH HL VOH VOL IIH IIL t19 ∆t19 t20 ∆t20 tr tf Min AGND AVCC – 2.7 Input Low Voltage Input High Voltage Input Rising Edge Threshold Voltage Input Falling Edge Threshold Voltage Output High Voltage Output Low Voltage Input Current High State Input Current Low State Input Rising Edge Propagation Delay Time t19 Variation with Temperature Input Falling Edge Propagation Delay Time t20 Variation with Temperature Output Rise Time Output Fall Time DVCC – 0.45 –2.5 Rev. 0 | Page 5 of 24 Typ AGND + 3 AVCC – 3 DVCC – 0.25 0.25 1.2 –1.2 16 2 12 2 5 6 0.45 2.5 AD8384 SERIAL INTERFACE Table 4. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVRL = 4 V, SVRH = 9 V, unless otherwise noted Parameter SERIAL DAC REFERENCE INPUTS SVRH Range SVRL Range SVFS Range SVRH Input Current SVRL Input Current SVRH Input Resistance SERIAL DAC ACCURACY DNL INL Output Offset Error Scale Factor Error SERIAL DAC LOGIC INPUTS CIN IIL IIH VTH VIH VIL SERIAL DAC OUTPUTS Maximum Output Voltage Minimum Output Voltage VAO1—Grounded Mode IOUT CLOAD Low Range6 CLOAD High Range1 SERIAL DAC DYNAMIC PERFORMANCE SEN to SCL Setup Time, t20 SCL, High Level Pulse Width, t21 SCL, Low Level Pulse Width, t22 SDI Setup Time, t24 SDI Hold Time, t25 SCL to SEN Hold Time, t23 VAO1, VAO2 Settling Time, t26 VAO1, VAO2 Settling Time, t26 6 Conditions SVFS = (SVRH – SVRL) SVRL < SVRH SVRL < SVRH SVFS = 5 V SVFS = 5 V Min SVRL + 1 AGND + 1.5 1 –2.8 SVFS = 5 V, RL = ∞ SVFS=5 V, RL = ∞ Typ Max Unit AVCC – 3.5 SVRH – 1 8 V V V nA mA kΩ +1.0 +1.5 +2.0 +4.0 LSB LSB LSB LSB 3 pF µA µA V V V –70 –2.5 40 –1.0 –1.5 –2.0 –4.0 –0.6 0.05 1.65 2.0 DGND DVCC 0.8 SVRH – 1 LSB SVRL 0.1 ±30 0.002 0.047 10 15 10 10 10 15 SVFS = 5 V, to 0.5%, CL = 100 pF SVFS = 5 V, to 0.5%, CL = 33 µF 1 10 Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. The load capacitance must be ≤ 0.002 µF or ≥0.047 µF. Load capacitance in the range 0.002 µF to 0.047 µF causes the output overshoot to exceed 100 mV. Rev. 0 | Page 6 of 24 2 15 V V V mA µF µF ns ns ns ns ns ns µs ms AD8384 POWER SUPPLIES Table 5. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVRL = 4 V, SVRH = 9 V, unless otherwise noted Parameter DVCC, Operating Range DVCC, Quiescent Current AVCC Operating Range Total AVCC Quiescent Current Min 3 Typ 3.3 40 9 70 Max 3.6 50 18 85 Unit V mA V mA Max 75 85 125 Unit °C °C °C OPERATING TEMPERATURE Parameter Ambient Temperature Range, TA7 Ambient Temperature Range, TA8 Junction Temperature Range, TJ Conditions Still Air 200 lfm 100% Tested 7 Min 0 0 25 Typ Operation at high ambient temperature requires a thermally optimized PCB layout (see the Applications section), input data update rate not exceeding 85 MHz, blackto-white transition ≤ 4V and CL ≤ 150 pF. In systems with limited or no airflow, the maximum ambient operating temperature is limited to 75°C. For operation above 75°C, see Note 8 below. 8 In addition to the requirements stated in Note 7 above, operation at 85°C ambient temperature requires 200 lfm airflow. Rev. 0 | Page 7 of 24 AD8384 ABSOLUTE MAXIMUM RATINGS Table 6. AD8384 Stress Ratings9 Parameter Supply Voltages AVCCx – AGNDx DVCC – DGND Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltages Internal Power Dissipation10 TQFP E-Pad Package @ TA = 25°C Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec) MAXIMUM POWER DISSIPATION Rating The maximum power that can be safely dissipated by the AD8384 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is approximately 150°C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. 18 V 4.5 V DVCC + 0.5 V DGND – 0.5 V AVCC + 0.5 V AGND – 0.5 V 4.16 W 0°C to 85°C –65°C to +125°C 300°C OPERATING TEMPERATURE RANGE Although the maximum safe operating junction temperature is higher, the AD8384 is 100% tested at a junction temperature of 125°C. Consequently, the maximum guaranteed operating junction temperature is 125°C. 9 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability. 10 80-lead TQFP E-pad package: θJA = 24°C/W (JEDEC STD, 4-layer PCB in still air) θJC = 16°C/W To ensure operation within the specified temperature range, it is necessary to limit the maximum power dissipation as follows: PDMAX≈ (TJMAX – TA) θJA– 0.5 × Airflow(lfm) 2.5 OVERLOAD PROTECTION EXPOSED PADDLE To ensure optimized thermal performance, the exposed paddle must be thermally connected to an external plane, such as AVCC or GND, as described in the Application Notes. 500lfm 100MHz 2.0 60Hz XGA 1.5 STILL AIR QUIESCENT 1.0 65 70 75 80 85 90 95 100 105 AMBIENT TEMPERATURE (°C) 04512-0-002 The thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short-circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typical with a period determined by the thermal time constant and the hysteresis of the thermal trip point. Thermal shutdown provides long term protection by limiting average junction temperature to a safe level. MAXIMUM POWER DISSIPATION (W) 200lfm The AD8384 employs a 2-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any one output of the AD8384 is, on average, internally limited to 100 mA. In the event of a momentary short circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection. Figure 2. Maximum Power Dissipation vs. Temperature* *AD8384 on a 4-layer JEDEC PCB with thermally optimized landing pattern, as described in the Application Notes. Note: When operating under the conditions specified in this data sheet, the AD8384’s quiescent power dissipation is 1.1 W. When driving a 6-channel XGA panel with a 150 pF input capacitance, the AD8384 dissipates a total of 1.58 W when displaying 1-pixel-wide alternating white and black vertical lines generated by a standard 60 Hz XGA input video. When the pixel clock frequency is raised to 100 MHz (the AD8384’s maximum specified operating frequency), total power dissipation increases to 1.83 W. Figure 2 shows these specific power dissipations. Rev. 0 | Page 8 of 24 AD8384 BYP V1 VRH VRL V2 AVCCDAC NC AGNDDAC NC DB1 DB0 DB2 DB3 DB4 DB5 DB6 DB8 DB7 DB9 DVCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DGND 1 60 AGND0 59 VID0 CLK 3 58 AVCC0,1 XFR 4 57 VID1 STSQ 5 56 AGND1,2 INV 6 55 VID2 R/L 7 54 AVCC2,3 E/O 8 53 VID3 AD8384 52 AGND3,4 TOP VIEW (Not to Scale) 51 VID4 50 AVCC4,5 NC 12 49 VID5 AGNDS 13 48 AGND5 SVRL 14 47 CLXN SVRH 15 46 CLX VAO1 16 45 ENBX4 VAO2 17 44 ENBX3 AVCCS 18 43 ENBX2 DIRXIN 19 42 ENBX1 DIRYIN 20 41 DX PIN 1 IDENTIFIER TSTM 2 SDI 9 SEN 10 SCL 11 CLXIN ENBX4IN ENBX3IN ENBX2IN DXIN ENBX1IN NC MONITO MONITI NRG AGNDL NRGIN AVCCL CLYN DY CLY DIRY DIRX DYIN NC = NO CONNECT CLYIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 3. 80-Lead 12 mm × 12 mm TQFP E-Pad Pin Configuration Table 7. Pin Function Descriptions Pin Name Function Description DB(0:9) Data Input 10-Bit Data Input. MSB = DB(9). CLK Clock Clock Input. STSQ Start Sequence The state of STSQ is detected on the active edge of CLK. A new data loading sequence begins on the next active edge of CLK after STSQ is detected HIGH. The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when E/O is held LOW. R/L Right/Left Select A new data loading sequence begins on the left, with Channel 0, when this input is LOW, and on the right, with Channel 5, when this input is HIGH. E/O Even/Odd Select The active CLK edge is the rising edge when this input is held HIGH. It is the falling edge when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is HIGH and on the falling edges when this input is LOW. XFR Data Transfer XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held HIGH. Data is transferred to the video outputs on the next rising CLK edge after XFR is detected. VID0–VID5 Analog Outputs These pins are directly connected to the analog inputs of the LCD panel. V1, V2 Reference Voltages The voltage applied between V1 and AGND sets the white video level during INV = LOW. The voltage applied between V2 and AGND sets the white video level during INV = HIGH. VRH, VRL Full-Scale References Twice the voltage applied between these pins sets the full-scale video output voltage. BYP Bypass A 0.1µ F capacitor connected between this pin and AGND ensures optimum settling time. Rev. 0 | Page 9 of 24 AD8384 Pin Name Function Description INV Invert When this input is HIGH, the VIDx output voltages are above V2. When INV is LOW, the VIDx output voltages are below V1. The state of INV is latched on the first rising CLK edge, after XFR is detected. The VIDx outputs change on the rising CLK edge after the next XFR is detected. DVCC Digital Power Supply Digital Power Supply. DGND Digital Ground This pin is normally connected to the digital ground plane. AVCCx Analog Power Supplies Analog Power Supplies. AGNDx Analog Ground Analog Supply Returns. SVRH, SVRL Serial DAC Reference Voltages Reference Voltages for the Output Amplifiers of the Control DACs. SCL Serial Data Clock Serial Data Clock. SDI Data Input While the SEN input is LOW, one 12-bit serial word is loaded into the serial DAC on the rising edges of SCL. The first bit selects the output, the next three bits are unused, and the subsequent eight bits are the data used in the DAC. SEN Serial DAC Enable A falling edge of this input initiates a loading cycle. While this input is held LOW, the serial DAC is enabled and data is loaded on every rising edge of SCL. The selected output is updated on the rising edge of this input. While this input is held HIGH, the control DAC is disabled. VAO1, VAO2 Serial DAC Voltage Output These output voltages are updated on the rising edge of the SEN input. TSTM Test Mode When this input is LOW, the output mode is determined by the function programmed into the serial interface. While this input is held HIGH, the output mode is forced to NORMAL, regardless of function programmed into the serial interface. MONITI Monitor Input Logic Input of the Level Shifting Inverting Edge Detector. MONITO Monitor Output Output of the Level Shifting Inverting Edge Detector. DYIN, DIRYIN, DIRXIN, DXIN, NRGIN, ENBX(1–4)IN Inverting Level Shifter Inputs Logic Input of the Inverting Level Shifters. DX, DY, DIRX, DIRY, NRG, ENBX(1-4) Inverting Level Shifter Outputs While the corresponding input voltage of these level shifters is below the threshold voltage, the output voltage at these pins is at VOH. While the corresponding input voltage of these level shifters is above the threshold voltage, the output voltage at these pins is at VOL. CLXIN, CLYIN Complementary Level Shifter Inputs Logic Input of the Complementary Level Shifters. CLX, CLXN, CLY, CLYN, Complementary Level Shifter Outputs While the corresponding input voltage of these level shifters is below the threshold voltage, the voltage at the noninverting output pins is at VOH and the voltage at the inverting outputs is at VOL. While the corresponding input voltage of these level shifters is above the threshold voltage, the voltage at the noninverting output pins is at VOL and the voltage at the inverting outputs is at VOH. Rev. 0 | Page 10 of 24 AD8384 tf TIMING CHARACTERISTICS tr t8 DECDRIVER SECTION CLK t1 DAC VID0 10 2-STAGE 10 LATCH DAC VID1 10 2-STAGE 10 LATCH BYP CLK STSQ XFR R/L INV VTH DB(0:9) STSQ DAC t2 t3 t4 t5 t6 VTH VID2 VTH XFR BIAS SEQUENCE CONTROL 10 2-STAGE 10 LATCH DAC VID3 10 2-STAGE 10 LATCH DAC VID4 10 2-STAGE 10 LATCH DAC VID5 04512-0-005 AD8384 10 2-STAGE 10 LATCH Figure 5. Input Timing, Even Mode (E/O = HIGH) t8 t7 VTH CLK t1 INV CONTROL VRH VRL V1 04512-0-004 SCALING CONTROL V2 t2 VTH DB(0:9) Figure 4. Block Diagram VTH STSQ t3 t4 VTH XFR t5 04512-0-006 DB(0:9) 10 10 VTH t7 t6 Figure 6. Input Timing, Odd Mode ( E/O = LOW) CLK DB(0:9) –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 STSQ XFR INV 50% PIXELS –6, –5, –4, –3, –2, –1 50% t9 t9 V1 PIXELS 0, 1, 2, 3, 4, 5 t10 V1–VFS 04512-0-007 V2+VFS VID(0:5) V2 Figure 7. Output Timing (R/L = Low, E/O = High) Table 8. Timing Characteristics Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Conditions CLK to Data Setup Time CLK to Data Hold Time CLK to STSQ Setup Time CLK to STSQ Hold Time CLK to XFR Setup Time CLK to XFR Hold Time CLK High Time CLK Low Time CLK to VIDx Delay INV to VIDx Delay Rev. 0 | Page 11 of 24 Min 0 3 0 3 0 3 3 2.5 10 13 Typ Max 12 15 14 17 Unit ns ns ns ns ns ns ns ns ns ns AD8384 CLX CLY CLXIN CLYIN 04512-0-008 DY DX DIRY DIRX NRG ENBX1 ENBX2 ENBX3 ENBX4 DYIN DXIN DIRYIN DIRXIN NRGIN ENBX1IN ENBX2IN ENBX3IN ENBX4IN CLXN CLYN 04512-0-009 LEVEL SHIFTER SECTION Figure 9. Level Shifter—Complementary Figure 8. Level Shifter—Inverting INPUTS t11 t12 INVERTING OUTPUTS t15 NONINVERTING OUTPUTS t13 t14 04512-0-010 t16 t18 t17 Figure 10. Inverting and Complementary Level Shifter Timing Table 9. Level Shifter Timing Parameter Output Rise, Fall Times, tr, tf DX, CLX, CLXN, ENBX(1–4) DY, CLY, CLYN DIRX, DIRY NRG Propagation Delay Times—t11, t12, t13, t14 DX, CLX, CLXN, ENBX(1–4) DY, CLY, CLYN DIRX, DIRY NRG Propagation Delay Skew ENBX(1–4)—t15, t16 DX to ENBX(1–4)—t16 DX to CLX—t15, t16, t17, t18 DY to CLY, CLYN—t15, t16, t17, t18 Conditions TA MIN to TA MAX CL = 40 pF CL = 200 pF CL = 300 pF TA MIN to TA MAX CL = 40 pF CL = 200 pF CL = 300 pF TA MIN to TA MAX, CL = 40 pF Rev. 0 | Page 12 of 24 Min Typ Max Unit 18.5 40 100 35 55 30 70 150 50 100 ns ns ns ns ns 20 29 60 25 32 50 50 100 55 ns ns ns ns ns 2 2 10 20 ns ns ns ns AD8384 LEVEL SHIFTING EDGE DETECTOR MONITO S 04512-0-011 R MONITI Figure 11. Level Shifting Edge Detector Block Diagram AVCC MONITI AGND t19 t20 VOH 04512-0-012 MONITO VOL Figure 12. Level Shifting Edge Detector Timing Table 10. Level Shifting Edge Detector, AVCC = 15.5 V, DVCC = 3.3 V, CL = 10 pF, TA MIN = 25°C, TA MAX = 85°C Parameter VIL VIH VTH LH VTH HL IIH IIL VOH VOL t19 ∆t19 t20 ∆t20 tr tf Input Low Voltage Input High Voltage Input Rising Edge Threshold Voltage Input Falling Edge Threshold Voltage Input Current High State Input Current Low State Output High Voltage Output Low Voltage Input Rising Edge Propagation Delay Time t19 Variation with Temperature Input Falling Edge Propagation Delay Time t20 Variation with Temperature Output Rise Time Output Fall Time Min AGND AVCC – 2.7 –2.5 DVCC – 0.45 Rev. 0 | Page 13 of 24 Typ AGND + 3 AVCC – 3 1.2 –1.2 DVCC – 0.25 0.25 16 2 12 2 5 6 Max AGND + 2.75 AVCC 2.5 0.45 Unit V V V V µA µA V V ns ns ns ns ns ns AD8384 SERIAL INTERFACE SVRH SVRL SDI 12-BIT SHIFT REGISTER SCL VAO1, VAO2 = SVRL + SDICODE (SVRH–SVRL)/256 SEN 8 SD(0:7) DUAL SDAC / AO2 SELECT LOAD SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 AO1 CONTROL ENABLE THERMAL SWITCH 6 VIDEO DACs 6 / 6 / / 04512-0-013 TSTM VID(0:5) Figure 13. Serial Interface Block Diagram SEN SCL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04512-0-014 SDI VAO1, VAO2 SEN t21 t24 SDI t22 t23 t25 D11 D10 D1 D0 VAO1, VAO2 t26 04512-0-015 t20 SCL Figure 14. Serial DAC Timing Table 11. Serial DAC Timing Parameter SEN to SCL Setup Time, t20 SCL, High Level Pulse Width, t21 SCL, Low Level Pulse Width, t22 SDI Setup Time, t24 SDI Hold Time, t25 SCL to SEN Hold Time, t23 VAO1, VAO2 Settling Time, t26 Conditions VFS = 5 V, to 0.5%, CL = 100 pF VFS = 5 V, to 0.5%, CL = 33 µF Rev. 0 | Page 14 of 24 Min 10 15 10 10 10 15 Typ Max 1 10 2 15 Unit ns ns ns ns ns ns µs ms AD8384 FUNCTIONAL DESCRIPTION The AD8384 is a system building block designed to directly drive the columns of LCD microdisplays of the type popularized for use in projection systems. It comprises six channels of precision, 10-bit digital-to-analog converters loaded from a single, high speed, 10-bit wide input. Precision current feedback amplifiers, providing well-damped pulse response and fast voltage settling into large capacitive loads, buffer the six outputs. Laser trimming at the wafer level ensures low absolute output errors and tight channel-to-channel matching. Tight part-to-part matching in high resolution systems is guaranteed by the use of external voltage references. Three groups of level shifters convert digital inputs to high voltage outputs for direct connection to the control inputs of LCD panels. V1, V2 Inputs—Voltage Reference Inputs Two external analog voltage references set the levels of the outputs. V1 sets the output voltage at Code 1023 while the INV input is LOW; V2 sets the output voltage at Code 1023 while INV is held HIGH. VRH, VRL Inputs—Full-Scale Video Reference Inputs Twice the difference between these analog input voltages sets the full-scale output voltage VFS = 2 × (VRH – VRL). INV Control—Analog Output Inversion The analog voltage equivalent of the input code is subtracted from (V2 + VFS) while INV is held HIGH and added to (V1 –VFS) while INV is held LOW. Video inversion is delayed by six to 12 CLK cycles from the INV input. Transfer Function and Analog Output Voltage An edge detector conditions a high voltage reference timing input from the LCD and converts it to digital levels for use in a synchronizing timing controller such as the AD8389. Start Sequence Control—Input Data Loading A valid STSQ control input initiates a new 6-clock loading cycle during which six input data-words are loaded sequentially into six internal channels. A new loading sequence begins on the current active CLK edge only when STSQ was held HIGH at the preceding active CLK edge. The DecDriver has two regions of operation where the video output voltages are either above reference voltage V2 or below reference voltage V1. The transfer function defines the video output voltage as a function of the digital input code: VIDx(n) = V2 + VFS × (1 – [n/1023]), for INV = HIGH VIDx(n) = V1 - VFS × (1 – [n/1023]), for INV = LOW n = input code where: Right/Left Control—Input Data Loading VFS = 2 × (VRH – VRL) To facilitate image mirroring, the direction of the loading sequence is set by the R/L control. A number of internal limits define the usable range of the video output voltages, VIDx. See Figure 15. AVCC ≥ 1.3V V2 + VFS INV = HIGH Even/Odd Control—Input Data Loading Data is loaded on the rising CLK edges when this input is HIGH, and on the falling CLK edges when this input is LOW. XFR Control—Data Transfer to Outputs Data transfer to the outputs is initiated by the XFR control. Data is transferred to all outputs simultaneously on the rising CLK edge only when XFR was HIGH during the preceding rising CLK edge. VIDx (V) VOUTN(n) INTERNAL LIMITS AND USABLE VOLTAGE RANGES 0 ≤ VFS ≤ 5.5V 9V ≤ AVCC ≤ 18V V2 5.25V ≤ V2 ≤ (AVCC – 4) V1 VOUTP(n) 0 ≤ VFS ≤ 5.5V 5.25V ≤ V1 ≤ (AVCC – 4) INV = LOW V1 – VFS ≥ 1.3V AGND 0 1023 INPUT CODE Figure 15. Transfer Function and Usable Voltage Ranges Rev. 0 | Page 15 of 24 04512-0-016 A new loading sequence begins at Channel 0 and proceeds to Channel 5 when the R/L control is held LOW. It begins at Channel 5 and proceeds to Channel 0 when the R/L control is held HIGH. AD8384 ACCURACY Table 12. Bit Definitions To best correlate transfer function errors to image artifacts, the overall accuracy of the DecDriver is defined by two parameters: VDE and VCME. Bit Name VDE, the differential error voltage, measures the difference between the rms value of the output and the rms value of the ideal. The defining expression is VDE(n) = [VOUTN (n) – V 2] – [VOUTP(n) – V 1] ⎛ n ⎞ – ⎜1 – ⎟ × VFS 2 1023 ⎝ ⎠ Bit Functionality SD(0:7) 8-Bit SDAC Data. MSB = SD7. SD8 Not Used. SD9 Not Used. SD10 Output operating mode and SDAC selection control. SD11 Output operating mode and SDAC selection control. Table 13. Truth Table VCME, the common-mode error voltage, measures ½ the dc bias of the output. The defining expression is SD 1 ⎡ VOUTN (n) +VOUTP(n) (V 2 +V 1)⎤ – ⎥ ⎢ 2 2⎣ 2 ⎦ 11 10 9 8 Action 0 0 X X Load VAO2. No change to VAO1. No change to Grounded mode. 1 0 X X Load VAO1. Release outputs from Grounded mode. No change to AO2. 0 1 X X Release Video Outputs and VAO1 from Grounded Output mode. No change to VAO1 and VAO2 data. In normal operating mode, the voltage of the video outputs and VAO1 are determined by the inputs. 1 1 X X In Grounded Output mode, the video outputs and VAO1 are forced to AGND. Video Outputs and VAO1 to Grounded Output mode. No change to VAO1 and VAO2 data. X X X X No Change. VCME(n) = SEN TSTM CONTROL—TEST MODE A LOW on this input allows serial interface control of the output operating mode. A HIGH on this input forces the video outputs and VAO1 to normal operating mode. GROUNDED OUTPUT MODE OVERLOAD PROTECTION SERIAL DACS The overload protection employs current limiters and a thermal switch, protecting the video output pins against accidental shorts between any video output pin and AVCC or AGND. Both serial DACs are loaded via the serial interface. The output voltage is determined by the following equation: VAO1, VAO2 = SVRL + SD(0:7) × (SVRH – SVRL)/256 The junction temperature trip point of the thermal switch is 165°C. Production test guarantees a minimum junction temperature trip point of 125°C. Consequently, the operating junction temperature should not be allowed to rise above 125°C. For systems that operate at high internal ambient temperatures and require large capacitive loads to be driven by the AD8384 at high frequencies, a minimum airflow of 200 lfm should be maintained to ensure junction temperatures below 125°C. 3-WIRE SERIAL INTERFACE The serial interface controls two 8-bit serial DACs, the overload protection and the video output operating mode via a 12-bit wide serial word from a microprocessor. Four of the 12-bits select the function and the remaining eight bits are the data for the serial DACs. Output VAO1 is designed to drive very large capacitive loads above 0.047 µF. Lower capacitive loads may result in excessive overshoot at VAO1. LEVEL SHIFTERS The characteristics of the level shifters are optimized based on their intended use. Seven level shifters—DX, CLX, CLXN, and ENBX(1:4)—are optimized for “X direction,” and three—DY, CLY, and CLYN— are optimized for the “Y direction” control signals. One level shifter, NRG, is designed to drive a large capacitive load and optimized for an X direction control signal and two, DIRX and DIRY are optimized for very low frequency control signals. One level shifting edge detector, MONITI, MONITO, is optimized to condition a synchronizing feedback reference signal from the LCD. Rev. 0 | Page 16 of 24 AD8384 APPLICATIONS AD8384 6-CHANNEL LCD VID(0:5) DB(0:5) CHANNEL 0–5 STSQ, XFR, CLK, R/L, INV DIRXIN, DIRYIN, DYIN, CLYIN, NRGIN DIRX, DIRY, DY, CLY, CLYN, NRG LCD TIMING CONTROLS DXIN, CLXIN, ENBXIN (1–4) DX, CLX, CLXN, ENBX (1–4) LCD TIMING CONTROLS IMAGE PROCESSOR 1/3 AD8389 DXI, CLXI, ENBX(1–4)I CLK DXxO, CLXxO, ENBX(1–4)xO MONITxI MONITO MONITI VAO1 SDI µP SCL MONITOR VCOM VAO2 SEN DC REFERENCE VOLTAGES 04512-0-017 VRH, VRL, V1, V2, SVRH, SVRL Figure 16. Typical Applications Circuit POWER SUPPLY SEQUENCING As indicated under the Absolute Maximum Ratings, the voltage at any input pin cannot exceed its supply voltage by more than 0.5 V. To ensure compliance with the Absolute Maximum Ratings, the following power-up and power-down sequencing is recommended. During power-up, initial application of nonzero voltages to any of the input pins must be delayed until the supply voltage ramps up to at least the highest maximum operational input voltage. During power-down, the voltage at any input pin must reach zero during a period not exceeding the hold-up time of the power supply. Power ON Failure to comply with the Absolute Maximum Ratings may result in functional failure or damage to the internal ESD diodes. Damaged ESD diodes may cause temporary parametric failures, which may result in image artifacts. Damaged ESD diodes cannot provide full ESD protection, reducing reliability. To Ensure Grounded Output Mode at Power-Off If references are active sources: 1. Program Grounded Output mode 2. Turn off references 3. Turn off AVCC 4. Turn off DVCC Sequence the applied voltages starting with the highest and proceeding toward the lowest. Apply AVCC and then proceed with applying the voltages in a decreasing order, for example VRH, V2, and so on. Apply DVCC last. If references are passive voltage dividers dependent on AVCC: Power OFF Remove voltages starting with the lowest and proceed toward the highest. Remove DVCC and then proceed with the voltages in an increasing order, for example V1, V2, VRH, and so on. Remove AVCC last. 1. Program Grounded Output mode 2. Set AVCC to 5 V 3. Hold for 1 ms 4. Turn off DVCC 5. Turn off AVCC Rev. 0 | Page 17 of 24 AD8384 VBIAS GENERATION—V1, V2 INPUT PIN FUNCTIONALITY APPLICATIONS CIRCUIT In order to avoid image flicker, a symmetrical ac voltage is required and a bias voltage of approximately 1 V minimum must be maintained across the pixels of HTPS LCDs. The AD8384 provides two methods of maintaining this bias voltage. Internal Bias Voltage Generation The circuit in Figure 18 ensures VBIAS symmetry to within 1 mV with a minimum component count. Bypass capacitors are not shown for clarity. Note from the curve in Figure 20 that the AD8132 (Figure 18) typically produces a symmetrical output at 85°C when its supply, (V+) – (V–), is at 7.2 V. Standard systems that internally generate the bias voltage reserve the upper-most code range for the bias voltage, and use the remaining code range to encode the video for gamma correction. In these systems, a high degree of ac symmetry is guaranteed by the AD8384. AVCC = 15.5V VZ = 5.1V The V1 and V2 inputs in these systems are tied together and are normally connected to VCOM, as shown in Figure 17. AD8384 3 1 –IN V2 = 8V 5 V+ V2 2 VCOM VCOM = 7V AD8132 8 R2 = 1kΩ +IN V– 4 V1 = 6V V1 R1 = 6kΩ VFS = 5V DVCC = 3.3V AD8384 V2 V1 VBIAS = 1V Figure 18. External VBIAS Generator with the AD8132 VCOM VBIAS = 1V 1023 RESERVED CODE RANGE 04512-0-018 VFS = 5V 820 VFS = 4V Figure 17. V1, V2 Connection and Transfer Function in a Typical Standard System V2 VBIAS = 1V VCOM VBIAS = 1V V1 External Bias Voltage Generation 04512-0-025 VFS = 4V In systems that require improved brightness resolution and higher accuracy, the V1 and V2 inputs, connected to external voltage references, provide the necessary bias voltage (VBIAS) while allowing the full code range to be used for gamma correction. Figure 19. AD8384 Transfer Function in a Typical High Accuracy System 8.75 To ensure a symmetrical ac voltage at the outputs of the AD8384, VBIAS must remain constant for both states of INV. Therefore, V1 and V2 are defined as V2 = VCOM + VBIAS 7.50 6.25 5.00 (V2 + V1)/2 – VCOM (mV) V1 = VCOM – VBIAS 1023 3.75 TA = 25°C TA = 85°C 2.50 1.25 0.00 –1.25 –2.50 –3.75 –5.00 –6.25 –7.50 –8.75 5.7 6.2 6.7 7.2 7.7 8.2 8.7 [V+] – [V–] (V) 9.2 9.7 10.2 10.7 04512-0-020 VCOM 04512-0-019 6 Figure 20. Typical Asymmetry at the Outputs of the AD8132 vs. Its Power Supply for the Application Circuit Rev. 0 | Page 18 of 24 AD8384 PCB DESIGN FOR OPTIMIZED THERMAL PERFORMANCE The AD8384’s total maximum power dissipation is partly load dependent. In a 6-channel 60Hz XGA system running at a 65 MHz clock rate, the total maximum power dissipation is 1.6 W at a 150 pF LCD input capacitance. At a clock rate of 100 MHz, the total maximum power dissipation can exceed 2 W, as shown in Table 14, for a black-towhite video output voltage swing of 4 V and 5 V. Table 14. Power Dissipation CLOAD (pF) 150 200 250 300 PQUIESCENT (W) 1.12 1.12 1.12 1.12 VSWING = 5 V PDYNAMIC PTOTAL (W) (W) 0.82 1.94 1.01 2.13 1.21 2.33 1.41 2.53 VSWING = 4 V PDYNAMIC PTOTAL (W) (W) 0.71 1.83 0.86 1.98 1.01 2.13 1.17 2.29 Although the maximum safe operating junction temperature is higher, the AD8384 is 100% tested at a junction temperature of 125°C. Consequently, the maximum guaranteed operating junction temperature is 125°C. To limit the maximum junction temperature at or below the guaranteed maximum, the package, in conjunction with the PCB, must effectively conduct heat away from the junction. A thermally effective PCB must incorporate two thermal pads and a thermal via structure. The thermal pad on the top surface of the PCB provides a solderable contact surface on the top surface of the PCB. The thermal pad on the bottom PCB layer provides a surface in direct contact with the ambient. The thermal via structure provides a thermal path to the inner and bottom layers of the PCB to remove heat. THERMAL PAD DESIGN To minimize thermal performance degradation of production PCBs, the contact area between the thermal pad and the PCB should be maximized. Therefore, the size of the thermal pad on the top PCB layer should match the exposed paddle. The second thermal pad of the same size should be placed on the bottom side of the PCB. At least one thermal pad should be in direct thermal contact with an external plane such as AVCC or GND. THERMAL VIA STRUCTURE DESIGN Effective heat transfer from the top to the inner and bottom layers of the PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmically with the number of vias. Near optimum thermal performance of production PCBs is attained only when tightly spaced thermal vias are placed on the full extent of the thermal pad. The AD8384 package is designed to provide enhanced thermal characteristics through the exposed die paddle on the bottom surface of the package. In order to take full advantage of this feature, the exposed paddle must be in direct thermal contact with the PCB, which then serves as a heat sink. Rev. 0 | Page 19 of 24 AD8384 AD8384 PCB DESIGN RECOMMENDATIONS 14 mm 6 mm Top PCB Layer Land Pattern Dimensions 04512-0-021 14 mm 6 mm Pad Size: 0.6 mm × 0.25 mm Pad Pitch: 0.5 mm Thermal Pad Size: 6 mm × 6 mm Thermal via structure: 0.25 mm to 0.35 mm diameter via holes on a 0.5 mm to 1.0 mm grid. LAND PATTERN – TOP LAYER Figure 21. Land Pattern—Top Layer 6 mm 6 mm Bottom PCB Layer Thermal Pad and Thermal Via Connections LAND PATTERN – BOTTOM LAYER 04512-0-022 The thermal pad on the solder side is connected to a plane. Use of thermal spokes is not recommended when connecting the thermal pads or via structure to the plane. Figure 22. Land Pattern—Bottom Layer Solder Masking Solder masking of the via holes on the top layer of the PCB plugs the via holes, inhibiting solder flow into the holes. To minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), the via diameter should be made small and an optional solder mask may be used. To optimize thermal pad coverage, the solder mask’s diameter should be no more than 0.1 mm larger than the via hole diameter. Solder Mask—Top Layer Thermal Via Holes: Circular mask, centered on the via holes. Diameter of the mask should be 0.1 mm larger than the via hole diameter. SOLDER MASK – TOP LAYER Figure 23. Solder Mask—Top Layer Solder Mask—Bottom Layer Set by customer’s PCB design rules. Rev. 0 | Page 20 of 24 04512-0-023 Pads: Set by the customer’s PCB design rules. AD8384 OUTLINE DIMENSIONS 14.00 SQ 1.20 MAX 0.75 0.60 0.45 12.00 SQ 80 60 60 SEATING PLANE 80 61 61 1 1 PIN 1 TOP VIEW (PINS DOWN) BOTTOM VIEW 20 41 21 6.00 SQ 20 41 40 40 21 0.15 0.05 1.05 1.00 0.95 7° 3.5° 0° 0.20 0.09 COPLANARITY 0.08 0.50 BSC 0.27 0.22 0.17 GAGE PLANE 0.25 COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 24. 80-Lead, Thermally Enhanced Thin Quad Flatpack Package [TQFP] (SV-80) Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model AD8384ASVZ11 11 Temperature Range 0°C to 85°C Package Description 80-Lead Thin Quad Flat Pack Z = Pb-free part. Rev. 0 | Page 21 of 24 Package Option SV-80 AD8384 NOTES Rev. 0 | Page 22 of 24 AD8384 NOTES Rev. 0 | Page 23 of 24 AD8384 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04512–0–1/04(0) Rev. 0 | Page 24 of 24