TI TPS658600ZQZR

TPS658600
www.ti.com
SLVSA37 – DECEMBER 2009
Advanced Power Management Unit
Check for Samples: TPS658600
1 INTRODUCTION
1.1
MAIN FEATURES
1
• BATTERY CHARGER
– Complete Charge Management Solution for a
Single Cell Li-Ion/Li-Pol Cell With Dynamic
Power Management and Thermal Foldback.
– Maximum 1.0A charge current
– Programmable Adapter and USB Charge
Operation
• INTEGRATED POWER SUPPLIES
– 3 Programmable Step-Down converters
• Software Controlled Enable/Forced PWM
Mode
• Automatic Power Saving Mode
• Maximum 1.2A Outputs
– 11 Programmable General Purpose LDOs
• 7 With Output Voltages of 1.25V to 3.3V
• 2 With Output Voltages of 0.725V to 1.5V
or 1.25V to 2.586V (factory configurable)
• 1 “Always On” With Output Voltages of
1.25V to 3.3V
• 1 With Output Voltage of 1.70V–2.475V
• DISPLAY SUPPORT FUNCTIONS
– 4 PWM Outputs With Programmable
Frequency and Duty Cycle
– Dual RGB LED Drivers
– Constant Current WLED Driver
• 26.5V (max) at 25mA
• Over-Voltage Protection
• Programmable Current Level and
Brightness Control
• HOST INTERFACE
– Interrupt Controller With Maskable Interrupts
– External ADC Triggering and Step-Down
Converter Mode Control
• SYSTEM MANAGEMENT
– Dual Input Power Path
• USB Current Limiting
• Max 18V Over-Voltage Protection
– Power Good Monitoring on all Supply
Outputs
– Software Reset Function
– Hardware On/Off and Reboot Control
– 11 Channel ADC With 3 Operating Modes
• Single Conversion
• Peak Detection
• Averaging
1.2
•
•
•
APPLICATIONS
Smart Phones
Portable Navigation Devices
Portable Media Players
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS658600
SLVSA37 – DECEMBER 2009
1.3
www.ti.com
OVERVIEW
The TPS658600 provides an easy to use, fully integrated solution for handheld devices, integrating charge
management, multiple regulated power supplies, system management and display functions in a small 6x6
package. The I2C interface enables control of a wide range of subsystem parameters. Internal registers
have a complete set of status information, enabling easy diagnostics and host-controlled handling of fault
conditions.
1.4
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
(3)
(4)
2
PART NUMBER (2)
(3)
TPS658600
PACKAGE (4)
PACKAGE DESIGNATOR
ORDERING (2)
PACKAGE MARKING
MicroStar BGA
ZQZ
TPS658600
TPS658600
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The TPS658600 is only available taped and reeled. Quantities are 2,500 devices per reel.
Devices with distinct part numbers have unique factory configurations for supply defaults, sequencing and other functions. Consult the
factor for configuration information for each part number.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
ELECTRICAL SPECIFICATIONS
Copyright © 2009, Texas Instruments Incorporated
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TPS658600
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SLVSA37 – DECEMBER 2009
2 ELECTRICAL SPECIFICATIONS
2.1
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNITS
AC and USB with respect to AGND1
–0.3 V to 18 V
ANLG1, ANLG2, ANLG3 with respect to AGND2
–0.3 V to 6.5 V
V(SYS), V(VIN_CHG) with respect to AGND1
–0.3 V to 6.5 V
VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9 with respect to AGND1
–0.3 V to 6.5 V
ADC_REF with respect to AGND2
–0.3 V to 3.6 V
RTC_OUT with respect to V(SYS)
–5.5 V to 3.6 V
RTC_OUT with respect to AGND1
–0.3 V to 3.6 V
LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9, V2V2 and TS with respect to AGND1
–0.3 V to 3.6 V
V32K with respect to AGND1
–0.3 V to 3.6 V
TS with respect to V2V2
–2.3 V to 0.3 V
SM0, L0, VIN_SM0 with respect to PGND0
–0.3 V to 6.5 V
SM1, L1, VIN_SM1 with respect to PGND1
–0.3 V to 6.5 V
SM2, L2, VIN_SM2 with respect to PGND2
–0.3 V to 6.5 V
SM3 , L3 with respect to PGND3
–0.3 V to 29 V
SM3SW with respect to PGND3
–0.3 V to 29 V
FB3 with respect to PGND3
–0.3 V to 0.5 V
V(BAT) with respect to AGND1, Battery power only
–0.3 V to 4.6 V
All other pins (except AGNDn and PGNDn) with respect to AGND1
–0.3 V to 6.5 V
AGND2, AGND3, , DGND1, DGND2DT, PGND0, PGND1, PGND2, PGND3 with respect to AGND1
–0.3 V to +0.3 V
Input Current, AC pin
Defined by ILIM
Input Current, USB pin
Defined by ILIM
Output continuous current, SYS, VIN_CHG pins
2500 mA
Output continuous current, BAT pin
–3000 mA
Continuous Current at L0, PGND0, L1, PGND1
1500 mA
Continuous Current at L3, PGND3
1000 mA
Continuous Current at L2, PGND2
2000 mA
Operating free-air temperature, TA
–40°C to 85°C
Maximum junction temperature, TJ
125°C
Storage temperature, TSTG
–65°C to 150°C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
260°C
HBM rating , all pins
2 kV
MM rating, all pins
100 V
(1)
2.2
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
Psi_Jb
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 55°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
ZQZ
25°C/W
4000 mW
40.0°C/W
2800 mW
2200 mW
1600 mW
ELECTRICAL SPECIFICATIONS
Copyright © 2009, Texas Instruments Incorporated
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TPS658600
SLVSA37 – DECEMBER 2009
2.3
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
AC and USB with respect to AGND1
4.30
16.5 (1)
V
V(SYS) with respect to AGND1
2.9
5.5
V
V(BAT) with respect to AGND1, battery power only
2.9
4.6
V
V(BAT) with respect to AGND1, battery connected, AC or USB
power selected, Selected power source >2.9V
2.15
4.6
V
0
2.6
V
VIN_LDO01, VIN_LDO23, VIN_LDO678, VIN_LDO4, VIN_LDO9
with respect to AGND1
Greater of : 1.7V OR Minimum input voltage
required for LDO/Converter operation outside
dropout region
5.5
V
VIN_SM0 with respect to PGND0
Greater of : 2.3V OR Minimum input voltage
required for LDO/Converter operation outside
dropout region. 2.9V to meet parametric
specifications.
5.5
V
VIN_SM1 with respect to PGND1
28
V
VIN_SM2 with respect to PGND2
28
V
VIN_SM4 with respect to PGND4
28
V
SM3 with respect to PGND3
28
V
V
ANLG1,ANLG2, ANLG3 with respect to AGND2
GPIOx with respect to AGND1
0
5.5
All other pins (except AGNDn and PGNDn) with respect to AGND1
0
5.5
V
Operating free-air temperature, TA
-40
85
°C
Maximum junction temperature, TJ , functional operation
-40
125
°C
0
125
°C
1 V/mSec
1 V/μSec
Maximum junction temperature, TJ , electrical characteristics
External supply ramp rate, AC or USB pins
(1)
4
Thermal operating restrictions are reduced or avoided if input voltage does not exceed 5V.
ELECTRICAL SPECIFICATIONS
Copyright © 2009, Texas Instruments Incorporated
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TPS658600
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2.4
SLVSA37 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
375
μA
QUIESCENT CURRENT – V(BAT) = 4.2V NO EXTERNAL LOADS AT SYS PIN OR SUPPLY OUTPUTS
Quiescent current, 6586x in normal or sleep
mode. All supplies, peripherals and charger off
IQ(ON)
IQ(DIGITAL)
IQ(SMn)
Quiescent current, control logic
Power path active, control logic in low power mode (1)
716
870
μA
SM0, SM1: enabled, PFM mode, from SYS pin
14
25
μA
SM2: enabled, PFM mode, from SYS pin
19
32
Control logic in high power mode
SM0, SM1, SM2 operating quiescent current
(2)
584
SM0, SM1, SM2: enabled, PWM mode, from VINSMn pin
6
IQ(LDOx)
LDO quiescent current, All but one LDOx
disabled
I(LDOx) = no external load
24
29
μA
I(LDOx) = –1 mA
24
150
μA
I(LDOx) = –50 mA
160
LDO disabled, TJ = 85°C
SM3 enabled, not switching
IQ(SM3)
SM3 operating quiescent current
(3)
ADC operating quiescent current
IQ(V32K)
V32K supply bias current , 32k buffer enabled
30
μA
200
μA
μA
Conversion active
1
mA
170
μA
Not converting, waiting for trigger
45
μA
RTC_OUT disabled via I C, TJ = 85°C . Externally applied
V(RTC_OUT) = 2 V supplies real time clock counters and xtal
oscillator
15
μA
32k buffer enabled, 100 pF external load
24
μA
8
μA
27
2
(4)
Disabled via I2C
Charger quiescent current
μA
1
Charger enabled, termination detected
IQ(CHG)
μA
15
Disabled via I C
RTC_OUT LDO enabled
RTC_OUT pin quiescent current
3
1
ADC disabled via I2C
IQ(RTC)
μA
1
Enabled, switching
2
IQ(ADC)
μA
1
disabled via I2C
μA
mA
40
Charger enabled, termination disabled, charge current=0 (3)
Charger disabled
10
50
μA
2
mA
20
μA
I2C INTERFACE TIMING – SDA, PSDA, PSCLK, SCLK (3)
TR
SCLK/SDATA rise time
300
ns
TF
SCLK/SDATA fall time
300
ns
TW(H)
SCLK pulse width high
600
ns
TW(L)
SCLK Pulse Width Low
1.3
μs
TSU(STA)
Setup time for START condition
600
ns
TH(STA)
START condition hold time after which first clock
pulse is generated
Pull-up resistors connected to 2.2V
600
ns
TSU(DAT)
Data setup time
100
ns
TH(DAT)
Data hold time
0
ns
TSU(STOP)
Setup time for STOP condition
600
ns
T(BUF)
Bus free time between START and STOP
condition
1.3
μs
FSCL
Clock Frequency
400
kHz
0.4
V
I2C BUFFERS – SDA, PSDA, PSCLK, SCLK
VIL(I2C)
Low level input voltage
VIH(I2C)
High level input voltage
VOL(I2C)
Low level output voltage
SDA, PSDA configured as output, IOL=3mA
IO(I2C)
Maximum load current (3)
SDA, PSDA configured as output
ILKG(I2C)
Input current
V(pin)=5V or 0V
CI2C
Input pin capacitance
SDAT, SCLK, PSDAT, PSCLK pins
CI2CBUS
(1)
(2)
(3)
(4)
2
I C bus capacitance
1.15
SDAT, SCLK, PSDAT, PSCLK
V
0.4
V
8
mA
1.0
μA
10
pF
400
pF
2
Control logic in low power mode when all functions are off and no I C communication is on going
Control logic in high power mode when one of the following events happen: 6586x in power-up/rtc/rtc_on/supplyseq states, any
converter in PWM mode, SM3 enabled, PWM driver enabled, ADC conversion on-going, I2C communication on-going, voltage transition
for DVM supplies on-going, charger on, AC or USB supply detected, initial power-up cycle.
Not production tested.
External voltage supplied by supercap or coin cell connected to RTC_OUT pin, see application diagram for details.
ELECTRICAL SPECIFICATIONS
Copyright © 2009, Texas Instruments Incorporated
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SLVSA37 – DECEMBER 2009
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT BUFFERS: RESUME, SM0EN, SM1EN, HOTRST, LDO4EN, SYNCEN
VIL(DIG)
Low level input voltage
VIH(DIG)
High level input voltage
ILKG(DIG)
Input current
RDIG
Internal resistor
0.4
V
0.1
μA
1.15
V
V(pin)=5V
RESUME pin , pull-down to AGND
55
100
150
HOTRST pin, pull-up to V2V2
55
100
150
kΩ
PUSH-PULL OUTPUT BUFFERS, USER SELECTABLE OUTPUT VOLTAGE – NORTC, NOPOWER
VBFRPWR
Buffer positive supply
Internally connected to V32K pin
1.1 to 3.3
V
IOL = 3 mA, V32K = 1.5 V
0.6
IOL = 10 μA, V32K > 1.1 V
0.1
VOL(OBFR)
Low level output voltage
V
High level output voltage, referenced to output
buffer supply, NORTC
IOH = 1.4 mA, V32K = 1.5 V
V32K-0.6
VOH(OBFR)
IOH = -10 μA, V32K = 1.1 V
V32K-0.11
High level output voltage, referenced to output
buffer supply,NOPOWER
IOH = 1.4 mA, V32K = 1.5 V
V32K-0.6
VOH(OBFR)
IOH = -10 μA, V32K = 1.1 V
V32K-0.11
IOL(OBFR)
Maximum low level sink current load (1)
V(pin) = 2.5 V
IOH(OBFR)
Maximum high level source current load (1)
V(pin) = 0 V
V
V
5
–5
mA
mA
OPEN DRAIN OUTPUT BUFFERS – INT
VOL(OBFR)
Low level output voltage
ILKG(OBFR)
Output leakage current
IOL = 3 mA, V32K = 1.5 V
0.6
IOL = 10 μA, V32K > 1.1 V
0.1
Output buffer, open-drain mode, V(pin)=5.5V
0.1
V
μA
PUSH-PULL OUTPUT BUFFERS – LDO4PG, SM0PG, SM1PG, CHGSTAT
IOL = 3 mA
0.6
IOL = 10 μA
0.1
VOL(DBFR)
Low level output voltage
V
High level output voltage , buffer configured as
push-pull via I2C
IOH = 3 mA
1.5
VOH(DBFR)
IOH = –10 μA
1.8
IOL(DBFR)
Maximum low level sink current load (1)
V(pin) = 2.5 V
IOH(DBFR)
Maximum high level source current load (1)
V(pin) = 0 V
V
5
–5
mA
mA
32kHz OUTPUT BUFFER , V(32K)=1.7V (min), UNLESS OTHERWISE STATED
Externally applied bias rail for output driver (1)
V32B
Buffer supply voltage
1.0
3.6
V(32K) = 1.1 V, IOL = 100 μA
VOL
Output low level
VOH
Normal operation
TF, TR
Rise/fall time
VJITTER
V
0.05
V(32K) = 1.1 V, IOL = 1 mA
0.2
V(32K) = 1.5 V, IOL = 5 mA
0.5
V(32K) = 1.1 V, IOH = -1 μA
V32K-0.05
V(32K) = 1.5 V, IOH = 5 mA
V32K-0.5
V
V
32 kHz clock driving 50pF load cap
15
Peak to peak
15
RMS
15
ns
Output jitter
ns
32kHz CLOCK AND 32K SWITCHING TIMING
TXTAL
XTAL oscillator stabilization time (1)
Frequency within 2% of typical value, frequency defined by XTAL
characteristics
F32K
Internal 32 kHz clock
Frequency
2
s
kHz
28
32
36
-3%
1.85
3%
INTERNAL REFERENCES AND POR
VUVLO
Internal UVLO detection threshold
V(2V2) decreasing
VUVLO_HYS
UVLO detection hysteresis
V(2V2) increasing from decreasing trigger point
VO(2V2)
Output Voltage
Always on,
2.1
ISH2V2
Short Circuit current limit
V(2V2)=0v
18
(1)
6
120
2.2
V
mV
2.3
V
mA
Not production tested.
ELECTRICAL SPECIFICATIONS
Copyright © 2009, Texas Instruments Incorporated
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TPS658600
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2.5
SLVSA37 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RTC_OUT LDO
VO(RTC_OUT)TYP=1.25, 1.50, 1.8, 2.5,
2.7,2.85,3.1,3.3
Output Voltage, Selectable via I2C (1)
Dropout voltage, I(RTC_OUT) = –15 mA
V(SYS) = 2.8 V
VO(RTC_OUT)
RTC_OUT output voltage
600
Total accuracy, V(AC):2V to 4.7V, –15mA load,
V(BAT1)=V(BAT2)=V(USB)=0V
–5%
V
mV
5%
Load regulation, V(AC)=3.5V,
load: 1mA → –15mA
1%
Line regulation, 5mA load,V(AC): 3.5V→18V,
V(BAT1) =V(BAT2) =V(USB) =0V
1%
ISHRTC
Short Circuit current limit
20
2.3
2.35
2.45
V(RTCGOOD)
RTC_OUT power good fault detection
threshold
mA
Falling RTC_OUT pin voltage, set via I2C
1.8
1.90
2.0
VHYS(RTC)
Power good fault detection hysteresis
Rising RTC_OUT pin voltage (Referenced to V(RTCGOOD) threshold)
VUVLO_RTC
Internal RTC UVLO detection threshold
VRTC Decreasing
VUVLO_RTC_HYS
UVLO detection hysteresis
Power-on-reset delay (2)
V
50
75
131
–10%
1.5
10%
mV
V
VRTC Increasing
100
150
200
mV
Fixed time, measured from 2V2>UVLO
7.2
8
8.8
ms
BOOT-UP TIMING
TPOR
Fixed time
500
TBOOT
Boot-up time
ms
THOTPLUG
Hot plug deglitch time
Fixed time
675
750
825
TWAKEUP
Wakeup pulse width
Fixed time
225
250
275
μs
TCHECK
RTC check wait time
Fixed time
2.7
3
3.3
ms
TMAX
RTC_ON watchdog timer
Fixed time
4×TNORTC
Fixed time
10
Accuracy, referenced to TBOOT(tTYP)
TNORTC
NORTC pin pulse width value
KNOPOWER
NOPOWER pin pulse width const.
TWAIT
Reboot and sleep request timeout
Accuracy, relative to TNORTC (TYP)
(2)
Fixed time
Measured from all supplies synchronized
Supply sync delay time
Accuracy, relative to TSYNCDLY(TYP)
ms
ms
10%
ms/nF
Regulator specific. See Table 3-17
TSYNCDLY
ms
0.25
Pulse width accuracy, CNOPOWER < 400nF
Synchronization complete delay
10%
–10%
TNOPOWER = KNOPOWER × CNOPOWER
TWAIT1
TSYNCEND
–10%
(2)
–25%
25%
18
20
22
ms
4.5
5
5.5
ms
4.5
5
5.5
ms
TSYNCDLY(TYP) = 1.25, 2.5, 3.75, 15,
20, 32, 40, 64
-10
ms
+10
POWER GOOD AND THERMAL FAULT DETECTION
TDGL(PGFLT)
Power good deglitch time
Applies to all non-masked power good signals, output voltage
falling edge.
TSHUT
Thermal shutdown
Increasing junction temperature
150
THYS(SHUT)
Thermal shutdown hysteresis
Decreasing junction temperature
30
TDGL(TSHUT)
Thermal shutdown detection delay
Rising temperature
(1)
(2)
4
15
5
20
6
ms
°C
°C
25
μs
Setting the RTC_OUT output voltage below the RTC_OUT power good threshold will result in a NORTC pulse being always generated
during reboot cycles or when exiting sleep.
Setting the RTC_OUT output voltage below VUVLO_RTC disables the use of the internal real time clock counter and xtal oscillator.
Not production tested.
ELECTRICAL SPECIFICATIONS
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESUME CONTROL TIMING
TRESUME(H)
RESUME pulse width high (1)
550
ms
TRESUME(L)
RESUME pulse width low (1)
1500
ms
SEQUENCER REBOOT CONTROL
VHOTRST
Reboot control threshold
THRST(H)
HOT_RST max pulse width
TDT(HRST)
HOT_RST min detection pulse width
Reboot started when normal state is set and
V(HOT_RST) < VREBOOT for
t > TDT(HRST)
HOT_RST deglitch
4
0.4
V
60
ms
16
μs
2
%
EXTERNAL SUPPLY DETECTION AND STATUS
System voltage V(SYS) decreasing.
3.0
VLOWSYS
Minimum system voltage detection threshold
VHYS(LOWSYS)
Minimum system voltage detection hysteresis
V(SYS) increasing from decreasing trigger point
TDGL(LOWSYS)
Minimum system voltage detection deglitch
time
V(SYS) decreasing
VIN(DT)
Input voltage detection threshold. Input voltage AC detected when V(AC)–V(BAT) > VIN(DT) AND V(AC) > VACMIN
increasing, referenced to battery voltage
USB detected when V(USB)–V(BAT) > VIN(DT)
VIN(NDT)
Input voltage removal threshold. Input voltage
decreasing, referenced to battery voltage
VACMIN
AC detection threshold, relative to GND
TDGLAC(DT)
TDGLUSB(DT)
VIN(OVP)
Input over voltage detection
TDLY(INOVP)
Input over voltage detection delay
Total accuracy, referenced to V(LOWSYS)TYP
-2
V
200
mV
5
ms
180
mV
AC not detected:
when V(AC)–V(BAT) < VIN(NDT) USB not detected when
V(USB)–V(BAT)< VIN(NDT)
65
mV
AC voltage decreasing , AC not detected when V(AC) < VACMIN
3.5
V
Hysteresis, AC voltage increasing
200
mV
AC Power detected deglitch
AC voltage increasing
22.5
ms
USB Power detected deglitch
USB voltage increasing
5.5
5.8
Rising AC or USB voltage
6.0
ms
6.3
V
μs
100
ANALOG COMPARATOR
VCOMPDET
Voltage threshold
Enabled at sleep mode not set
IQCDET
Bias current (1)
Always On
TP
Propagation time
V(COMP):0→1.5V→0, measured from input to
NOPOWER:HI→LO
(1)
8
1.21
1.245
50
1.28
V
5
μA
μs
Not production tested.
ELECTRICAL SPECIFICATIONS
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Product Folder Link(s): TPS658600
TPS658600
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2.6
SLVSA37 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER PATH CURRENT LIMIT AND PROTECTION FUNCTIONS
IUSB100
Selected input current limit, applies to USB input
only
IUSB500
Selected Input switch not in dropout. I2C
settings: USBMODE=HI, USBLIMIT=LO
–40°C < TA < 85°C
90
100
–25°C < TA < 85°C
92
100
435
500
Selected Input switch not in dropout. I2C settings: USBMODE=HI,
USBLIMIT=HI
mA
Input current limit range, AC input
2.75
mA
A
Selected input current limit, applies to AC input
Total accuracy, relative to IINLIM(TYP)
IINLIM
–20%
Input current limit range, USB input configured with USBMODE=LO
20%
2.11
A
Selected input current limit, applies to USB input
Total accuracy, relative to IINLIM(TYP)
–12.5%
TOVSH
Input current limit transient time
Load at SYS pin: 80% of current limit value to 120% of regulation value
(IINLIM, IUSB100 or IUSB500). Time measured from load transient to input current
within regulation limits.
IOVSHPKUSB
Input current limit overshoot
Load at SYS pin: 80% of current limit value to 120% of regulation value
(IINLIM, IUSB100 or IUSB500),
t < TOVSH
VSH(SYS)
SYS power path Short Circuit detection threshold
All power path switches set to OFF if V(SYS) < VSH(SYS)
RFLT(USB)
SYS short circuit recovery pull-up resistor
V(SYS) < VSH(SYS), internal resistor connected from USB to SYS
RFLT(AC)
SYS short circuit recovery pull-up resistor
V(SYS) < VSH(SYS), internal resistor connected from AC to SYS
IBATSYS
Battery switch over-current detection
TDGL(BATSYS) Battery switch over-current detection delay
μs
20
20%
1.6
1.8
2.0
Ω
550
2.18
Short circuit detection blanked for TDGL(BATSYS), measured from batt
switch: OFF->ON or initial sys power path enable
100
IFLT(SYS)
Battery switch over-current recovery pull-up current V(BAT) –V(SYS) > VOC(SYS), internal current source connected from BAT to
source
SYS
VSUP(SYS)
Supplement detection threshold
Battery switch ON at V(BAT)-V(SYS) > VSUP(SYS)
Battery switch OFF at V(BAT)-V(SYS)<VSUPNDT(SYS)
110
V
Ω
550
Battery switch already turned on or sys power path enabled
VSUPNDT(SYS) Supplement mode not detected threshold
12.5%
2.54
A
120
ms
1
ms
30
mA
40
mV
7
mV
POWER PATH INTEGRATED MOSFETS CHARACTERISTICS
VACDO
AC switch dropout voltage
VACDO = V(AC)-V(SYS); V(AC)=4V AC input current limit set to 2.0A (typ)
IO(SYS) = 1.0A
190
240
USB switch dropout voltage
VUSBDO = V(USB)-V(SYS);
V(USB)=4.6V
I(SYS)+I(BAT)= 0.425A
VUSBDO
I(SYS)+I(BAT)= 85mA
240
VBATDODCH
Battery Switch dropout voltage, discharge
mV
mV
VBATDODCH = V(BAT)-V(SYS), V(BAT)=3V,
I(BAT)= 1A
40
155
mV
POWER PATH TIMING CHARACTERISTICS
TSW(ACBAT)
Switching from AC to BAT
No USB, AC power removed
150
μs
TSW(USBBAT)
Switching from USB to BAT
No AC, USB power removed
150
μs
POWER PATH DISCHARGE SWITCHES
IDCH(AC)
AC pin discharge current
Always ON, V(AC) > 1 V
100
μA
IDCH(USB)
USB pin discharge current
Always ON, V(USB) > 1 V
100
μA
SM0, SM1, SM2 DC/DC CONVERTERS
VSMUV
RDS(ON)
Low input voltage detection threshold, input voltage Converter turned OFF at V(VIN_SMn) < VSMUV
decreasing
Hysteresis , rising input voltage
100
mV
High side MOSFET on-resistance
VIN_SMx = 3.6V, 100% duty cycle
200
mΩ
Low side MOSFET on-resistance
VIN_SMx = 3.6V, 0% duty cycle
200
ILK_HS
High side leakage current
ILK_LS
Low side leakage current
2.0
TJ = 85°C
2.9V ≤ VIN_SMx ≤ 5.5V
μA
1
μA
1550
1860
SM2 (snubber enabled)
1550
1860
2.025
2.25
2.475
–13.0%
–10%
–7.0%
High side and low side current limit
fSW
Oscillator frequency
PWM mode
Power good threshold
Power fault detection, Voltage decreasing, referenced to programmed
output voltage
VSMPG
mΩ
1
SM0, SM1
ILIM
V
mA
Hysteresis, voltage increasing, referenced to VSMPG
5%
ELECTRICAL SPECIFICATIONS
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9
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SLVSA37 – DECEMBER 2009
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Adjustable output voltage range, Selectable via I2C VIN_SMx = 2.9V to 5.5V
VO(SMx)
Output Voltage Accuracy, relative to VO(SMx)TYP
MIN
TYP
MAX
SM0, low range, 25mV
steps
VO(SMx)TYP = 0.725 to 1.50
SM1, high range, 50mV
steps
VO(SMx)TYP =1.45 to 3.0
SM2, high range, 50mV
steps
VO(SMx)TYP =3.0 to 4.55
VIN_SMx = 2.9V to 5.5V, PFM mode
–1%
VIN_SMx = 2.9V to 5.5V, PWM mode, 0mA < IOUT< 1A
–2%
DC output voltage load regulation
PWM mode, VIN_SMn>2.7V, Load<1A
DC output voltage line regulation
VIN_SMx = VOUT + 0.5V (min. 2.5V), PWM mode VIN_SMn>2.7V, Load<1A
1%
UNIT
V
3%
2%
0.25
%/A
0.1
%/V
SM0, SM1: typical
values:Instantaneous, 0.11,
0.22, 0.44, 0.88, 1.76, 3.52,
7.04
KRAMP(SMx)
Voltage change ramp constant
Value set via I2C, available options:
tStart
Start-up time
Time to start switching, measured from end of I2C command enabling
converter
210
μs
tRamp
VOUT Ramp UP time
Time to ramp from 5% to 95% of VOUT
250
μs
RDCH
Discharge switch resistance
SMx disabled
250
Ω
VIN_SM
x/
34Ω
A
VIN_SMx = 2.9V to 5.5V, duty cycle > 85%
mV/μs
IPFM(ENTER)
Load current to enter PFM mode
CLC
External LC capacitor (1)
4.7
22
μF
LLC
External LC inductor (1)
1.5
4.7
μH
CSMINP
External Input capacitor (1)
10
47
μF
Electrical characteristics over the output current range IO(LDOx)
2.3
5.5
Electrical characteristics specified , max load current = 75mA
1.7
5.5
LDO’S : LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9
Input voltage range (1)
VINMIN
IO(LDOx)
Output current
V
(1)
300
Output Voltage, Selectable via I2C. LDO6, LDO0, LDO3, LDO5,
LDO7,LDO8,LDO9
V(LDOx)
LDOx Output Voltage, Selectable via I2C
PSRR(LDOx) PSRR at 20 kHz
Available output voltages:
V(LDO6)TYP = 1.20 (LDO0
only), 1.25, 1.5, 1.8, 2.5, 2.7,
2.85, 3.1,3.3
LDO1 Output Voltage, Selectable via I2C
Low range, 25mV steps
V(LDO1)TYP = 0.725 to 1.5
LDO4 Output Voltage, Selectable via
High range, 25mV steps
V(LDO4)TYP = 1.7 to 2.475
LDO2 Output Voltage, Selectable via I2C
Low range, 25mV steps
V(LDO2)TYP= 0.725 to 1.5
Dropout, V(IN)= V(LDOx)TYP - 0.1V , V(IN)=2.3V, 250mA load. 1 LDO active at
a time per input pin group (2)
415
Total accuracy, V(VIN_LDOx)= V(LDOx)TYP + 0.5V, 10mA → 250 mA
See
(3)
3.5%
Line Regulation, 100mA load, V(VIN_LDOx):
V(LDOx) TYP + 0.5V→ 4.7V
–0.5%
0.5%
Load regulation, load change from 10mA → 250 mA
V(VIN_LDOx)> V(LDOx) TYP + 0.5V
See
(4)
mA
V
V
mV
%
250mA load, 1V input to output ,CL = 4.7 μF
40
100mA load, 0.5V input to output, CL = 1 μF
40
dB
ISC(LDOx)
Short circuit current limit
Output grounded
RDCH(LDOx)
Discharge resistor
LDOx disabled
LDOnILIM=HI
350
415
Ω
KRAMP(LDOx)
Voltage change ramp constant
LDO2, LDO4 only. Fixed value, hardwired at top level
7.04
mV/μs
CCOMP
External output capacitor value (1)
Stable operation
load <100 mA
load>100 mA
PGOOD(LDO)
(1)
(2)
(3)
(4)
10
Power good threshold
LDO output voltage increasing
Hysteresis
Decreasing voltage from increasing trigger
700
mA
μF
1
0.01μF/mA, min cap value =
1μF
95%
5%
Not production tested
Dropout not measured for devices with V(IN)<2.3V because minimum VIN is 2.3V
MIN = –3.2 – (0.105 × ILOAD / V(LDOX)TYP), ILOAD = load current in mA
MIN = –2.5 – (0.105 × ILOAD, ILOAD = load current in mA
ELECTRICAL SPECIFICATIONS
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SLVSA37 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY VOLTAGE THRESHOLDS AND CHARGER TIMING
TCHGDLY
Charger turn-off delay
Time delay to turn off charger or set suspend mode
25
Fast charge at V(BAT) > VLOWBAT
VLOWBAT
Precharge to fast-charge transition , selectable via
I2C
TDGL(PRE)
Deglitch time for fast charge to precharge transition Decreasing battery voltage
VRCH
Recharge threshold voltage
TDGL(RCH)
Deglitch time for battery recharge detection
ms
Selectable via I2C, 2.9V or
2.5V
Total accuracy, relative to selected value
–3%
3%
25
New charge cycle starts if
V(BAT) < VO(BATREG) – VRCH, after termination was detected
38
V
100
ms
170
65
mV
ms
PACK INSERTION AND PACK TEMPERATURE FAULT DETECTION , V(VTSBIAS)>2V
KTHOT
Pack hot temperature detection constant
Pack hot temp detected and charge suspended at V(TS) < V(2V2) × KTHOT
0.189
0.203
0.222
KTCOLD
Pack cold temperature detection constant
Pack cold temp detected and charge suspended at V(TS) > V(2V2) × KTCOLD
0.610
0.625
0.641
KNOPACK
Pack not detected threshold
V(TS) > V(2V2) × KNOPACK
0.935
0.95
0.965
TDGLTEMP
Pack temperature fault/no fault detection deglitch
15
ms
TDGL(DT)
Pack insertion detection deglitch
10
ms
TDLY(NDT)
Pack removal detection delay
RDSTSBIAS
Integrated switch resistance
Measured from VTSBIAS to V2V2
ITS(DET)
TS pin bias current
VTSBIAS to V2V2 switch open
μs
100
210
Ω
μA
–1
CHARGER INTEGRATED MOSFET CHARACTERISTICS
VBATDOCH
IDCH(BAT)
Battery Switch dropout voltage, charge
VBATDODCH = V(VIN_CHG) – V(BAT) , V(BAT) :3V, I(BAT) = –1A
BAT pin discharge current
ON at battery not detected and discharge switch enabled via I2C
(BATDCH=HI), V(BAT) > 1 V
100
5
200
mV
10
mA
V
CHARGER PROTECTION AND RECOVERY FUNCTIONS
VSH(VIN_CHG) VIN_CHG Short Circuit detection threshold
BATCHG switch set to OFF if
V(VIN_CHG) < VSH(VIN_CHG)
1.0
1.2
1.4
VSH(BAT)
BAT Short Circuit detection threshold
BATCHG switch set to OFF if V(BAT) < VSH(BAT)
1.6
1.8
2.0
RSH(BAT)
BAT short circuit recovery pull-up resistor
V(BAT) < VSH(BAT), Internal resistor connected between VIN_CHG and BAT2
TCHG
Charge safety timer
Safety timer value, thermal and DPPM loops not active or DTC function
disabled
Total accuracy
Pre charge timer range, thermal and DPPM
loops not active or DTC function disabled
1
Selectable via I2C: 4, 5,6,8
hours
–15%
25
30
35
TPCH=HI
50
60
70
Precharge timer
RTMR(FLT)
Timer fault recovery pull-up resistor
Internal resistor connected from VIN_CHG to BAT when timer fault is
detected
TSTRCHG
Charger thermal loop threshold
Charge current reduced for TJ > TSTRCHG
hours
15%
TPCH=LO
TPRECHG
V
kΩ
min
1
kΩ
125
°C
ELECTRICAL SPECIFICATIONS
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SLVSA37 – DECEMBER 2009
2.7
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.03
A
FAST CHARGE CURRENT , V(VIN_CHG) > V(BAT) + 0.2V , V(BAT) > VLOWBAT, t< TCHG
IO(BAT)
KSET
Charge current range
Charge current set factor
IO(BAT) = KSET/RISET DPPM/Thermal loops not active
RISET = 1 kΩ, scalable via I2C, (ISET_1, ISET_0)
=
0.1
11, 100% scaling
703
865
1020
10, 75% scaling
506
648
773
01, 50% scaling
325
432
530
00, 25% scaling
145
215
293
AΩ
PRE CHARGE CURRENT , V(VIN_CHG) > V(BAT) + 0.1V , VSH(BAT) < V(BAT) < VLOWBAT , t < TPRECHG
IO(PRECHG)
KPRECHG
Precharge current range
Precharge current set factor
IO(PRECHG) = KPRECHG/RISET DPPM/Thermal loops not active
0C<TJ<125°C RISET=I kΩ,scalable via I2C,
(IPCH_1, IPCH_0)=
10
00
13
01
10
11
170
43
71
48
85
110
80
126
159
85
166
200
mA
AΩ
CHARGE CURRENT REDUCTION - THERMAL, DPPM LOOPS ACTIVE (TJ > TSTRCHG, V(SYS) < VSYSDPPM )
KTHERMAL
Thermal loop factor
Charge Current (ICHG) = IO(BAT) × (1 – KTHERM × (TJ – TSTRCHG)/100)
10
%/°C
KDPPM
DPPM loop factor
Charge Current (ICHG ) = IO(BAT) × (1 – KDPPM × 10 × (VSYS(DPPM) – V(SYS)))
0.8
%/mV
CHARGE REGULATION VOLTAGE , V(VIN_CHG) > VO(BATREG) + 0.3V
VO(BATREG)
RSVD4B4=HI
4.3, 4.35, 4.4, 4.45
RSVD4B4=LO
4.1, 4.15, 4.2, 3.95
V
Voltage options, Selection via I2C
Battery charge voltage, selectable via
Accuracy, TA = 25°C, relative to selected value
I2C
Total Accuracy, relative to selected value
–0.55%
0.95%
–0.85
1.2
4.16
4.25
V
Total Accuracy range for selected value of 4.2 V
CHARGE TERMINATION, V(BAT) > VRCH, t < TTERM, VOLTAGE REGULATION MODE SET
ITERM
KTERM
Charge termination current range
Charge termination detection factor
ITERM = KTERM/RISET
10
2
40mA<ITERM</=170mA, scalable via I C,
(ITERM_1, ITERM_0)=
AC input selected
or USBMODE=HI
170mA
00
18
01
10
11
USB input selected,
(USBMODE=LO and
USBLIM=LO)(2)
TDGL(TERM)
Deglitch time, termination detection
170
40
50
42
82
112
70
140
188
85
165
208
18
40
50
I(BAT) < ITERM
25
mA
AΩ
ms
CHARGER DPPM LOOP AND SM2 CONTROL
VSYS(DPPM
SYS DPPM detection threshold ,
selectable via I2C
Charge current reduced for V(SYS)<VSYS(DPPM), VSYS(DPPM) set via I C,
(SYSDPPM_1, SYSDPPM_0) =
VSM2TRK
SM2 output voltage
Battery tracking enabled – V(BAT)+value
12
2
ELECTRICAL SPECIFICATIONS
00
3.413
3.5
3.588
01
3.656
3.75
3.844
10
3.9
4.0
4.1
11
4.144
4.25
4.356
0.17
0.265
0.37
V
V
Copyright © 2009, Texas Instruments Incorporated
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2.8
SLVSA37 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SM3 BOOST CONVERTER – CONTROL CIRCUIT AND POWER STAGE
VVIN(SM3)
Input Voltage range (1)
V(VIN)
VO(SM3)
Output voltage range (1)
V(SM3)
V(OVP3)
Output over-voltage trip
OVP detected at V(SM3) > V(OVP3)
VHYS(OVP3)
Output over-voltage hysteresis
OVP not detected at
V(SM3) < V(OVP3) – VHYS(OVP3)
V(SM3REF)
FB3 voltage sense threshold (1)
V(FB3) below regulation point at V(FB3) < V(SM3REF)
IO(SM3)
LED current (1)
IO(SM3) =
Current range,
2.5
6.5
V
VVIN(SM3)
26.5
V
29
V
26.5
28
1.8
V(SM3REF)
RFB3
V
238
248
258
1.237
1.25
1.263
0
25
mV
V
mA
Duty cycle range
D(SM3SW) = 0% to 99.96%, set via I2C,
2048 steps 0.05% minimum step
%
2048 pulses within repetition rate time, repetition rate set via
I2C
F(REP_SM3)TYP = 550Hz, 366Hz, 275Hz
or 220Hz
Hz
D(SM3SW)
LED switch duty cycle, selectable via I2C
F(REP_SM3)
LED switch duty cycle pattern repetition rate,
selectable via I2C
RDSON(SM3SW)
LED switch FET on-resistance (1)
ILKG(SM3SW)
LED switch FET leakage
RDSON(L3)
Power stage FET on-resistance
ILKG(L3)
Power stage FET leakage
IMAX(L3)
Power stage FET current limit
TSM3PWR(ON)
Maximum on time detection threshold
5
TSM3PWR(OFF)
Minimum off time detection threshold
310
1
Total accuracy, relative to F(REP_SM3)TYP
–12%
V(VIN)=3.8 V; I(SM3SW)=20 mA
V(VIN)=3.8 V; I(L3)=200 mA
2.5V< V(IN) <5.5V
400
12%
1
2
Ω
1
4
μA
300
600
mΩ
1
4
μA
500
600
mA
6
15
μs
400
480
ns
HIGH/LOW BRIGHTNESS CONTROL
RDSON(ISM3G)
Output buffer switch on resistance
V(VIN)=2.5V, I(ISM3G)=25mA
2
Ω
ILKG(ISM3G)
Leakage current
Hi-Z mode, V(ISM3G)=5V
1
μA
At nominal load
1
MHz
SWITCHING FREQUENCY
Maximum switching frequency (1)
FSM3
GPIO1-4 – DIGITAL OUTPUT BUFFER
IOL = 3 mA
0.6
IOL = 10 μA
0.1
VOL(GPIO)
Low level output voltage
VOH(GPIO)
High level output voltage GPIO
IOL(GPIO)
Maximum low level sink current
V(GPIOn)=2.5V
IOH(GPIO)
Maximum high level source current (1)
V(GPIOn)=0V
V
IOH = –3 mA
1.5
IOH = –10 μA
1.8
V
5
–5
mA
mA
GPIO1-4 – DIGITAL INPUT BUFFER
VIL(GPIO)
Low level input voltage
VIH(GPIO)
High level input voltage
ILKG(GPIO)
Input current
0.4
V
0.5
μA
3.5
μA
1.15
V
V(GPIOn)=5V or 0V, GPIO configured,
GPIO input current sink OFF
GPIO1-4 - INPUT CURRENT SINK
ISNK(GPIO)
(1)
Input current sink
ON if TPS658600 is not in sleep mode and GPIO is not
configured.
2.5
Not production tested
ELECTRICAL SPECIFICATIONS
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SLVSA37 – DECEMBER 2009
2.9
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM DRIVER, PWM OPEN DRAIN OUTPUT
IPWM
Maximum operating current (1)
PWM driver ON
200
mA
VOL
Low level output voltage
IOL = 100mA , V(AVDD6)=3V
0.2
V
F(PWM)
PWM driver frequency
Frequency range
Set via I2C F(PWM)TYP = 0.75, 1.5,
2.3, 3.0, 4.5, 6.7,11.7,23.4
D(PWM)
PWM driver duty cycle
Duty cycle range
D(PWM) = 6.25% to 100%, set via
I2C, 15 steps, 6.25% minimum step
ILKG(PWM)
Output off leakage current
Output voltage = 5V, driver set to OFF
kHz
%
5
μA
200
mA
1
LED_PWM DRIVER, LED_PWM OPEN DRAIN OUTPUT
Maximum operating current (1)
ILEDPWM
PWM driver ON
D(LEDPWM) = 0% to 99.6%, set via
I2C, 255 steps, 0.4% minimum step
Duty cycle range, 128Hz repetition rate
D(LEDPWM)
LED_PWM driver duty cycle
VOL(LEDPWM)
Low level output voltage
IOL = 50mA , V(AVDD6) = 3 V
ILKG(LEDPWM)
Output off leakage current
Output voltage = 5 V, driver set to OFF
Total accuracy, relative to selected value
–10%
%
10%
0.2
V
5
μA
1
RGB DRIVER, RED/GREEN/BLUE OPEN DRAIN OUTPUTS
TFLASH(RGB)
RGB1, RGB2 Flashing period
Flashing period range
TFLASH(ON)
RGB1, RGB2 Flash On Time
Flash on time range, value selectable by I2C
D(RGB)
RGB1, RGB2 Duty Cycle
Duty cycle range, value selectable via I2C
RGB1 output sink current
V(RED1) =
V(GREEN1) =
V(BLUE1) = 0.25V
Sink current, set via I2C
ISINK(RGB1)
RGB2 output sink current
V(RED2) = V(GREEN2)
= V(BLUE2) = 0.25V
s
Set via I2C, TFLASH(ON) = 0.1, 0.15,
0.2, 0.25, 0.3, 0.4, 0.5, 0.6
s
D(RGB) = 0% to 96.875%, set via
I2C, 3.125% minimum step
%
ISINK(RGB1)TYP = 0, 3.7, 7.4, 11.1
mA
Absolute accuracy relative to
selected value
–35%
35%
Relative accuracy between sink
current outputs
–10%
10%
ISINK(RGB at TYP = 0, 3.7, 7.4, 11.1,
14.9, 18.6, 23.2, 27.3,
Sink current, set via I2C
ISINK(RGB2)
TFLASH(RGB) = 1 to 8 sec, set via I2C,
0.5sec minimum step, 15 steps
mA
Absolute accuracy relative to
selected value
–35%
35%
Relative accuracy between sink
current outputs
–10%
10%
VLO(RGB1)
Low level output voltage
Output low voltage, RED1/GREEN1/BLUE1 pins, one current
source ON (4 or 8 or 12mA source) ON at a time,
V(AVDD6)=3V
0.25
V
VLO(RGB2)
Low level output voltage
Output low voltage, 16mA load, RED2/GREEN2/BLUE2 pins,
one current source ON (4 or 8 or 16mA source) ON at a time,
V(AVDD6)=3V
0.25
V
ILKG(RGB)
Output off leakage current
Output voltage = 5V, driver set to OFF
2
μA
140
Hz
1
DIG_PWM , DIG_PWM1 DRIVER , PUSH PULL OUTPUT
Frequency range
F(PWM)
PWM driver frequency
VHI(DIGPWM)
Output level, HI
VLO(DIGPWM)
Output level, LO
(1)
14
Total accuracy, relative to selected value
110
–10%
V(DIG_PWM) at I(DIG_PWM) = –5 mA
1.7
V(DIG_PWM) at I(DIG_PWM) = –10 μA
2.0
125
10%
V
V(DIG_PWM) at I(DIG_PWM) = 5 mA
0.5
V(DIG_PWM) at I(DIG_PWM) = –10 μA
0.1
V
Not production tested
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2.10
SLVSA37 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC REFERENCE
VREF(ADC)
Internal ADC reference voltage
ISHRT(ADCREF)
Internal reference short circuit limit
CREFADC
Maximum capacitance for internal ADC reference
supply (1)
TA = 25°C
2.595
2.6
2.605
Over full temp range
2.577
2.595
2.607
3.0
4.5
V
V(ADC_REF)=AGND1
mA
6.8
μF
ADC ANALOG INPUTS
VRNG(CH1_6)
Full scale input range Channels 1–6 (1)
Positive inputs, Full scale ~ 2.60 V
0
VREF(ADC)
V
VRNG(CH7_10)
Full scale input range Channels 7, 10 (1)
Positive inputs, Full scale ~ 4.622 V
0
VREF(ADC) × 1.78
V
VRNG(CH8_9)
Full scale input range Channels 8, 9 (1)
Positive inputs , Full scale ~ 5.54 V
0
VREF(ADC) × 2.13
CIN(ADC)
Input capacitance (all channels)
RINADC(CH1_6)
Input resistance (all channels)
AVDD6-V(ANLG) >= 500mV
ILKGADC(CH1_6)
Leakage current (all channels)
ADC disabled
15
V
pF
1
MΩ
0.1
1
μA
ADC – DC ACCURACY
RES(ADC)
Resolution
MCD(ADC)
Missing codes
INL(ADC)
Integral Linearity Error
±3
LSB
DNL(ADC)
Differential non-linearity error
±1
LSB
OFFZERO(ADC)
Offset error
OFFCH(ADC)
Offset error match between channels (1)
SAR ADC
10
None
Deviation from the first code transition (00..00) to
(00.001) fro m the ideal AGND + 1LSB
GAIN(ADC)
Gain error
Deviation in code from the ideal full scale code
(11…111) for the full scale voltage
GAINCH(ADC)
Gain error match
Any two channels
None
Bits
None
1
5
LSB
1
5
LSB
±8
LSB
2
LSB
ADC THROUGHPUT SPEED
ADCCLK
ADCTCONV
Sampling Clock (1)
506
562
619
kHz
Sampling time - 9X ADCCLK
16
μs
conversion and settling time -11X ADCCLK
20
μs
Sampling and conversion time
ANLGx (USER_DEFINED INPUTS) BIAS CURRENTS
00 =
I(ANLGx)
ADC channel 1 bias current, set via I2C
register ADC_WAIT bits (ADICH2_1,
ANLG1, 2, or 3 pin internal pull-up current source ADICH2_2)
0
01 =
3
10 =
10
11 =
Total Accuracy
(1)
μA
50
–20%
20%
Not production tested
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2.11 PIN DESCRIPTION, REQUIRED EXTERNAL COMPONENTS
2.11.1 Package Pinout (Top View)
PIN FUNCTIONS
NAME
PIN
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
I/O
DESCRIPTION
A11, B11
I
Adapter Charge Input Voltage, connect to AC_DC
adapter positive output terminal (DC voltage)
1uF(minimum) capacitor to AGND1 pin to minimize over-voltage
transients during AC power hot-plug events.
USB
C10,
C11
I
USB charge input voltage, connect to USB port
positive power output
1μF(minimum) capacitor to AGND1 pin, to minimize over-voltage
transients during USB power hot-plug events.
BAT
D11, E11
I/O
Battery power
Connect to battery positive terminal. Connect 4.7μF capacitor
(minimum) from BAT2 pin to clean analog ground plane
SYS
A10, B10
O
AC/BAT/USB Power path output. Connect to
System main power rail (system power bus)
10μF capacitor to AGND1 pin
SYSTEM POWER PATH
AC
REFERENCE SYSTEM
TNOPOWER
D4
I
NOPOWER pin pulse width
Capacitor to AGND1. Capacitor value sets pulse width
AVDD6
H11
O
Internal supply rail
Connect 4.7μF capacitor to AGND1
V2V2
G10
O
Internal 2.2V supply rail
1μF (minimum) decoupling capacitor to AGND1
16
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SLVSA37 – DECEMBER 2009
PIN FUNCTIONS (continued)
NAME
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
PIN
I/O
G11
O
Internal 1.25V reference filter capacitor
100nF (minimum) decoupling cap to AGND1
TS
E9
I/O
Temperature Sense Input, current source output
Connect to battery pack thermistor to sense battery pack temperature
ISET
F9
I
Current set point when charging with AC selected. External resistor from ISET pin to AGND1 pin sets charge current
value
VTSBIAS
H8
O
Thermistor network bias supply, internally
connected to 2V2 via integrated switch
Connect to external thermistor pull-up resistor
VIN_CHG
F10, F11
I/O
Charger supply.
Connect to SM2 converter output or SYS pin, see charger section
K2
O
Charger Status
Push-pull output, 2V2 level
D10
I
DPPM loop filter capacitor
Not used, pin should be left open
1V25
DESCRIPTION
CHARGER
CHG_STAT
FLTDPPM
SM3 BOOST CONVERTER
L3
K11
O
Drain of the integrated boost power stage switch
4.7μH inductor to SYS pin, external Schottky diode to SM3 pin
FB3
G9
I
White LED duty cycle switch output, LED current
setting
External resistor from FB3 pin to PGND3 pin sets LED peak current.
Connect 100pF (minimum) filter capacitor to PGND3 pin.
Integrated White LED duty cycle switch input
SM3_SW
H9
I
SM3IG
H10
I/O
SM3
J10
PGND3
General purpose input/output
HI-Z Output, controlled via I2C. May be used to set SM3 current gain
step, implementing a high/low brightness control
I
White LED driver output over-voltage detection
Connect 1μF capacitor to PGND3 pin. Connect SM3 pin to the
positive side of white LED ladder.
J11
I
Power ground, SM3 converter
Connect to the power ground plane
RED2
K8
O
L8
O
Programmable LED driver, open drain output,
current sink output when active.
Connect to RED input of RGB LED
GREEN2
BLUE2
G7
O
Connect to BLUE input of RGB LED
RED1
K9
O
Connect to RED input of RGB LED
GREEN1
L9
O
Connect to GREEN input of RGB LED
BLUE1
J8
O
L10
O
LED_PWM driver output, open drain,
programmable duty cycle.
Can be used to drive a keyboard backlight LED or other external
functions
DRIVERS
LED_PWM
PWM
Connect to GREEN input of RGB LED
Connect to BLUE input of RGB LED
J9
I
PWM DRIVER, open drain output
May be used to control external vibrator motor
DIG_PWM
L11
O
PWM, digital push-pull output
2V2 output voltage level
DIG_PWM2
G3
O
PWM, digital push-pull output
2V2 output voltage level
B1, B2
I
SM0 synchronous buck converter positive supply
input
2 x 10μF capacitor to PGND0 pin
A2
I
SM0 synchronous buck converter output voltage
sense
LC filter: 1.5μH Inductor and 10μF Capacitor. Connect capacitor to
PGND0 pin
C1, C2
O
SM0 synchronous buck converter power stage
output
1.5μH inductor to SM0 pin
PGND0
D1, D2
I
Power ground, SM0 converter
Connect to the power ground plane
VIN_SM1
G1, G2
I
SM1 synchronous buck converter positive supply
input
2 x 10μF capacitor to PGND1 pin
B4
I
SM1 synchronous buck converter output voltage
sense
LC filter: 1.5μH Inductor and 10μF Capacitor. Connect capacitor to
PGND1 pin
L1
F1, F2
O
SM1 synchronous buck converter power stage
output
1.5μH inductor to SM1 pin
PGND1
E1, E2
I
Power ground, SM1 converter
Connect to the power ground plane
VIN_SM2
A9, B9
I
SM2 synchronous buck converter positive supply
input
2 x 10μF capacitor to PGND2 pin
C9
I
SM2 synchronous buck converter output voltage
sense
LC filter: 1.5μH Inductor, 10μF Capacitor. Connect capacitor to
PGND2 pin
L2
A8, B8
O
SM2 synchronous buck converter power stage
output
1.5μH inductor to SM2 pin
PGND2
A7, B7
I
Power ground pin, SM2 converter
Connect to power ground plane
DC/DC CONVERTERS
VIN_SM0
SM0
L0
SM1
SM2
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PIN FUNCTIONS (continued)
NAME
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
PIN
I/O
DESCRIPTION
AGND2
J3
I
Analog ground, ADC subsystem
Connect to analog ground plane
ANLG1
H5
I
Can be used to monitor additional system or pack parameters
ANLG2
L2
I
Analog input1 to ADC, programmable current
source output
ANLG3
K3
I
ADC_REF
L1
I/O
ADC internal reference filter or ADC external
reference input
Connect a maximum capacitance of 6.8uF referenced to the AGND2
pin.
ADC
EXTERNAL SYSTEM RESET AND CLOCK OUTPUTS, ADJUSTABLE LEVEL
V32K
B6
I
Power supply for host interface buffers
INT
K10
O
Interruption pin nINT pin is LO when interrupt is
requested by TPS658XX.
Open drain output
OUT32K
C6
O
32kHz clock from external XTAL
Push-pull output, V32K level
NOPOWER
G8
O
Host reset output, LO level, adjustable width
NORTC
D3
O
RTC_OUT POR pulse, LO level, fixed width
SEQUENCING CONTROL INPUTS
HOT_RST
B3
I/O
Reboot cycle request
Hardware reboot cycle control
RESUME
A1
I
Sleep on/off request
Hardware sleep on/off control
LDO4EN
E4
I
LDO4 enable control
SM0EN
(CORECTRL)
D9
I
Supply enable control
SM1EN
C8
I
Supply enable control
SYNCEN
C7
I
Supply enable control
G5
I/O
Active low signal.
I2C INTERFACE
PSDAT
Power I2C clock line
Connect to external host power I2C clock. Connect 2K external
pull-up resistor. Connect to 2V2 pin if not used
Connect 2K external pull-up resistor.
PSCLK
J2
I
SDAT
H3
I/O
I2C interface data line
SCLK
G4
I
I2C interface clock line
XTAL1
L5
I
Xtal oscillator
Connect to external xtal
XTAL2
K6
I
GPIO1
L3
I/O
General purpose input/output
Input: SM0, SM1, SM2 power saving mode and output voltage setting
control
GPIO2
K4
I/O
General purpose input/output
Input: ADC external trigger or LDO0, LDO1 enable
GPIO3
J5
I/O
GPIO4
L4
I/O
COMP
J4
I
General purpose comparator input, ADC input
SM0PG
A3
O
SM0 power good status
SM1PG
C4
O
SM1 power good status
LDO4PG
H4
O
LDO4 power good status
RTC OSCILLATOR
INPUT / OUTPUT
Input: LDO2, LDO3 enable
Input: ADC external trigger or LDO6, LDO7, LDO8 enable
LINEAR REGULATORS
VIN_LDO01
J6
I
Positive supply input for LDO0, LDO1
1μF (minimum) decoupling capacitor to AGND1
LDO0
K5
O
LDO0 output
1μF(minimum) capacitor to AGND1
LDO1
L6
O
LDO1 output
1μF(minimum) capacitor to AGND1
VIN_LDO23
A5
I
Positive supply input for LDO2, LDO3
1μF (minimum) decoupling capacitor to AGND1
LDO2
A6
O
LDO2 output
1μF(minimum) capacitor to AGND1
LDO3
B5
O
LDO3 output
1μF(minimum) capacitor to AGND1
VIN_LDO4
H7
I
Positive supply input for LDO4
1μF (minimum) decoupling capacitor to AGND1
LDO4
K7
O
LDO4 output
1μF(minimum) capacitor to AGND1
LDO5
D7
O
LDO5output
1μF(minimum) capacitor to AGND1
VIN_LDO678
H1
I
Positive supply input for LDO0, LDO1
1μF (minimum) decoupling capacitor to AGND1
18
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SLVSA37 – DECEMBER 2009
PIN FUNCTIONS (continued)
NAME
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
PIN
I/O
LDO6
H2
O
LDO6 output
1μF(minimum) capacitor to AGND1
LDO7
K1
O
LDO7 output
1μF(minimum) capacitor to AGND1
LDO8
J1
O
LDO8 output
1μF(minimum) capacitor to AGND1
VIN_LDO9
J7
I
Positive supply input for LDO9
1μF (minimum) decoupling capacitor to AGND1
LDO9
L7
O
LDO9 output
1μF(minimum) capacitor to AGND1
E10
O
Low leakage LDO output. Can be connected to a
super-capacitor or secondary cell, if used as a
RTC backup output.
1μF (minimum) capacitor to AGND1 pin or supercap
RTC_OUT
DESCRIPTION
ANALOG AND DIGITAL GROUND PINS
DGND1
H6
I
Digital ground pin
Connect to digital ground plane
AGND1
F8
I
Analog ground pin
Connect to analog ground plane
AGND3
A4
I
Analog ground pin
Connect to analog ground plane
DGND2DT
C5
I/O
Digital ground pin
Connect to analog ground plane
See
Package
Drawing
N/A
There is an internal electrical connection between all HSK pins of the IC. The HSK pins must be connected to the same
potential as the AGND1 pin on the printed circuit board. Do not use the HSK pins as the primary ground input for the
IC.
HSK
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RED1
DIGPWM2
GREEN2
RED2
BLUE1
GREEN1
LED_PWM
PWM
DIGPWM
BLUE2
VIN_CHG
ISET
TS
VTSBIAS
FLTDPPM
SYS
TNOPOWER
AVDD6
2V2
1V25
2.11.2 Block Diagram
TPS6586x
PROCESSOR
POWER PATH, OVP
AND INPUT
CURRENT LIMIT,
REFSYS
LINEAR
CHARGER
DRIVERS
AC
USB
BAT
VINLDO9
VINLDO678
LDO6
LDO6
1.25-3.3V
LDO7
LDO7
1.25-3.3V
LDO8
LDO8
1.25-3.3V
LDO9
1.25-3.3V
SM3IG
L3
FB3
PGND3
SYS
SYS
LDO5
1.25-3.3V
LDO5
0.725 - 1.5V
31x25mv steps,
1.45 - 3.0V,
31x50mV steps
Peak Eff : 0.4A
1.2A max
LDO4
1.7-2.475V,
1.7-2.0V,
31X25mV steps,
VINLDO4
LDO4
VINLDO23
LDO2
LDO2
0.725-1.5V ,
31x25mV steps,
1.25V-2.586V,
31x43mV steps
LDO3
LDO3
1.25-3.3V
SM3
SM3_SW
WHITE LED
DRIVER
RTC_OUT LDO
1.25-3.3V
RTC_OUT
LDO9
CONTROL
LOGIC
VIN_SM0
L0
SM0
PGND0
0.725 - 1.5V
31x25mv steps,
1.45 - 3.0V,
31x50mV steps
Peak Eff : 0.4A
1.2A max
VIN_SM1
L1
SM1
PGND1
1.7 - 2.475V
31x25mv steps
3.0 - 4.55V
31x50mV steps,
VBAT+0.265v,
Peak Eff : 0.4A
1.6A max
L2
SM2
PGND2
10 CHANNEL
MUX
ANLG1
ANLG2
ANLG3
COMP
VIN_SM2
6 INTERNAL
CHANNELS
VINLDO01
LDO0
1.25-3.3V
LDO0
LDO1
0.725 -1.5V
31x25mV steps,
1.25 - 2.586V,
31X43mV steps
LDO1
A/D
!CONVERTER
ADC_REF
AGND2
RTC_OUT
COMP
AGND1
AGND3
20
ELECTRICAL SPECIFICATIONS
XTAL2
XTAL1
LDO4PG
RTC
SM0PG
SM1PG
GPIO1
GPIO2
GPIO3
GPIO4
I/O
V32K
RESUME
LDO4EN
CHG_STAT
NORTC
NOPOWER
32KOUT
SYNCEN
SM0EN
SM1EN
SEQUENCING AND RESET
CONTROLLER
HOTRST
PSDAT
PSCLK
INT
SDAT
SCLK
DGND1
DGND2DT
HOST INTERFACE AND SEQUENCING
I2C INTERFACE
AND INTERRUPT
CONTROLLER
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SLVSA37 – DECEMBER 2009
2.12 TYPICAL CHARACTERISTICS
LDO9 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO9 Vout vs. Iout (Temp. = 25°C) 3.30V
3.40
1.28
1.27
3.35
1.26
3.30
V out [V ]
Vout [V]
1.25
1.24
1.23
1.22
3.20
Vin=2.3v, Ta=25C
1.20
0.10
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=3.9v, Ta=25C
1.21
3.25
3.15
Vin=5.5v, Ta=25C
3.10
0.10
1.00
Vin=5.5v, Ta=25C
1.00
10.00
Iout [ma]
Figure 2-1.
100.00
1000.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-2.
LDO0 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO0 Vout vs. Iout (Temp. = 25°C) 3.30V
1.28
3.40
1.27
3.35
1.26
3.30
Vout [V]
Vout [V]
1.25
1.24
1.23
Vin=2.3v, Ta=25C
3.25
Vin=Vout + 0.5, Ta=25C
3.20
Vin=3.9v, Ta=25C
1.22
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
Vin=5.5v, Ta=25C
3.15
1.21
1.20
0.10
3.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-3.
Figure 2-4.
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(continued)
LDO1 Vout vs. Iout (Temp. = 25°C) Low Range
LDO1 Vout vs. Iout (Temp. = 25°C) High Range
0.75
2.64
0.73
2.62
0.72
2.60
Vout [V]
Vout [V]
0.74
0.71
0.70
2.58
Vin=Vout+0.5, Ta=25C
2.56
Vin=3.9v, Ta=25C
0.69
Vin=2.3v, Ta=25C
0.68
Vin=3.9v, Ta=25C
0.67
Vin=5.5v, Ta=25C
0.66
0.10
Vin=5.5v, Ta=25C
2.54
2.52
2.50
1.00
10.00
100.00
1000.00
0.10
1.00
Iout [ma]
10.00
100.00
1000.00
Iout [ma]
Figure 2-5.
Figure 2-6.
LDO2 Vout vs. Iout (Temp. = 25°C) Low Range
LDO2 Vout vs. Iout (Temp. = 25°C) High Range
0.75
2.65
0.74
2.63
0.73
0.71
Vout [V]
Vout [V]
0.72
0.70
0.69
0.68
2.61
2.59
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C]
Vin=Vout+0.5v, Ta=25C
Vin=5.5, Ta=25C
2.57
0.67
Vin=5.5v, Ta=25C
0.66
0.10
2.55
1.00
10.00
100.00
1000.00
0.10
Iout [ma]
1.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-8.
Figure 2-7.
22
Vin=3.9v, Ta=25C
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(continued)
LDO3 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO3 Vout vs. Iout (Temp. = 25°C) 3.30V
3.40
1.28
1.27
3.35
1.26
3.30
V out [V ]
Vout [V]
1.25
1.24
1.23
1.22
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
3.25
3.20
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
3.15
Vin=5.5v, Ta=25C
1.21
1.20
0.10
3.10
1.00
10.00
Iout [ma]
Figure 2-9.
100.00
0.10
1000.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-10.
LDO4 Vout vs. Iout (Temp. = 25°C) 2.475V
LDO4 Vout vs. Iout (Temp. = 25°C) 1.700V
1.74
2.54
2.52
1.73
2.50
Vout [V]
Vout [V]
1.00
1.72
2.48
Vin=Vout + 0.5, Ta=25C
Vin=2.3v, Ta=25C
1.71
Vin=4.65v, Ta=25C
Vin=3.9v, Ta=25C
2.46
Vin=5.5v, Ta=25C
1.70
0.10
1.00
10.00
Iout [ma]
100.00
1000.00
2.44
0.10
Vin=5.5v, Ta=25C
1.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-12.
Figure 2-11.
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(continued)
LDO5 Vout vs. Iout (Temp. = 25°C) 3.30V
LDO5 Vout vs. Iout (Temp. = 25°C) 1.250V
3.40
1.28
1.27
3.35
1.26
3.30
Vo u t [V]
Vout [V]
1.25
1.24
1.23
3.25
3.20
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
1.22
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
3.15
Vin=5.5v, Ta=25C
1.21
1.20
0.10
3.10
1.00
10.00
Iout [ma]
100.00
0.10
1000.00
1.00
Figure 2-13.
10.00
Iout [ma]
100.00
1000.00
Figure 2-14.
LDO6 Vout vs. Iout (Temp. = 25°C) 3.30V
LDO6 Vout vs. Iout (Temp. = 25°C) 1.250V
1.28
3.40
1.27
3.35
1.26
3.30
Vout [V]
Vout [V]
1.25
1.24
1.23
1.22
Vin=2.3v, Ta=25C
3.25
3.20
Vin=3.9v, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
3.15
1.21
1.20
0.10
Vin=5.5v, Ta=25C
3.10
1.00
10.00
100.00
1000.00
0.10
Iout [ma]
Figure 2-15.
24
Vin=Vout + 0.5, Ta=25C
1.00
10.00
Iout [ma]
100.00
1000.00
Figure 2-16.
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(continued)
LDO7 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO7 Vout vs. Iout (Temp. = 25°C) 3.30V
1.28
3.40
1.27
3.35
3.30
1.25
Vout [V]
Vout [V]
1.26
1.24
1.23
Vin=4.65v, Ta=25C
3.20
Vin=5.5v, Ta=25C
Vin=5.5v, Ta=25C
3.15
1.21
1.20
0.10
Vin=Vout + 0.5, Ta=25C
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
1.22
3.25
1.00
10.00
Iout [ma]
100.00
3.10
0.10
1000.00
1.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-18.
Figure 2-17.
LDO8 Vout vs. Iout (Temp. = 25°C) 3.30V
LDO8 Vout vs. Iout (Temp. = 25°C) 1.250V
1.28
3.40
1.27
3.35
1.26
3.30
Vout [V]
Vout [V]
1.25
1.24
1.23
1.22
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
3.25
3.20
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
3.15
Vin=5.5v, Ta=25C
1.21
1.20
0.10
1.00
10.00
Iout [ma]
Figure 2-19.
100.00
1000.00
3.10
0.10
1.00
10.00
Iout [ma]
Figure 2-20.
100.00
1000.00
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(continued)
LDO2 0.725V DropOut at 25°C
LDO0 1.25V DropOut at 25°C
1.40
0.80
1.30
0.78
1.20
0.76
1.10
0.74
1.00
0.80
Vout [V]
0.70
0.70
0.60
0.68
Temp = 25°C
Iout = 1mA
Temp = 25°C
Iout = 100mA
Temp = 25°C
Iout =250mA
Temp. = 25°C
Iout = 1mA
Temp. = 25°C
Iout = 100mA
Temp. = 25°C
Iout = 250mA
0.66
0.64
0.62
2.20
.
2.00
.
1.80
.
1.60
.
1.40
1.20
.
Vout [V]
0.90
0.72
0.50
0.40
0.30
0.20
0.10
0.60
1.00
0.00
2.30 2.20 2.10 2.00 1.90 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00
Vin [V]
Figure 2-22.
Vin [V]
Figure 2-21.
Efficiency SM0 Auto PFM Vout 1.8V at 25°C
LDO0 3.3V DropOut at 25°C
3.50
100
3.40
90
3.30
3.20
80
3.10
70
2.80
2.70
2.60
2.50
Temp. = 25°C
Iout = 1mA
Temp. = 25°C
Iout = 100mA
Temp. = 25°C
Iout = 250mA
Vout [V]
2.90
Efficiency [%]
3.00
60
50
40
30
2.40
2.30
20
2.20
10
2.6
2.8
3.1
3.4
3.6
3.9
4.2
4.4
4.7
4.9
5.2
5.5
5.7
6.0
2.10
2.00
3.80 3.70 3.60 3.50 3.40 3.30 3.20 3.10 3.00 2.90 2.80 2.70 2.60 2.50
Vin [V]
0
0.0001
Figure 2-23.
26
2.3
0.001
0.01
0.1
1.0
10.0
Iout [A]
Figure 2-24.
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(continued)
Efficiency SM0 PWM Vout 1.8V at 25°C
Efficiency SM1 Auto PFM Vout 1.25V at 25°C
100
80
Efficiency [%]
70
60
2.6
2.8
3.1
3.4
3.6
3.9
4.2
4.4
4.7
4.9
5.2
5.5
5.7
90
80
70
Efficiency [%]
90
100
2.3
6.0
50
40
60
50
40
30
30
20
20
10
10
0
0.00010
0.00100
0.10000
0.01000
Iout [A]
1.00000
0
0.00010
10.00000
3.1
3.4
3.6
3.9
4.2
4.4
4.9
4.7
5.2
5.5
5.7
0.00100
0.01000
0.10000
Iout [A]
1.00000
10.00000
Figure 2-26.
Efficiency SM2 Auto PFM Vout 3.25V at 25°C
Efficiency SM1 PWM Vout 1.250V at 25°C
100
100
2.3
2.6
2.8
3.4
3.1
3.6
90
80
3.9
4.2
80
70
4.4
4.9
4.7
5.2
70
5.7
60
5.5
6.0
Efficiency [%]
Efficiency [%]
2.6
2.8
6.0
Figure 2-25.
90
2.3
50
40
60
50
40
30
30
20
3.0
3.2
3.4
3.6
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.4
5.6
5.8
20
6.0
10
0
0.0001
10
0.001
0.01
0.1
Iout [A]
1.0
10.0
0
0.001
Figure 2-27.
0.01
0.10
Iout [A]
Figure 2-28.
1.0
10.0
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(continued)
Efficiency SM2 PWM Vout 3.25V at 25°C
100
90
80
Efficiency [%]
70
60
50
40
30
20
28
3.2
3.4
3.6
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.4
5.6
5.8
6.0
10
0
0.0001
3.0
0.001
0.01
0.1
Iout [A]
Figure 2-29.
1.0
ELECTRICAL SPECIFICATIONS
10.0
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3 DETAILED DESCRIPTION
3.1
I2C INTERFACE
Two I2C configurations are implemented in the TPS658600 device:
A –Standard I2C interface (SDAT/SCLK engine) : A single I2C communication port provides a simple
way for an I2C compatible host to access system status information, reset fault modes, and set supply
output voltages. The I2C port functions as a SLAVE enabling I2C compatible hosts (MASTER) to perform
WRITES and READS to/from internal registers. The I2C port is a 2-wire bidirectional interface using the
SCLK (clock) and SDAT (data) pins. The I2C is designed to operate at SCLK frequencies up to 400 kHz.
The standard 8 bit command is supported. The CMD part of the sequence is the 8 bit register address to
read or write.
B – Power I2C interface (PSDAT/PSCLK engine): The TPS658600 supports processors that use a
dedicated I2C bus to dynamically adjust critical supply voltages by adding a second I2C bus (Power I2C)
connected to a second, dedicated I2C engine. The Power I2C port is a 2-wire bidirectional interface using
the PSCLK (clock) and PSDAT (data) pins. The Power I2C is designed to operate at PSCLK frequencies
up to 400 kHz. A multiple-byte data-register pair command protocol, not compatible with the standard I2C
protocol, is supported by the Power I2C engine. The Power I2C engine does not support read operations.
NOTE
The Standard and Power I2C engines are always reset by the sequencer when the
TPS658600 is in the POWER-UP state and when the SLEEP state is set.
3.2
I2C ADDRESS
The TPS658600 will acknowledge (ACK) addresses 0x68 (writes) and 0x69 (reads) and will NACK any
other address.
3.3
DVM REGISTER ACCESS
The sequencer state machine disables write access to specific supply voltage setting registers when the
TPS658600 is initially powered and when the integrated supplies are being sequenced. See the
sequencer functional description for details.
3.4
SCLK/SDAT AND PSCLK/PSDAT TIMEOUT
The TPS658600 monitors the SCLK/PSCLK clock lines, and it identifies a timeout condition if the clock
line is held at a logic low for longer than 30ms. The I2C engine is NOT reset when the clock line timeout is
identified.
The TPS658600 monitors the SDAT/PSDAT data lines. The I2C engine will be reset when the data line is
held at a logic low for more than 30ms.
3.5
I2C BUS RELEASE
The TPS658600 I2C engine does not create START or STOP states on the I2C bus during normal
operation.
3.6
I2C BUS ERROR RECOVERY
The I2C bus specification does not define a method to be used when recovering from a host side bus
error. During a read operation the SDAT pin can be left in a LO state if the host has not sent enough
SCLK pulses to complete a transaction (i.e. host side bus error). The TPS658600 will clear any SDAT LO
condition if 10 SCLK pulses are sent by the host, enabling recovery from host side bus error events.
DETAILED DESCRIPTION
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I2C COMMUNICATION PROTOCOL
The following conventions will be used when describing the communication protocol:
CONDITION
START sent from host
CODE
S
STOP sent from host
P
TPS658600 I2C slave address sent from host (WRITE)
hA0
TPS658600 register address sent from TPS658600 (READ)
hA1
2
Non-valid I C slave address sent from host
hA_N
Valid TPS658600 register address sent from host
HCMD
Non-valid TPS658600 register address sent from host
HCMD_N
I/O data byte (8 bits) sent from host to TPS658600
hDATA
I/O data byte (8 bits) sent from TPS658600 to host
bqDATA
Acknowledge (ACK) from host
hA
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from TPS658600
bqA
Not acknowledge (NACK) from TPS658600
bqN
Figure 3-1. I2C Conditions
For normal data transfers, the data line (SDAT or PSDAT) is allowed to change only when the clock line
(SCLK or PSCLK) is low, and one clock pulse is used per bit of data. The data line must remain stable
whenever the clock line is high, as data changes when the clock is high are reserved for indicating the
start and stop conditions. Each data transfer is initiated with a start condition and terminated with a stop
condition.
When addressed, the TPS658600 device generates an acknowledge bit after the reception of each byte
by pulling the data line Low. The master device (microprocessor) must generate an extra clock pulse that
is associated with the acknowledge bit. After the acknowledge/not acknowledge bit, the TPS658600
leaves the data line high, enabling a STOP condition generation.
3.8
I2C READ AND WRITE OPERATIONS
The TPS658600 supports the standard I2C one byte Write. The basic I2C read protocol has the following
steps:
1. Host sends a start and sends TPS658600 address
30
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2.
3.
4.
5.
6.
7.
SLVSA37 – DECEMBER 2009
TPS658600 ACK’s that this is a valid I2C address and that the bus is configured for write
Host sends TPS658600 register address
TPS658600 ACK’s that this is a valid register and stores the register address to be read
Host sends a repeated start and TPS658600 I2C slave address, reconfiguring the bus for read
TPS658600 ACK’s that this is a valid address and that bus is reconfigured
Bus is in read mode, TPS658600 starts sending data from selected register
The I2C write protocol is similar to the read, without the need for a repeated start and bus being set in
write mode. In a WRITE, it is not necessary to end each 1 byte WRITE command with a STOP as a
START will have the same effect (repeated start).
The host can complete a READ or a WRITE sequence with either a STOP or a START.
NOTE
Read operations are not supported for the PSDAT/PSCLK I2C engine.
Figure 3-2. I2C Read/Write Example
3.9
VALID WRITE SEQUENCES (SDAT/SCLK, PSDAT/PSCLK)
The TPS658600 will always ACK its own address. If CMD points to an allowable READ or WRITE
address, the device writes the address into its RAM address register and sends an ACK. If CMD points to
a non-allowed address, the device does NOT write the address into its RAM address register and sends a
NACK.
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S
hA0
www.ti.com
bqA
S
hA0
bqA
hCMD
bqA
S
hA0
bqA
hCMD_N
bqN
3.10 ONE BYTE WRITE (SDAT/SCLK, PSDAT/PSCLK)
The data is written to the addressed register at the end of the bq ACK, ending the one byte write
sequence when the RAM address and the data byte are stored in the I2C registers. The host can cancel a
WRITE by sending a STOP or START before the trailing edge of the ACK clock pulse.
S
hA0
bqA
hCMD
bqA
hDATA
bqA
3.11 VALID READ SEQUENCES (SDAT/SCLK ONLY)
The TPS658600 will always ACK its own address.
S
hA1
bqA
Upon receiving hA1, TPS658600 starts at the current location of the RAM address register. The START
and the STOP both act as priority interrupts. If the host has been interrupted and is not sure where it left
off, it can send a STOP and reset the TPS658600 state machine to the WAIT state; once in the WAIT
state, the TPS658600 will ignore all activity on the SCLK and SDAT lines until it receives a START. A
repeated START and START in the I2C specification are both treated as a START.
S
S
hA0
hA0
bqA
bqA
hCMD
hCMD
bqA
S
hA1
bqA
bqA
bqDATA
P
hN
P
3.12 VALID READ SEQUENCES (SDAT/SCLK ONLY)
S
hA1
bqA
bqDATA
hN
P
Incremental read sequences
S
hA1
bqA
bqData
hA
bqDATA
hA
...
bqDATA
hN
P
3.13 NON-VALID SEQUENCES
START and non-hA0 or non-hA1 Address: A START followed by an address which is not hA0 or hA1 will
be NACKED.
S
hA_1
bqN
Attempt to Specify Non-Allowed READ Address
If the CMD points to a non-allowed READ address (reserved registers), bq will send a NACK back to the
host and it will not load the address in the RAM address register. Note that the TPS658600 NACKS
whether a stop is sent or not.
S
32
hA0
bqA
hCMD_N
bqA
P
S
DETAILED DESCRIPTION
hA0
bqA
hCMD_N
bqN
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Attempt to Specify Non-Allowed WRITE Address
If the host attempts to WRITE to a READ-ONLY or non-accessible address, the TPS658600 ACKS the
CMD containing the allowed READ address, loads the address into the address register and ACKS after
the host sends the next data byte. A subsequent hA1 READ could read this address, but the data sent by
the host will not have been written.
S
hA0
bqA
hCMD
bqA
hDATA
bqA
3.14 INCREMENTAL READ (SDAT/SCLK ONLY)
The SDAT/SCLK I2C interface supports incremental read operations. Each register must be accessed in a
single read operation. A valid WRITE address is required to write to the RAM, and a valid READ address
is required to specify the initial RAM address where the READ starts. Once a read command is received,
the RAM data for the specified address is output to the host. If the host chooses, it can loop through the
remaining addresses; the address is automatically incremented by one at the end of each read. If the loop
gets to the top address, it automatically rolls over to address 0x00 and the sequence stops.
3.15 I2C COMMUNICATION PROTOCOL – POWER I2C INTERFACE, PINS PSDAT/PSCLK
The Power I2C interface is designed to support fast write operations using multiple register-data pair
sequences. The Power I2C engine is a write-only engine, and it does not support read operations.
During a write sequence, the host sends the start command, followed by the TPS658600 address. Then
the host sends the register address byte, followed by eight bits of the data for the respective register
(Register1 Address/Data in Figure 3-3). From this point on the TPS658600 will accept all the following 2
byte pairs as a random register address, followed by the data content to be written to that register. This
process continues until the host sends a valid stop condition after the last register (Register N in
Figure 3-3) is written. A typical multi-byte sequence is shown in Figure 3-3.
Figure 3-3. Power I2C Protocol
3.16 SIMULTANEOUS STANDARD AND POWER I2C OPERATION
The TPS658600 has individual address pointers for the Power I2C engine and Standard I2C engine. The
value written to the register will be defined by the relative timing between read/write pulses when
simultaneous I2C read/write operations happen. Simultaneous write/read operations to the same register
will be handled as follows:
1. Both Standard I2C and Power I2C are executing operations accessing distinct registers at the same
time (simultaneous read/read, read/write, write/read or write/write): No conflict exists in this case.
2. Power I2C writes and Standard I2C reads the same register at the same time
(a) Standard I2C will read the old register value if the Standard I2C read pulse is generated at least
110nsec (typ) before the Power I2C write pulse happens.
(b) Standard I2C will read the new register value if the Standard I2C read pulse is generated at least
110nsec (typ) after the Power I2C write pulse happens.
3. Power I2C and Standard I2C write to the same register at the same time
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(a) If both write operations are more than 110nsec (typ) apart, the register final value will be set by the
engine that executes the last write operation.
(b) a. If both write operations are less than 110nsec (typ) apart, the priority will be given to the Power
I2C engine. The value from the Power I2C engine will be written into the register, and the data
received by the Standard I2C operation is not written to the TPS658600 internal memory.
THERE IS NO CLOCK STRETCH FUNCTION IN EITHER SCLK OR PSCLK WHEN A CONFLICT
SITUATION HAPPENS. THE CONFLICT IS HANDLED INTERNALLY BY GIVING PRIORITY TO
PSDAT/PSCLK ENGINE.
3.17 POWER PATH
3.17.1 RAM Control Bits
The power path circuit connects one of the power sources plugged into the AC, USB or BAT pins to the
SYS pin. The supply selection is made based on system parameters monitored by the power path circuit
and internal RAM control bits in register 0x4C.
Table 3-1. Power Path Control
PPATH1 [Addr 0x4C]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
USBSUSP
USBDCH
ACDCH
RSVD4B4
BOOTOFF
USBLIMIT
USBMODE
PWRSYS
Function
USB SUSPEND
MODE
SPARE
SPARE
USB INPUT
CURRENT LIMIT
SETTING
USB INPUT
CURRENT LIMIT
AUTO SYS
POWER
SELECTION
When 0
SUSPEND OFF
NOT USED
NOT USED
3.95V-4.2V
SET BY USBLIMIT
ONLY
100mA
SET BY USBLIMIT
BAT TO SYS
When 1
SUSPEND ON
NOT USED
NOT USED
4.3V-4.45V
SET BY
USBMODE AND
USBLIMIT
500mA
2.25 A
AUTO MODE
ENABLED
CHARGE
USB INPUT ILIMIT
VOLTAGE RANGE at BOOT PHASE
The input power priority is hard-wired internally, with the AC input having the higher priority, followed by
the USB input (2nd) and the battery pack (3rd). The SYS pin voltage is not regulated and it will be equal
to the input voltage (AC, USB or BAT value) minus the voltage drop across the switch that is ON when the
selected input current limit is not active.
Setting the control bit PWRSYS (bit 0) to 0, the user can override the power path priority, connecting the
battery to the SYS pin even if AC or USB are detected. When PWRSYS is 0 and the battery is removed,
the SYS pin will not be connected back to the AC or USB inputs and thereby will discharge to ground.
The USB power will be ignored when USBSUSP (bit 7) is 1, connecting only the AC or BAT power
sources to the SYS pin. If neither AC nor BAT is connected the SYS pin, it will discharge to ground.
The USB input current is limited to the maximum value programmed by the host via the I2C interface by
setting bits USBLIMIT (bit 2) and USBMODE (bit 1) as shown in Table 3-2.
Table 3-2. Power Path Current Limit
34
USBMODE
USBLIMIT
USB INPUT CURRENT LIMIT
0
0
100 mA max
0
1
500 mA max
1
X
2.1A min
DETAILED DESCRIPTION
AC INPUT CURRENT LIMIT
2.2 A min
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If the system current requirements exceed the input current limit, the SYS pin voltage will be reduced until
the power path is set in supplement mode (if pack is connected).
3.18 SYSTEM STATUS DETECTION
The TPS658600 has integrated comparators that monitor the BAT, AC, USB and SYS pin voltages. The
data generated by the comparators is used by the power path control logic to define which of the
integrated power path switches will be active. Table 3-3 lists the system power detection conditions:
Table 3-3. Power Path Detection Functions
(1)
SYSTEM STATUS
DETECTION CONDITIONS (1)
AC input voltage detected
VIN(OVP) > V(AC) > V(BAT) + VIN(DT)
USB input voltage detected
VIN(OVP) > V(USB) > V(BAT) + VIN(DT)
AC over-voltage detected
V(AC) > VIN(OVP)
USB over-voltage detected
V(USB) > VIN(OVP)
SYS pin short detected
V(SYS) < VSH(SYS)
Battery switch over-current detection
I(BAT) > IBATSYS
Supplement mode detection
V(SYS)<V(BAT)–VSUP(SYS) AND I(BAT)< IBATSYS
VIN(DT), VSH(SYS), VBATSH, VIN(OVP), VSUP(SYS) are TPS658600 internal references, refer to the electrical characteristics for additional
details
Figure 3-4. Simplified Power Path Block
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The I2C control bits and system status are used by the power path control logic to define the state of the
power path switches as shown below; a fault condition will be detected when the SYS pin is shorted or a
battery switch over-current condition is detected.
Table 3-4. Power Path Control
FAULT
DETECTE
D
AC
SWITCH
USB
SWITCH
BATTERY SWITCH
X
X
OFF
OFF
OFF
NONE
X
YES
OFF
OFF
OFF
PULL-UP RES/ISRC
YES
X
NO
ON
OFF
NO
YES
NO
OFF
ON
ON if Supplement
mode is required,
OFF otherwise
1
NO
YES
NO
OFF
OFF
ON
BATTERY
X
NO
NO
NO
OFF
OFF
ON
BATTERY
X
X
NO
OFF
OFF
ON
BATTERY
6586x MODE
PWRSYS
USBSUSP
AC
DETECTED
USB
DETECTED
UVLO
X
X
X
NOT UVLO
X
X
X
NOT UVLO
X
NOT UVLO
0
NOT UVLO
NOT UVLO
X
1
NOT UVLO
0
SYS PIN
CONNECTED TO
AC
USB
When a fault condition is detected, the fault recovery method (resistor or current source) is defined by the
input power supply detection:
Table 3-5. Power Path Fault Recovery Control
AC DETECTED
USB DETECTED
RECOVERY METHOD
YES
X
AC PULL-UP RESISTOR ON
NO
YES
USB PULL-UP RESISTOR ON
NO
NO
30mA CURRENT SOURCE ON
3.19 POWER PATH STATUS
The power path status is available at register 0xB9, bits BATSYSON, ACSWON, USBSWON , and
register 0xBB, bits LOWSYS, ACDET, USBDET, AC_OVP and USB_OVP. See the STATUS REGISTER
section for bit function description.
3.20 BATTERY CHARGER
The TPS658600 has an integrated linear charger that is designed to enable the implementation of two
distinct configurations. The TPS658600 has been configured such that the Charger input power is
supplied by the SM2 output. In this mode, the SM2 acts as a pre-regulator to the charger input. The
Charger is active when the device is in the SLEEP state.
Charger input power supplied by power path output : The SM2 voltage is set to the voltage
programmed by the host via register SUPPLYV2 control bits VSM2[4:0] at all times. The charger input pin
VIN_CHG must be connected to the power path output SYS pin. This topology has lower efficiency when
compared to the pre-regulator configuration, but it enables the use of SM2 as a stand alone converter in
systems where lower charge rates are required.
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Figure 3-5. Linear Charger Configured as Stand-Alone
SM2 acting as a pre-regulator to the linear charger input: The charger and internal control logic are
configured to work together such that during fast charge, the SYS pin voltage is down-converted by SM2
to VBAT+ 0.26V (typ), tracking the battery voltage as it increases during the charge process . This
topology achieves overall efficiency close to a switched mode charger topology. When the system is on
battery power operation, pre-charge or the thermistor is removed, the SM2 tracking mode is disabled and
SM2 down converts the battery voltage to the voltage programmed by the host via register SUPPLYV2
control bits VSM2[4:0]. When the charger is configured to turn ON in sleep mode, the SM2 output voltage
should be set using the SUPPLY2 control bits VSM2[4:0] to a voltage 250mV (typ) above the charge
regulation voltage.
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Figure 3-6. Linear Charger Configured with SM2 as Pre-Regulator
3.21 OPERATING MODES
The TPS658600 supports charging of single-cell Li-Ion or Li-Pol battery packs. The charge process is
executed in three phases: pre-charge (or pre-conditioning), constant current and constant voltage.
Protection circuits reduce the charge current when the IC junction temperature exceeds 125°C (typ,
thermal loop), or when the SYS pin voltage drops below a user-selectable threshold (DPPM loop).
When the charger is enabled, the control loops limit the BAT pin current to the programmed charge
current value (charge current loop) or regulates the BAT pin voltage to the programmed charge voltage
value (charge voltage loop). If V(BAT) < VLOWBAT, the BAT pin current is internally set to the programmed
pre-charge current value. A typical charge profile is shown below, for an operation condition when the
thermal and DPPM loops are not active.
If the operating conditions cause the IC junction temperature to exceed 125°C or the SYS pin voltage
collapses, the charge cycle is modified, with the activation of additional control loops. The DPPM and
thermal loops will override the other charger control loops and reduce the charge current. A modified
charge cycle, with the thermal or DPPM loop active, is shown in Figure 3-7 and Figure 3-8.
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Figure 3-7. Charge Phases Without Thermal
Foldback
Figure 3-8. Charge Phases With Thermal Foldback
3.22 DETECTING THE SYSTEM STATUS
The TPS658600 has integrated comparators that monitor the voltages at the BAT, TS, and VIN_CHG
pins, as well as the charge current. The data generated by those comparators is used by the control logic
to detect fault conditions and control SM2 operation. Table 3-6 lists the system power detection
conditions. VSH(VIN_CHG), VLOWBAT, and VSH(BAT) are TPS658600 internal references (refer to the electrical
characteristics for additional details).
Table 3-6. System Status Detection Conditions
STATUS
DETECTION REQUIREMENTS
VIN_CHG pin short detected
V(VIN_CHG) < VSH(VIN_CHG)
Battery voltage below pre-charge threshold
V(BAT) < VLOWBAT
Battery short detected
V(BAT) < VSH(BAT)
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SYS
2V2
1uA
VTSBIAS
I2C
DPPM AND THERMAL
CONTROL
VTSBIAS
NOBAT
0.95 * VTSBIAS
TS
COMP
CHARGE
CURRENT
I2C
VTS
BATCHG
SWITCH
Charge
Current
Loop
IO(BAT)
BAT
COLD
COMP
VBAT
0.625*VTSBIAS
VBAT
0.203*VTSBIAS
HOT
COMP
Charge
Voltage
Loop
IO(BAT) / K(SET)
VISET
ISET
CHARGE
VOLTAGE
TERM
I2C
VBATVSUP(BATCHG)
SUPPLEMENT
V(VINCHG)
DCHGOFF
1k
VISET
VIN_CHG
DISRCON
TSON
DBATRON
VIN_CHG
DBATDCH
DISRCON
DBATRON
DCHGOFF
DBATDCH
COMP
VBAT-VOC(VINCHG)
BATOC
COMP
TERMINATION
CURRENT
TERM
VISET
COMP
I2C
PRE-CHARGE
VOLTAGE
VBAT
PRECHG
VINSHORT
CHARGE CONTROL
LOGIC
COMP
V(VINCHG)
VSH(VINCHG)
V(VINCHG)
VO(BATREG) – VRCH
RECHARGE
COMP
I2C
VBAT
BATSHORT
VSH(BAT)
VBAT
Figure 3-9. Simplified Charger Block Diagram
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3.23 CHARGER RAM REGISTERS
The charger has control bits that enable user configuration of multiple charger parameters, as shown
below:
Table 3-7. Charger Control
CHG1 [Addr 0x49]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
CHGTMR[1]
CHTMR[0]
BATDCH
TSON
ISET[1]
ISET[0]
TERMOFF
CHSUSP
BATTERY
DISCHARGE
SWITCH
THERMISTOR
BIAS
CONTROL
CHARGE
TERMINATION
STATE
SUSPEND
CHARGE
OFF
OFF
TERM ON
NOT
SUSPENDED
ENABLED
ON
TERM OFF
SUSPENDED
Function
CHARGE SAFETY TIMER VALUE
When 0
00 = 4 Hrs 01 = 5 Hrs
10 = 6 Hrs 11 = 8 Hrs
When 1
CHARGE CURRENT SCALING
FACTOR
00 = 0.25 10 = 0.75
01 = 0.50 11 = 1.00
CHG2 [Addr 0x4A]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
DTCON
VPCHG
TSBYP
CHTMREN
VCHG[1]
VCHG[0]
CHGON[1]
CHBOOT
Function
DYNAMIC
TIMER
FUNCTION
PRE-CHARGE
VOLTAGE
ENABLE
CHARGER
LDO MODE
CHARGE
SAFETY
TIMER
CHARGE VOLTAGE
SELECTION
CHARGER
ON/OFF
CHARGER
OPERATION
DURING
BOOT
When 0
OFF
2.5V
OFF
OFF
SEE VCHG SETTING TABLE
When 1
ON
2.9V
ON
ON
SEE VCHG SETTING TABLE
SEE CHARGE
ENABLE TABLE
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
CHGON[0]
SYSDPPM[1]
SYSDPPM[0]
TPCHG
ITERM[1]
ITERM[0]
IPCHG[1]
IPCHG[0]
Function
CHARGER
ON/OFF
SYSTEM POWER PATH DPPM
THRESHOLD
SEE CHARGE
ENABLE TABLE
00=3.5V 01=3.75V
10=4.0V 11=4.25V
CHG3 [Addr 0x4B]
When 0
When 1
OFF
ON
Defaults in BOLD
PRE-CHARGE
TIMER
SCALING
30 MIN
60 MIN
TERMINATION CURRENT
FACTOR
PRE-CHARGE CURRENT FACTOR
00=0.04 01=0.10
10=0.15 11=0.20
00=0.04 01=0.1
10=0.15 11=0.2
Table 3-8. VCHG Settings
(1)
RSVD4B4 (1)
VCHG[1]
VCHG[0]
CHARGER REGULATION VOLTAGE (1)
0
0
0
4.10
0
0
1
4.15
0
1
0
4.20
0
1
1
3.95
1
0
0
4.30
1
0
1
4.35
1
1
0
4.40
1
1
1
4.45
The charge voltage range is set by bit RSVD4B4, located on register PPATH1, 0x4C (bit B4)
Table 3-9. Charge Enable Control
SM2
CHGON[1]
CHGON[0]
CHARGER MODE
IN SLEEP
CHARGER MODE
IN NORMAL
OFF
X
X
OFF
OFF
ON
0
0
OFF
OFF
ON
0
1
OFF
OFF
ON
1
0
ON
OFF
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Table 3-9. Charge Enable Control (continued)
SM2
CHGON[1]
CHGON[0]
CHARGER MODE
IN SLEEP
CHARGER MODE
IN NORMAL
ON
1
1
ON
ON
3.24 SUPPLEMENT MODE DETECTION
The TPS658600 charger does not have a supplement mode. The charger power mosfet will NOT turn on
when the charger is disabled and V(VIN_CHG) < V(BAT).
3.25 SHORT CIRCUIT DETECTION
The BAT pin is monitored for a short circuit condition. If V(BAT) < VSH(BAT) , the BATCHG switch is turned
OFF and an internal resistor is connected from VIN_CHG pin to BAT pin.
3.26 DPPM FUNCTION
Internal circuits monitor the voltage at the SYS pin and reduce the charge current when V(SYS) <
VSYS(DPPM). This function assures that the external power is used to run the system. The threshold
VSYS(DPPM) can be programmed using the I2C bits SYSDPPM<1:0> in register CHG3.
3.27 BATTERY DETECTION, TEMPERATURE QUALIFICATION
Battery pack insertion and battery pack temperature are detected by three comparators that monitor the
thermistor voltage. The thermistor supply is enabled via I2C when control bit TSON=HI in register CHG1.
This control bit enables the host software to turn on the thermistor bias when the charger is off and the
pack temperature needs to be measured via the ADC, minimizing system quiescent current when
operating under battery power. When the charger is activated, the thermistor power is enabled
independent of the state of bit TSON.
The host software must disable the charger by setting bit CHGON(1)=0 when the battery pack removal is
detected by the TPS658600. This procedure is required in order to avoid undesired transients when a
battery pack is hot-plugged in the system.
3.28 BATTERY PRE-CONDITIONING
The TPS658600 applies a pre-charge current Io(PRECHG) to the battery if the battery voltage is below the
VLOWBAT threshold, pre-conditioning deeply discharged cells. The resistor, RISET, connected between the
ISET and AGND pins, determines the pre-charge rate. The pre-charge rate programmed by RISET is
always applied to a deeply discharged battery pack, independent of the input power selection (AC or
USB). The pre-charge current can be calculated as shown in Equation 1:
IO(PRECHG) =
KPRECHG
RISET
(1)
where KPRECHG is the pre-charge current scaling factor in AΩ.
The pre-charge current is set by the resistor on the ISET pin and can be scaled via I2C register CHG3 bits
IPCH_1, IPCH_0 to a percentage (20%, 15%, 10%, or 4%) of the value set by RISET. The pre-charge
voltage is selectable via bit VPCHG, register CHG2.
3.29 CONSTANT CURRENT CHARGING
The constant charge current mode (fast charge) is set when the battery voltage is higher than the
pre-charge voltage threshold. The fast charge current regulation point is defined by the external resistor,
RISET, connected to the ISET pin as shown in Equation 2.
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IO(BAT) =
K SET
RISET
(2)
where KSET is the charge current scaling factor in AΩ.
The charge current is set by the resistor on the ISET pin and can be scaled via I2C register CHG1 bits
ISET1[1:0] to a percentage (100%, 75%, 50% or 25%) of the value set by RISET.
The ISET resistor will always set the maximum charge current if the AC input is selected. When the USB
input is selected the maximum charge current will be defined by the USB input current limit and the
programmed charge current. If the USB input current limit is lower than the IO(BAT) value, the battery switch
will be set in the dropout region and the charge current will be defined by the input current limit value and
system load, as shown in Figure 3-10.
Figure 3-10. USB Supplement Mode
3.30 BATTERY VOLTAGE REGULATION, CHARGE VOLTAGE
The Voltage regulation feedback is implemented by sensing the BAT pin voltage, which is connected to
the positive side of the battery pack. The TPS658600 monitors the battery-pack voltage between the BAT
and AGND1 pins. When the battery voltage rises to the VO(BATREG) threshold, the voltage regulation phase
begins and the charging current tapers down.
The charging voltage can be selected via I2C, with bits VCHG<1:0> (register VCHG1) and RSVD4B4
(register PPATH1, 0x4C)
3.31 LDO MODE OPERATION
The LDO mode makes it possible to run critical subsystems connected directly to the battery node (BAT
pin) when the battery is removed and the end equipment is powered by the AC or USB input.
The SM2 voltage must be programmed by the host via register SUPPLYV2 control bits VSM2<4:0> to a
value 100mv above the programmed charge voltage before the LDO mode is enabled, and it should be
left at that value while LDO mode is in use. The SM2 voltage can be set to any other value after the LDO
mode is disabled.
The charger LDO Mode operation is enabled when termination is disabled (TERMOFF bit is 1 in CHG1)
and thermistor removal detection is ignored (setting TSBYP bit to 1 in CHG2).
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When the LDO mode is set, termination is disabled, all safety timers are held in reset, and the battery
discharge switch is disabled. The BAT pin voltage will regulate to VO(BATREG) when all the following
conditions are true: the charger is enabled (VIN_CHG > VO(BATREG)) and input power is present (AC or
USB input power detected). Under these conditions the BAT pin voltage will be regulated to the charge
voltage VO(BATREG) if the charger current loops are not active.
The charger current limit loop will still be enabled, and the current that can be supplied by the BAT pin in
LDO mode will be dependent on the BAT pin voltage, as shown in Table 3-10.
Table 3-10. Battery Charge Current
BAT PIN VOLTAGE
BATTERY CHARGE CURRENT
< VLOWBAT
IO(PRECHG)
> VLOWBAT
IO(BAT)
In LDO mode, both the thermal loop and DPPM loop are also enabled. These loops, when active, limit the
current available at the BAT pin. The BAT pin voltage will collapse if the charge current available is lower
than the current required to run subsystems connected to the BAT pin.
The battery tracking function is disabled when the thermistor is not detected; the BAT pin will, as a result,
track the SM2 output voltage when V(SM2) is set below VO(BATREG).
3.32 CHARGER CONTROL LOGIC AND OPERATING MODES
The charger control logic monitors system parameters and control signals to define when the charger is
enabled. The table below lists the charger operating modes. Note that when the charger is set to OFF all
timers are reset. The charge is enabled by setting bit CHGON to 1 in register CHG2.
The timer fault and termination detection events are latched internally to the charger control logic, and
after that the charger is set to OFF. The only way to reset a timer fault and termination detection is to start
a new charge cycle.
Table 3-11. Charger Mode Control
TPS658600
MODE
UVLO
NOT UVLO
(1)
INPUT POWER
DETECTED
SM2
MODE (1)
CHARGER
THSHUT
DETECTED
CHARGE
ENABLED
CHARGE
SUSPEND
CMD
TIMER
FAULT
DETECTED
PACK
TEMP
FAULT
TERM
DETECTED
CHARGER
MODE
X
X
X
X
X
X
X
X
OFF
NO
X
X
X
X
X
X
X
OFF
YES
OFF
X
X
X
X
X
X
OFF
YES
ON
YES
X
X
X
X
X
OFF
YES
ON
NO
NO
X
X
X
X
OFF
YES
ON
NO
YES
NO
NO
NO
NO
ON
YES
ON
NO
YES
NO
YES
X
X
OFF
YES
ON
NO
YES
NO
X
X
YES
OFF
YES
ON
NO
YES
YES
NO
X
NO
SUSPEND
YES
ON
NO
YES
NO
NO
YES
NO
SUSPEND
When SM2 is not configured as the charger pre-regulator the SM2 mode does not affect the charger mode.
3.33 CHARGE SUSPEND
The charge may be suspended anytime by setting CHSUSP to 1 in register CHG1 or when the pack
temperature is out of range and I2C control bit TSBYP is 0. This will disable the charger stage and hold
the safety timers at their current count. Normal operation resumes when a temperature fault is not
detected.
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3.34 CHARGE TERMINATION
The TPS658600 monitors the charging current during the voltage regulation phase. Charge is terminated
when the charge current is lower than an internal threshold, set to 10% (typ) of the fast charge current
rate. The termination point applies to both AC and USB charging, and it can be calculated as shown in
Equation 3.
ITERM =
K TERM
RISET
(3)
where KTERM is the termination constant detection factor.
The termination current may be scaled using I2C register CHG3 bits ITERM[1:0].
The termination detection is internally deglitched by TDGL(TERM) , 25ms typ. When the charge current drops
below the internal termination threshold for t > TDGL(TERM), the bit ITERM is set to 1 in the status register
STAT, indicating that termination was detected. ITERM is not affected by the state of TERMOFF control
bit, and it will always report the charge current status. If the termination is enabled (TERMOFF cleared to
0) and termination is detected, the charge cycle ends and the charger is turned off.
Table 3-12. Termination Detection Conditions
CHARGE CURRENT
BELOW TERMINATION
THRESHOLD
DPM OR DPPM OR
THERMAL LOOP
ACTIVE
CHARGER MODE
TERMINATION
DETECTION ENABLED
VIA I2C
TERMINATION
DETECTED,
I(BAT) < ITERM
NO
X
X
X
NO
YES
X
OFF
X
NO
YES
X
SUSPEND
X
NO
YES
X
ON
NO
NO
YES
YES
ON
YES
NO
YES
NO
ON
YES
YES
The termination detection is latched and it will be reset only when a new charge cycle starts.
The I2C charge status bits in the STAT2 register only indicate DONE state when termination is detected.
3.35 STARTING A NEW CHARGE CYCLE
A new charge cycle will start only if the voltage on the BAT pin falls below the V(RCH) threshold for a time
longer than TDGL(RCH), 25ms (typ). A new charge cycle also starts when bit CHGON (CHG1 register)
changes from 0 to 1, or if both AC and USB input power are removed and then one or both are
re-inserted.
After termination is detected a new battery pack insertion detection will not start a new charge cycle, even
if V(BAT) < V(RCH).
3.36 PRE-CHARGE SAFETY TIMER
The TPS658600 activates an internal safety timer during the battery pre-conditioning phase. The
pre-charge safety timer value is set internally to a fixed value, TPRECHG, 30 min or 60 min typ, selectable
via I2C. The pre-charge safety timer is disabled when the termination is disabled via I2C (bit
TERMOFF=HI, register CHG1) or when CHTMREN=0 at the I2C register CHG2.
When the charger is in suspend mode the pre-charge safety timer is put on hold (i.e., charge safety timer
is not reset). Normal operation resumes when the charger exits the suspend mode. If V(BAT) does not
reach the internal voltage threshold V(PRECHG) within the pre-charge timer period a fault condition is
detected and the charger is turned off.
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3.37 CHARGE SAFETY TIMER
As a safety mechanism the TPS658600 has a user-selectable timer that measures the total fast charge
time. This timer (charge safety timer) is started at the end of the pre-conditioning period. The following
values are available: 4, 5, 6, 8 hours, selectable via I2C register CHG1 bits CHGTMR. The charge safety
timer is kept in reset mode when CHTMREN=0 at the I2C register CHG2. The charge safety timer is
disabled when TERMOFF=1, in register CHG1. When the charger is in suspend mode, set via I2C register
CHG_CONFIG bit CHGON or set by a pack temperature fault, the charge safety timer is put on hold (i.e.,
charge safety timer is not reset). Normal operation resumes when the charger exits the suspend mode. If
charge termination is not reached within the timer period a fault condition is detected, and the charger is
turned off.
3.38 TIMER FAULT RECOVERY
The TPS658600 provides a recovery method to deal with timer fault conditions. The following summarizes
this method:
Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs.
Recovery
method:
The IC waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge or battery removal. Once
the battery falls below the recharge threshold, the IC clears the fault and starts a new
charge cycle.
Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs.
Recovery
method:
Under this scenario, the IC connects an internal pull-up resistor from VIN_CHG pin to
BAT pin. This pull-up resistor is used to detect a battery removal condition and
remains on as long as the battery voltage stays below the recharge threshold. If the
battery voltage goes above the recharge threshold, the IC disables the pull-up resistor
connection and executes the recovery method described for condition 1.
All timers will be reset and all timer fault conditions are cleared when a new charge cycle is started
either via I2C (toggling bit CHGON in register CHG1) or by cycling the input power. All timers are
reset and all timer fault conditions are cleared when the TPS658600 enters the UVLO mode or if the
LDO mode is set.
3.39 DYNAMIC TIMER CONTROL
When the charger, thermal loop or DPPM loop are active the charge current is reduced. To avoid a false
termination detection when those loops are active the charger logic doubles the period of the clock used
by the charge safety timer.
The clock frequency is divided by 2 when any of those loops are active and DTCON=1. The dynamic timer
control may be disabled by setting control bit DTCON=0, at the CHG2 I2C register.
3.40 BATTERY DISCHARGE SWITCH
An internal switch will discharge the BAT pin to ground when the battery is not detected. This switch is
enabled via I2C control bit BATDCH on register CHG1.
3.41 CHARGER STATUS
Charger status information is available at registers 0xB9, bits PACK_HOT, PACK_COLD, BATDET and
BATCHGSWON; register 0xBA, bits TMRFLT, DPPM_ON, TH_ON, ITERM, STAT1 and STAT2 . See
STATUS REGISTERS section for bit functional description. The charger status also is indicated at pin
CHG_STAT , this pin can be used as a logic level output (2v2 level) or it can be connected to an external
LED.
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Table 3-13. Charger Status Pin States
0xBA[2]
(STAT1)
0xBA[1]
(STAT2)
CHARGER STATE
CHG_STAT LEVEL
0
0
Pre-Charge
HI
0
1
Charge Done
LO
1
0
Fast Charge
HI
1
1
Charge Suspend, Timer fault
LO
3.42 TPS658600 OPERATING MODES
The TPS658600 has an internal state machine that sets the operating modes based on the system status
and host commands. The state machine directly controls the state of the integrated supplies during
power-up sequences and normal operation. It also can change the on/off state of all integrated power
supplies and peripherals to implement protection functions or execute external hardware control or host
software commands.
DETAILED DESCRIPTION
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3.43 STATE MACHINE DIAGRAM
V(AC) > VUVLO
OR
V(USB) > VUVLO
OR
V(BAT) > VUVLO
POWER UP(B)
ALL REGISTERS RESET TO
DEFAULT
ENABLE POWER PATH
OPERATION
nNOPOWER=LO
{ [ INPUT POWER(AC OR USB):
NOT DETECTED Ø DETECTED] OR
[RESUME=HI FOR 550ms (min) DETECTED]
OR
[ RTC_ALARM=HI ] }
AND
[ V(SYS) > VLOW_SYS AND
SLEEP NOT SET BY THERMAL
FAULT ]
AND
INITIAL POWER UP CYCLE DONE
NO POWER
ALL
SUPPLIES
OFF
TPS6585X
IN UVLO
MODE
V(SYS) > VLOWSYS AND t>TPOR
ANY
STATE
RTC(B)
ALL SUPPLIES OFF
FORCE RTC_OUT LDO OFF
nNOPOWER=LO
RESET/START T CHECK TIMER
t >TWAIT
CYCLE= INITIAL POWER UP
AND
V(SYS) > VLOW_SYS AND
t > TCHECK
CYCLE=POWER UP DONE
AND
V(SYS) > VLOW_SYS AND
t > TCHECK
WAIT (B)
nNOPOWER=LO
SUPPLIES OFF
RTC REGISTERS RESET IF RTC_OUT < VUVLO_RTC
EE-LOADABLE REGISTERS ARE
NOT RESET (KEEP VALUES)
ALL OTHER REGISTERS RESET TO DEFAULT
BOOT TIMER EXPIRES
OR
[ HOTPLUG TIMER EXPIRES AND
V(SYS) < VLOW_SYS FOR 5mSEC AND
SLEEP BY LOWSYS ENABLED]
t > TWAIT – TWAIT1
HARD REBOOT
ALL SYNC SUPPLIES OFF
nNOPOWER=LO
RESET/START T WAIT TIMER
RTC_ON(B)
FORCE RTC_OUT LDO ON
nNOPOWER=LO
ALL SUPPLIES OFF
ALL REGISTERS RESET TO DEFAULT
RESET/START TIMERS : TNORTC ,
THOTPLUG, TBOOT
SLEEP STATE
NO I2C COMMUNICATION
V(2V2) < VUVLO
CYCLE=
INITIAL POWER UP
ALL SUPPLIES OFF
FORCE RTC_OUT LDO ON
ENABLE nNOPOWER TIMER
RESET/START T MAX TIMER
V(RTC_OUT) > VRTCLOW
OR t > TMAX
t >TWAIT
AND
REBOOT REQUEST
TO HARD REBOOT
ENABLED
SUPPLYSEQ (B)
FORCE RTC_OUT LDO ON
RTC REGISTERS NOT RESET (KEEP VALUES)
ALL OTHER REGISTERS RESET TO DEFAULT
RESET/START TIMERS : TNORTC , THOTPLUG, TBOOT
EXECUTE SUPPLY SEQUENCING
nNOPOWER=LO
RESET/START TIMER T SYNCEND WHEN
SEQUENCING IS COMPLETE
SUPPLY
SEQUENCING
COMPLETE
AND
t > TSYNCEND
BOOT TIMER EXPIRES
OR
[ HOTPLUG TIMER EXPIRES AND
V(SYS) < VLOW_SYS FOR 5mSEC AND
SLEEP BY LOWSYS ENABLED]
t > TWAIT1
POWER GOOD CHECK(B)
FORCE RTC_OUT LDO ON
PGOOD FAULT
DETECTED
NO PGOOD FAULT
SLEEP REQUEST
NO THERMAL FAULT
AND
SLEEP EXIT SET VIA I2C
AND
CYCLE=POWER UP DONE
RESET/ START
TWAIT TIMER
THERMAL FAULT
ANY
STATE
NORMAL MODE
ENABLE WRITE TO DVM REGISTERS
RTC REGISTERS RESET IF RTC_OUT < VUVLO_RTC
TURN OFF ENABLE PIN PULL-DOWN RESISTORS
ENABLE SUPPLY OUTPUT DISCHARGE
RESISTORS
[RESUME = HI FOR 400ms (min) DETECTED] OR
[PGOOD FAULT AND NORMAL MODE SET ] OR
SLEEP MODE SET VIA I2C
OR
[ HOTPLUG TIMER EXPIRED AND
V(SYS) < VLOW_SYS FOR 5mSEC AND
SLEEP BY LOWSYS ENABLED VIA I2C ]
REBOOT SET VIA I2C OR
nHOTRST PIN LO PULSE
DETECTED
REBOOT
REQUEST
RESET/ START
TWAIT TIMER
nNOPOWER=LO
WHEN ANY OF THE BOOT PHASE (B) STATES ARE SET :
1 - WRITE TO DVM REGISTERS IS DISABLED
2 - SM0EN, SM1EN, SYNCEN,LDO4EN PULL-DOWN RESISTORS ON
3 - SUPPLY OUTPUT DISCHARGE RESISTORS ON
Figure 3-11. TPS658600 Operation Mode State Machine
The state machine transitions for the TPS658600 have been defined as shown below.
1. Supply sequencing started only when LDO4EN voltage level is a logic high
2. REBOOT REQUEST state transitions to the HARD REBOOT state
3. Supply sequencing is considered complete only if SM0 is turned ON
4. Sequencer goes into sleep during initial power-up cycle and ONLY RESUME pin can trigger exit from
sleep state
3.44 STATE MACHINE DESCRIPTION
In a normal power-up sequence the state machine will step through the following states:
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POWER-UP: If the internal digital supply (2V2) is below the internal UVLO threshold, VUVLO (2V typ), all IC
blocks are disabled and the TPS658600 is not operational. When the 2V2 supply voltage rises above
VUVLO, the POWER-UP state is entered, an internal delay (TPOR, 8ms typ) is started and the SYS power
path is enabled. The SYS pin voltage is sensed by an internal comparator, and compared to the internal
threshold VLOW_SYS. When the power-on-reset delay expires and V(SYS) > VLOW_SYS the TPS658600
enters the RTC mode.
RTC: When the RTC state is set the nNOPOWER pin is pulled to ground, discharging the external
capacitor connected to pin TNOPOWER and resetting the NOPOWER timer. The RTC_OUT LDO is
turned off, and the voltage at pin RTC_OUT is flagged as low if V(RTC_OUT) < VRTCLOW The RTC state
ends when the timer TCHECK expires.
RTC_ON: When the state RTC_ON is set the integrated current source connected to the TNOPOWER pin
and the RTC_OUT LDO are enabled. If the RTC_OUT voltage was flagged as low in the RTC state the
TNORTC timer is enabled, and the NORTC pin is pulled low until V(RTC_OUT) > VRTC_PGOOD. The TNORTC
timer starts counting when RTC_OUT > VRTCLOW, and NORTC will be set to hi when t > TNORTC.
The TNOPOWER current source will remain ON until a new reboot cycle or sleep cycle is set, charging
the external capacitor connected to the TNOPOWER pin. The NOPOWER pin will be at a low logic level
until the TNOPOWER pin voltage is above an internal threshold (1.23v typ). When NOPOWER pin
transitions from LO→HI, a 250μsec (typ) positive going pulse is generated at CHG_STAT pin. The
TNOPOWER external capacitor is discharged whenever the sequencer sets the NOPOWER pin to a low
state.
The RTC_ON state ends when V(RTC_OUT) > VRTC_PGOOD or when the internal watchdog timer TMAX
expires.
WAIT: The TPS658600 will go into the WAIT state when exiting the RTC state during the initial power-up
cycle. To avoid undesired lockup conditions this operational mode should be used only when the boot
timer is enabled.
Three internal timers are started when the state machine enters the WAIT state. These timers run
independent of the sequencing state and have the following functionality:
• BOOT Timer (TBOOT): Sets the TPS658600 in the SLEEP REQUEST state if it expires during WAIT
state.
• HOTPLUG Timer (THOTPLUG): SLEEP REQUEST state set by V(SYS) < VLOWSYS is inhibited until this
timer expires
• NORTC Timer (TNORTC): NORTC pin will be set to a logic low level until this timer expires
The BOOT timer value is set to 500ms and the NORTC pulse width is set to 10ms.
SUPPLYSEQ: During the SUPPLYSEQ state all the internal supplies, with exception of RTC_OUT, are
initially turned off and then turned on according to a pre-programmed internal sequencing. Three internal
timers are started when the state machine enters the SUPPLYSEQ state. These timers run independent
of the sequencing state and have the following functionality:
• BOOT Timer (TBOOT): Sets the TPS658600 in the SLEEP REQUEST state if it expires during
SUPPLYSEQ state.
• HOTPLUG Timer (THOTPLUG): SLEEP REQUEST state set by V(SYS) < VLOWSYS is inhibited until this
timer expires
• NORTC Timer (TNORTC): NORTC pin will be set to a logic low level until this timer expires
The BOOT timer value is set to 500ms and the NORTC pulse width is set to 10ms.
The I2C engines are available while the device is in the SUPPLYSEQ state, however write operations to
the DVM registers are disabled, refer to DVM register section for more details. The TPS658600 remains in
this state until all the supplies are sequenced and the internal delay TSYNCEND (5ms typ) has expired.
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POWER GOOD CHECK: Supplies that were powered up during the SUPPLYSEQ state will have their
power good flags checked during the POWER GOOD CHECK state (with exception of RTC_OUT ldo).
The POWER GOOD CHECK state ends and the NORMAL state is set when a power good fault is not
present. If a power good fault is detected, the POWER GOOD CHECK state will move to the SLEEP
REQUEST state when the boot timer expires.
NORMAL STATE: In this state write operations to the DVM registers are enabled and the external host
controls all the TPS658600 functions. The normal state operation ends if a fault condition (defined as
either a thermal fault, V(SYS) < VLOW_SYS or a supply power good fault) is detected or if hardware or
software commands trigger a sleep or reboot request. While in NORMAL mode, the host can mask any of
the power supply power good fault detection via I2C registers PGFLTMASK1 and PGFLTMASK2. Supplies
that have their power good fault detection masked will not end the normal state operation. However, the
status bit for the supply indicates that the output voltage is out of regulation. A RTC_OUT LDO power
good fault does not trigger a transition to SLEEP REQUEST.
Table 3-14. Sequencer Power Good Fault Masking
PGFLTMASK1 [Addr 0x4D]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
MASK_PLDO8
MASK_PLDO7
MASK_PLDO6
MASK_PLDO4
MASK_PLDO3
MASK_PLDO2
MASK_PLDO1
MASK_PLDO0
Function
MASK
PGOODLDO8
MASK
PGOODLDO7
MASK
PGOODLDO6
MASK
PGOODLDO4
MASK
PGOODLDO3
MASK
PGOODLDO2
MASK
PGOODLDO1
MASK
PGOODLDO0
When 0
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
When 1
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
PGFLTMASK2 [Addr 0x4E]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
MASK_PSM3
MASK_PSM2
MASK_PSM1
MASK_PSM0
MASK_PLDO9
MASK_PLDO5
RSVD4E1
RSVD4E0
Function
MASK
PGOODSM3
MASK
PGOODSM2
MASK
PGOODSM1
MASK
PGOODSM0
MASK
PGOODLDO9
MASK
PGOODLDO5
NOT USED
NOT USED
When 0
UNMASKED
MASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
NOT USED
NOT USED
When 1
MASKED
UNMASKED
MASKED
MASKED
MASKED
MASKED
NOT USED
NOT USED
SLEEP REQUEST: The SLEEP REQUEST state is set at anytime when a thermal fault condition is
detected. It is also set when the TPS658600 is in the NORMAL state followed by one of the events shown
below.
1. A hardware sleep request is detected at the RESUME pin.
2. A power good fault is detected at any of the integrated supplies
3. V(SYS_IN) < VLOW_SYS and the HOTPLUG timer has expired (t > THOTPLUG)
4. SLEEP MODE is 1 (register 0x14, bit B3)
When the SLEEP REQUEST state is set an internal timer is started and bit SLEEPREQ=1 is set in
register STAT3 (address 0xBB). Writing EXITSLREQ to 1 (0x14, bit B1) returns the TPS658600 to the
NORMAL state. If no action is taken by the host, while SLEEP_REQUEST state is set, the NOPOWER pin
is pulled low when TWAIT1 expires and the SLEEP state is entered after the TWAIT timer expires.
Table 3-15. Sequencer Control, LDO5/LDO9 Enable
SUPPLYENE [Addr 0x14]
50
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
LDO9_ON
LDO5_ON
SYSINEN
HOTDLY
SLEEP MODE
RSVD
EXITSLREQ
SOFT RST
Function
LDO9 ON/OFF
CONTROL
LDO5 ON/OFF
CONTROL
SYS_IN LOW
VOLTAGE
SETS SLEEP
MODE
HOT RESET
DEGLITCH
SET
TPS658600 IN
SLEEP MODE
SLEEP
REQUEST
EXIT
CONTROL
SOFTWARE
RESET
CONTROL
When 0
OFF
OFF
DISABLED
5μsec min,
16μsec max
NOT ACTIVE
GO TO SLEEP
at T>Twait
NOT ACTIVE
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Table 3-15. Sequencer Control, LDO5/LDO9 Enable (continued)
When 1
ON
ON
ENABLED
5ms
FORCE
TRANSITION
TO NORMAL
STATE
SET SLEEP
REBOOT
REQUEST
SLEEP STATE: When the SLEEP state is set all supplies are set to OFF mode (with exception of
RTC_LDO) and the NOPOWER output is pulled low. A few internal blocks are still active, enabling
detection of system status changes that trigger the SLEEP state exit.
All I2C engines are reset and all RAM registers are reset to their default condition when the SLEEP state
is set. The RAM bits that have a default set via the non-volatile memory will keep the value they had
before the SLEEP state was set.
The SLEEP state ends when one of the following sequences is executed:
A. If SLEEP was set by thermal fault: The SLEEP state will end only when all external input supplies and
battery pack are removed and an UVLO condition is detected by the TPS658600, setting the POWER
UP state.
B. If SLEEP was not set by thermal fault: The SLEEP state will end when a hardware sleep exit request is
detected at RESUME pin
EXITING THE SLEEP STATE: The figure below shows the timing relationship needed on the RESUME
pin to exit the sleep mode. This applies for all cases where the sleep mode entry was triggered by any
event other than a thermal fault.
TRESUME(H)
TRESUME(L)
TRESUME(H)
RESUME PIN
TPS6586x
MODE
NORMAL MODE
SLEEP MODE
NORMAL MODE
SET SLEEP
ENTER/EXIT
SLEEP
EXIT SLEEP
Figure 3-12. Entering and Exiting Sleep Mode Resume
REBOOT REQUEST: The REBOOT REQUEST state is entered from the NORMAL state. It can be set via
software (SOFT_RST set to 1, register 0x14 Bit B0) or by a VIL level detection at HOTRST pin. When the
reboot request state is set an internal timer TWAIT (10ms typ) is started, and the NOPOWER pin is pulled
to ground. The reboot request ends when t > TWAIT. The REBOOT REQUEST will transition the device
state machine to the HARD REBOOT state. The REBOOT REQUEST is set if the HOTRST low pulse
width is greater than 10μsec (typ).
The status bit COMPDET=1 (register STAT2, address 0xBA) when the NORMAL state is entered after a
reboot cycle triggered by the HOTRST pin. The status bit COMPDET=0 when the NORMAL state is
entered, after a power-up, sleep cycle or software triggered reboot cycle.
The bit COMPDET is reset to 0 when bit SPARECC0=1, in register SPARE2 (address 0xCC). After
resetting the COMPDET bit the host needs to set SPARECC0=0 to enable detection of another reboot
cycle set via the HOTRST pin.
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An interrupt is generated when the TPS658600 transitions from the POWER GOOD CHECK state to the
NORMAL state , COMPDET=1 and IMASK_COMP=0 in register INTMASK4 (address 0xB3). An interrupt
request is generated after the NORMAL state is set if IMASK_COMP=0 and COMPDET value changes
from 1 to 0.
Table 3-16. Reboot Flag Control
SPARE2 [Addr 0xCC]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SPARECC7
SPARECC6
SPARECC5
SPARECC4
SPARECC3
SPARECC2
SPARECC1
SPARECC0
Function
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
RESET
REBOOT BY
HOTRST
STATUS BIT
When 0
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
DO NOT
RESET
When 1
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
RESET
HARD REBOOT: The HARD REBOOT state powers down all the TPS658600 supplies, with exception of
the RTC_OUT LDO.
SUPPLYLOAD: When the SUPPLYLOAD state is set all the registers are reset to their defaults, and the
non-volatile memory is reloaded into the RAM. The supplies are not sequenced, and they will return to
their on/off and output voltage defaults upon entering the SUPPLYLOAD state (on/off, default voltages).
The timers TBOOT, THOTPLUG and TSYNCEND are reset and started. The SUPPLYSEQ state ends when t >
TSYNCEND, and the POWER GOOD CHECK state is set.
3.45
CNOPOWER CAPACITOR DISCHARGE
The external capacitor connected to the TNOPOWER pin is always discharged when the sequencer sets
NOPOWER=LO in the following states: POWER-UP, RTC, REBOOT REQUEST, HARD REBOOT and
SLEEP. For large capacitance values (above 330nF) the external capacitor may not be fully discharged
during reboot cycles, and as a result the NOPOWER pulse width may be slightly reduced when compared
to the value indicated in the parametric tables.
3.46 SEQUENCER STATUS
Sequencer status information is available at registers 0xBA, bit COMPDET and register 0xBB bits
SLEEPREQ and RESUME. See STATUS REGISTERS section for functional description of these bits.
3.47 SUPPLY SEQUENCING AND HOST INTERFACE
3.47.1 Integrated Supply Sequencing
The TPS658600 enables the implementation of complex supply sequencing. With the exception of
RTC_OUT, the integrated power-up sequencing starts when the TPS658600 state machine enters the
SUPPLYSEQ state. The RTC_OUT LDO is always enabled in the RTC state, which occurs before the
SUPPLYSEQ state, and the output of this LDO can be used to power an external processor or circuitry in
systems where the supply sequencing is controlled externally using pins SM0EN, SM1EN or SYNCEN.
Each supply rail is controlled by a combination of its default status (ON or OFF), its assigned sequencing
trigger group (INTERNAL, SM0EN, SM1EN or SYNCEN), and a delay time.
The default status (ON or OFF) of each rail is shown in Table 3-17.
If the default for a supply rail is ON the trigger group associated to the supply determines the control
signal that initiates the delay time to the start of the rail power up. There are four trigger groups, one
internal and three external pins:
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INTERNAL
This group is controlled by an internal signal that goes high when the TPS658600 goes
from the RTC_ON state to the SUPPLYSEQ state.
SM0EN
This group is controlled by the falling edge of the SM0EN pin and starts when the pin
voltage is below its VIL level.
SM1EN
This group is controlled by the rising edge of the SM1EN pin and starts when the pin
voltage is above its VIH level.
SYNCEN
This group is controlled by the rising edge of the SYNCEN pin and starts when the pin
voltage is above its VIH level.
The trigger group of each rail and its associated delay is shown in Table 3-17. If a supply rail has a default
state of ON and the appropriate trigger is high, the rail will be turned on after the delay time for that rail
has expired. The delay time starts when the trigger signal for that supply has gone high, while
SUPPLYSEQ state is set. No delays are available after NORMAL mode is set.
Table 3-17. TPS658600 Integrated Supply Power-Up Defaults
TPS658600 SETTINGS
SUPPLY
DEFAULT
STATE
DEFAULT
VOLTAGE
TRIGGER
DELAY
LDO0
ON
2.85V
SM1EN
LDO1
ON
1.2V
INTERNAL
15ms
Value applies to LDO0, LDO1
LDO2
ON
1.2V
INTERNAL
LDO3
OFF
1.8V
SM1EN
0ms
Value applies to LDO2, LDO3
LDO4
OFF
1.8V
INTERNAL
2.5 ms
LDO6
ON
2.85V
SYNCEN
LDO7
OFF
2.85V
INTERNAL
LDO8
ON
2.85V
SYNCEN
LDO5
OFF
2.85V
LDO9
OFF
2.85V
SM1EN
Trigger applies to both LDO5 and LDO9
3.75ms
Value applies to LDO5, LDO9
SM0
ON
1.2V
SM0EN
2.5ms
SM1
ON
1.8V
SM1EN
15ms
SM2
OFF
4.4V
INTERNAL
15ms
2.5ms
Value applies to LDO6, LDO7 and LDO8
3.48 INTEGRATED SUPPLY SEQUENCING – SUPPLY ENABLE CONTROL
The ON or OFF mode for each supply is defined by the supply enable RAM control bits and enable pins
SM0EN, SM1EN and LDO4EN. The supply enable bits are located in registers SUPPLYENA,
SUPPLYENB, SUPPLYENC, SUPPLYEND, SUPPLYENE (see supply functional description for more
details). The functionality of the RAM bits and enable pins is dependent on the state set in the state
machine as follows:
When the NORMAL state is NOT set : The pins SM1EN , SM0EN and LDO4EN will always control the
ON or OFF modes for all supplies that use them as triggers. The supply enable RAM bits will control the
ON or OFF modes for the supplies.
When the NORMAL state is set: The supply enable RAM bits will always control the ON or OFF modes
for the supplies. The pins SM1EN, SM0EN and LDO4EN may control the ON or OFF modes for supplies
SM1, SM0 and LDO4. The enable pins do not control the ON or OFF modes of any other supplies.
During sequencing, the following RAM bits control the supply ON/OFF mode: LDO2 RAM bits, LDO4 RAM
bits, SM0 RAM bits and SM1 RAM bits.
When the NORMAL mode is set, SM0EN controls the SM0 ON/OFF mode, SM1EN controls the SM1
ON/OFF mode and LDO4EN controls the LDO4 ON/OFF mode.
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3.49 INTEGRATED SUPPLY SEQUENCING – POWER-DOWN
To start a power down sequence the SLEEP REQUEST or REBOOT REQUEST states must be set. Once
one of those two states is set the trigger pins are active again and they will control the ON/OFF state of
the supplies associated with that trigger group. The device will enter the SLEEP or HARD REBOOT state
10ms after the SLEEP REQUEST or REBOOT REQUEST is initiated. Any supply still active when the
SLEEP or HARD REBOOT state is entered will be immediately disabled. This is the default turn off
condition for any supply associated with the INTERNAL sequencing trigger group.
For example, if a supply has a default state of OFF and it has SM1EN as the selected factory trigger: this
supply will not power up during the SUPPLYSEQ state when SM1EN goes high. If it is enabled during the
NORMAL state and is still enabled when the SLEEP REQUEST or REBOOT REQUEST states are
entered, this supply will be turned off on the falling edge of SM1EN as this is its assigned trigger group
programmed at the factory.
If LDO4EN is set LO by the host when the TPS658600 enters the SLEEP REQUEST or REBOOT
REQUEST states, the LDO4 supply will turn off only when the HARD REBOOT or SLEEP states are set.
The LDO4PG pin will be pulled low when LDO4EN is below VIL, with no delay.
All the supplies are turned off at the same time when the TPS658600 enters the SLEEP or HARD
REBOOT state.
3.50 HOST INTERFACE
The TPS658600 devices have multiple signals that can be used by the external system to execute power
sequencing operations or verify the system status. Those signals are generated as follows:
1. Power supply status (2V2 logic level) : SM0PG, SM1PG, LDO4PG – A HI level indicates that the
supply is on and the regulation voltage is valid. A LO level indicates either that the supply voltage is
out of regulation or that the supply has been disabled.
2. External system and host control (V32K pin logic level): The NOPOWER, NORTC, and OUT32K pins
may be used to interface to external hosts, controlling the host reset and executing host-controlled
power-up sequencing.
3.51 EXTERNAL 32 kHz
The TPS658600 outputs a 32 kHz clock (pin OUT32K) that can be used by the external system. The
OUT32K output starts when the NORTC pin is above VIH and V32K is valid. The 32 kHz can be derived
either from an internal 32kHz oscillator or from a crystal-based clock, selectable via I2C using bit 6 of the
RTC_CTRL (Addr 0xC0) register (see the Real Time Clock section). However, only the crystal-based
clock is output to the OUT32K pin.
3.52 SUPPLY INPUT PIN CONNECTION
The input pins for all supplies (VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9) enable
optimization of the overall system power architecture by connecting lower output voltage supplies to
intermediate rails or external rails. Care must be taken to ensure that the input pin for each integrated
supply is powered when the supply is enabled during the power-up sequencing. Failure to do so will result
in a power good fault detection with a potential lock-up situation. The input pins VIN_SM0, VIN_SM1,
VIN_SM2 must be connected to the SYS pin
3.53 HOST INTERFACE
The TPS658600 may be used in systems where the sequencing is controlled by an external host or
housekeeping circuit, as well as in systems where stand-alone sequencing is a requirement. For host
controlled systems the RTC_OUT LDO can be used as the supply that powers the external sequencing
control and the NOPOWER and NORTC pin signals are used as resets for the external circuit.
54
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Power applied
AC, USB OR BAT
2V2
VUVLO
VLOW_SYS
SYS
RTC_OUT/BBAT
32KHZ_OUT
HOST CONTROLLED
SEQUENCING :
VRTCLOW
RTC_OUT SUPPLIES
EXTERNAL CIRCUIT
THAT DRIVES SUPPLY
POWER-UP USING
TRIGGER PINS SM0EN,
SM1EN, SYNCEN
32kHZ
X
ENABLE
PINS
NOPOWER
NORTC
X
X
Z
TPOR=8mSec
TNOPOWER
TNORTC
6586X POWER-UP
EXTERNAL CONTROL
CIRCUIT RESET
HOST-BASED SEQUENCING OF SUPPLIES
SEQUENCING COMPLETED
Figure 3-13. Host Controlled Startup
Power applied
AC, USB OR BAT
2V2
VUVLO
6586X SEQUENCING :
VLOW_SYS
SYS
32KHZ_OUT
HOST IS KEPT IN
RESET MODE UNTIL
6586X SEQUENCES ALL
SUPPLIES FOLLOWING
INTERNAL,
PRE-DEFINED TIMING.
ALL ENABLE PINS
CONNECTED TO 2V2
VRTCLOW
RTC_OUT/BBAT
32kHZ
X
ALL
ENABLES
NOPOWER
NORTC
X
X
Z
TNOPOWER
TPOR=8mSec
TNORTC
6586X POWER-UP
HOST RESET , TPS6585X SEQUENCES THE INTEGRATED SUPPLIES
SEQUENCING COMPLETED
Figure 3-14. TPS658600 Controlled Startup
3.54 INTEGRATED SUPPLIES – ENABLE CONTROL, DVM CONTROL
3.54.1 DVM and Non-DVM Supplies
The TPS658600 has two types of voltage control for the integrated supplies:
1. DVM supplies: SM0, SM1, LDO2 and LDO4 are DVM supplies with dedicated register sets that enable
a controlled transition from an initial voltage to a final voltage. The initial voltage, final voltage, and
voltage transition start time are set via I2C. SM0 and SM1 have I2C programmable slew rate.
DETAILED DESCRIPTION
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2. NON-DVM supplies: LDO0, LDO1, LDO3, LDO5, LDO6, LDO7, LDO8, LDO9, SM2 and RTC_OUT
outputs can be changed, but without slew rate and transition start time control. The output of these
supplies will be changed to the new value as soon as TPS658600 sends the ACK of the I2C command
setting the new output voltage.
3.54.2 DVM and Non-DVM Supply Enable
All the integrated supplies can be turned on/off by RAM enable bits. All the supplies (with exception of
LDO5, LDO9 and RTC_OUT LDO's) have two enable bits on distinct registers (registers 0x10, 0x11, 0x12,
0x13, 0x14). A supply will be enabled when ANY of its enable bits, in the registers below, are set to 1.
Each supply will be disabled when ALL of the enable bits for that supply are set to 0. For example: SM0
enabled: SM0_ENA=1 OR SM0_ENB=1, SM0 disabled: SM0_ENA=0 AND SM0_ENB=0
Table 3-18. SM0-2, LDO0-9 Control
SUPPLYENA [Addr 0x10]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD107
RSVD106
RSVD105
RSVD104
LDO2_ENA1
LDO2_ENA0
SM0_ENA
SM1_ENA
LDO2
CONTROL
SM0
CONTROL
SM1
CONTROL
Function
NOT USED
NOT USED
NOT USED
NOT USED
LDO2
CONTROL
SUPPLYENB [Addr 0x11]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD117
RSVD116
RSVD115
RSVD114
LDO2_ENB1
LDO2_ENB0
SM0_ENB
SM1_ENB
Function
NOT USED
NOT USED
NOT USED
NOT USED
LDO2
CONTROL
LDO2
CONTROL
SM0
CONTROL
SM1
CONTROL
SUPPLYENC [Addr 0x12]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SM2_ONC
LDO8_ONC
LDO7_ONC
LDO6_ONC
LDO4_ONC
LDO3_ONC
LDO1_ONC
LDO0_ONC
Function
SM2
CONTROL
LDO8
CONTROL
LDO7
CONTROL
LDO6
CONTROL
LDO4
CONTROL
LDO3
CONTROL
LDO1
CONTROL
LDO0
CONTROL
SUPPLYEND [Addr 0x13]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SM2_OND
LDO8_OND
LDO7_OND
LDO6_OND
LDO4_OND
LDO3_OND
LDO1_OND
LDO0_OND
Function
SM2
CONTROL
LDO8
CONTROL
LDO7
CONTROL
LDO6
CONTROL
LDO4
CONTROL
LDO3
CONTROL
LDO1
CONTROL
LDO0
CONTROL
SUPPLYENE [Addr 0x14]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
LDO9_ON
LDO5_ON
SYSINEN
HOTDLY
SLEEP
MODE
SETNORMAL
EXITSLREQ
SOFT RST
Function
LDO9
ON/OFF
CONTROL
LDO5
ON/OFF
CONTROL
SYS_IN LOW
VOLTAGE
SETS SLEEP
MODE
HOT RESET
DEGLITCH
SET
TPS658600
IN SLEEP
MODE
SET
TPS658600
IN NORMAL
MODE
SLEEP
REQUEST
EXIT
CONTROL
SOFTWARE
RESET
CONTROL
When 0
OFF
OFF
DISABLED
5μsec min,
16μsec max
NOT ACTIVE
NORMAL
MODE NOT
SET
GO TO
SLEEP at
T>Twait
NOT ACTIVE
When 1
ON
ON
ENABLED
5ms
SET SLEEP
ENABLE
NORMAL
MODE
FORCE
TRANSITION
TO NORMAL
STATE
REBOOT
REQUEST
56
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LDO5 and LDO9 will be turned on when LDO5_ON is 1 or LDO9_ON is 1, respectively. The RTC_OUT
LDO enable bits are located in the RTC control register, see real time clock section for details.
The supply enable defaults are unique for each device. See App Notes for device specific settings.
3.54.3 DVM Supplies - Voltage Transition Control
The output voltage for the DVM supplies can be set to one of the values programmed in the voltage
setting registers SM0V1, SM0V2, SM1V1, SM2V2, LDO2AV1, LDO2AV2, LDO2BV1, LDO2BV2, LDO4V1
and LDO4V2 in registers VCC1 and VCC2.
The voltage change for the DVM supplies is usually done with 2 I2C write commands:
1. The host writes the new voltage to the voltage setting register for the supply(s) that will have an output
voltage modification.
2. The voltage change starts by setting specific control bits in registers VCC1 and VCC2.
Bits VS in registers VCC1 and VCC2 select the next voltage for the DVM supplies. A voltage change is
started when ANY of the GO bits for the supply is set to 1. At the end of the voltage transition the GO bits
are cleared by the internal logic.
Table 3-19. DVM Supply Control
VCC1 [Addr 0x20]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
LDO4VS
LDO4GO
LDO2AVS2
LDO2AGO2
SM0VS1
SM0GO1
SM1VS1
SM1GO1
LDO4 VOLTAGE
SELECTION
Function
LDO2 VOLTAGE SELECTION
When 0
SELECT
VOLTAGE
SET BY
LDO4V1
HOLD
CURRENT
VOLTAGE
When 1
SELECT
VOLTAGE
SET BY
LDO4V2
SM0 VOLTAGE SELECTION SM1 VOLTAGE SELECTION
NOT USED
HOLD
CURRENT
VOLTAGE
SELECT
VOLTAGE
SET BY
SM0V1
HOLD
CURRENT
VOLTAGE
SELECT
VOLTAGE
SET BY
SM1V1
HOLD
CURRENT
VOLTAGE
RAMP TO
VOLTAGE
SELECTED
BY LDO4VS
NOT USED
RAMP TO
VOLTAGE
SELECTED
BY
LDO2BVS1
SELECT
VOLTAGE
SET BY
SM0V2
RAMP TO
VOLTAGE
SELECTED
BY SM0VS1
SELECT
VOLTAGE
SET BY
SM1V2
RAMP TO
VOLTAGE
SELECTED
BY SM1VS1
VCC2 [Addr 0x21]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
LDO2BVS1
LDO2BGO1
LDO2AVS1
LDO2AGO1
SM0VS2
SM0GO2
SM1VS2
SM1GO2
LDO2 VOLTAGE
SELECTION
Function
LDO2 VOLTAGE SELECTION I SM0 VOLTAGE SELECTION SM1 VOLTAGE SELECTION
When 0
SELECT
VOLTAGE
SET BY
LDO2BV1
HOLD
CURRENT
VOLTAGE
When 1
SELECT
VOLTAGE
SET BY
LDO2BV2
RAMP TO
VOLTAGE
SELECTED
BY
LDO2BVS1
NOT USED
HOLD
CURRENT
VOLTAGE
SELECT
VOLTAGE
SET BY
SM0V1
HOLD
CURRENT
VOLTAGE
SELECT
VOLTAGE
SET BY
SM1V1
HOLD
CURRENT
VOLTAGE
NOT USED
RAMP TO
VOLTAGE
SELECTED
BY
LDO2BVS1
SELECT
VOLTAGE
SET BY
SM0V2
RAMP TO
VOLTAGE
SELECTED
BY SM0VS2
SELECT
VOLTAGE
SET BY
SM1V2
RAMP TO
VOLTAGE
SELECTED
BY SM1VS2
Table 3-20. SM0 and SM1 Voltage Selection Register Settings
SM0 OUTPUT VOLTAGE SELECTION
SM1 OUTPUT VOLTAGE SELECTION
SM0VS1
SM0VS2
SM0GO1=1 OR SM0GO2=1 STARTS
VOLTAGE TRANSITION
TO VALUE SET BY REGISTER :
SM0VS1
SM0VS2
SM1GO1=1 OR SM1GO2=1 STARTS
VOLTAGE TRANSITION
TO VALUE SET BY REGISTER
0
0
SM0V1
0
0
SM1V1
0
1
SM0V2
0
1
SM1V2
DETAILED DESCRIPTION
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Table 3-20. SM0 and SM1 Voltage Selection Register Settings (continued)
SM0 OUTPUT VOLTAGE SELECTION
SM1 OUTPUT VOLTAGE SELECTION
1
0
SM0V2
1
0
SM1V2
1
1
SM0V2
1
1
SM1V2
Table 3-21. SM0 Voltage Selection by SM0EN
SM0 ACTIVE LEVEL
SM0EN
SM0 OUTPUT VOLTAGE
0
0
1.2V
0
1
OFF
The SM0 output voltage value and transition is controlled by the SM0EN pin and SM0VS1/SMVS2.
NOTE
During a HI to LO transition of SM0EN (enabling SM0), the SM0 output will power up to
the pre-defined default state regardless of the setting set via I2C prior to SM0 being
disabled.
Table 3-22. SM0 Output Voltage Settings Available for SM0EN Selection
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
0.725V–1.50V
00000
0.725
01000
0.925
10000
1.125
11000
1.325
00001
0.750
01001
0.950
10001
1.150
11001
1.350
00010
0.775
01010
0.975
10010
1.175
11010
1.375
00011
0.800
01011
1.000
10011
1.200
11011
1.400
00100
0.825
01100
1.025
10100
1.225
11100
1.425
00101
0.850
01101
1.050
10101
1.250
11101
1.450
00110
0.875
01110
1.075
10110
1.275
11110
1.475
00111
0.900
01111
1.100
10111
1.300
11111
1.500
Table 3-23. LDO4 Voltage Selection Register Settings
LDO4 OUTPUT VOLTAGE SELECTION
LDO4VS
LDO4GO=1 STARTS VOLTAGE TRANSITION TO
VALUE SET BY REGISTER
0
LDO4V1
1
LDO4V2
The LDO2 output voltage selection and GO bit functionality is shown below.
1. LDO2AGOn bits are not active
2. LDO2BGO1=1 starts a voltage transition to the voltage selected by LDO2BV1, LDO2BV2 and
LDO2BVS1
3. LDO2 voltage transition starts when SM0EN is set to LO
When the LDO2 output voltage is controlled by the SM0EN (CORECTRL) pin, registers LDO2AV2 and
LDO2AV1 define the output voltage:
58
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3.54.4 DVM Supply Voltage Transition
During a voltage transition the output voltage will be stepped from the currently programmed voltage to the
new target voltage as shown below. The slew rate from the initial voltage to the final voltage for SM0 and
SM1 can be selected using the I2C registers SM0SL (ADDRESS = 0x25) and SM1SL (ADDRESS = 0x28)
respectively. LDO2 and LDO4 have the slew rate fixed internally to 7mV/μSec(typ).
Figure 3-15. SM0 and SM1 Dynamic Voltage Slew Rate Example
3.55 SM0, SM1, SM2 CONVERTERS
The TPS658600 has three highly efficient step down synchronous converters. The integration of the power
stage switching FETs reduces the external component count, and only the external output inductor and
filter capacitor are required. The integrated power stage supports 100% duty cycle operation. The
converters have two possible modes of operation: a 2.25MHz fixed frequency pulse width modulation
(PWM) mode at moderate to heavy loads, and a pulse frequency modulation (PFM) mode at light loads.
The converters SM0, SM1 and SM2 output voltages are programmable via I2C registers SMnV1 and
SMnV2 (SM0 and SM1) and SUPPLYV2 (SM2):
NOTE
VIN_SM0, VIN_SM1 AND VIN_SM2 PINS SHOULD ALWAYS BE EXTERNALLY
CONNECTED TO SYS PIN
3.55.1 SM0, SM1 DVM Buck Converters - Output Voltage Registers
Table 3-24. DVM Supply Voltage and Slew Rate Selection – SM0 and SM1
SM1V1 [Addr 0x23]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD237
RSVD236
RSVD235
SM1V1[4]
SM1V1[3]
SM1V1[2]
SM1V1[1]
SM1V1[0]
Function
NOT USED
NOT USED
NOT USED
B6
B5
SM1 SUPPLY OUTPUT VOLTAGE
SM1V2 [Addr 0x24]
Bit Number
B7
B4
B3
B2
B1
B0
DETAILED DESCRIPTION
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Table 3-24. DVM Supply Voltage and Slew Rate Selection – SM0 and SM1 (continued)
Bit Name
RSVD247
RSVD246
RSVD245
Function
NOT USED
NOT USED
NOT USED
B6
B5
SM1V2[4]
SM1V2[3]
SM1V2[2]
SM1V2[1]
SM1V2[0]
SM1 SUPPLY OUTPUT VOLTAGE
SM1SL [Addr 0x25]
Bit Number
B7
B4
B3
B2
SM1SL[2]
Bit Name
RSVD257
RSVD256
RSVD255
RSVD254
RSVD253
Function
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
B1
B0
SM1SL[1]
SM1SL[0]
SM1 SUPPLY RAMP RATE
SM0V1 [Addr 0x26]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD267
RSVD266
RSVD265
SM0V1[4]
SM0V1[3]
SM0V1[2]
SM0V1[1]
SM0V1[0]
Function
NOT USED
NOT USED
NOT USED
SM0 SUPPLY OUTPUT VOLTAGE
SM0V2 [Addr 0x27]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD277
RSVD276
RSVD275
SM0V2[4]
SM0V2[3]
SM0V2[2]
SM0V2[1]
SM0V2[0]
Function
NOT USED
NOT USED
NOT USED
SM0 SUPPLY OUTPUT VOLTAGE
SM0SL [Addr 0x28]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD287
RSVD286
RSVD285
RSVD284
RSVD283
SM0SL[2]
SM0SL[1]
SM0SL[0]
Function
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
SM0 SUPPLY RAMP RATE
The available output voltages and slew rates are shown below.
Table 3-25. SM0V1[4:0] / SM0V2[4:0] / Output Voltage Settings
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
0.725V–1.50V
00000
0.725
01000
0.925
10000
1.125
11000
1.325
00001
0.750
01001
0.950
10001
1.150
11001
1.350
00010
0.775
01010
0.975
10010
1.175
11010
1.375
00011
0.800
01011
1.000
10011
1.200
11011
1.400
00100
0.825
01100
1.025
10100
1.225
11100
1.425
00101
0.850
01101
1.050
10101
1.250
11101
1.450
00110
0.875
01110
1.075
10110
1.275
11110
1.475
00111
0.900
01111
1.100
10111
1.300
11111
1.500
Table 3-26. SM1V1[4:0] / SM1V2[4:0] Output Voltage Settings
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
1.45V–3.0V
00000
1.45
01000
1.85
10000
2.25
11000
2.65
00001
1.50
01001
1.90
10001
2.30
11001
2.70
00010
1.55
01010
1.95
10010
2.35
11010
2.75
00011
1.60
01011
2.00
10011
2.40
11011
2.80
00100
1.65
01100
2.05
10100
2.45
11100
2.85
00101
1.70
01101
2.10
10101
2.50
11101
2.90
00110
1.75
01110
2.15
10110
2.55
11110
2.95
00111
1.80
01111
2.20
10111
2.60
11111
3.00
Table 3-27. SM0SL[2:0] and SM1SL[2:0] Slew Rate Settings
60
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
000
INSTANTLY
001
0.11
010
0.22
011
0.44
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Table 3-27. SM0SL[2:0] and SM1SL[2:0] Slew Rate Settings (continued)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
100
0.88
101
1.76
110
3.52
111
7.04
Table 3-28. Non-DVM supply Voltage selection - SM2, LDO8
SUPPLYV2 [Addr 0x42]
Bit Number
B7
Bit Name
VLDO8[2]
Function
B6
B5
B4
B3
VLDO8[1]
VLDO8[0]
VSM2[4]
VSM2[3]
LDO8 OUTPUT VOLTAGE
B2
B1
B0
VSM2[2]
VSM2[1]
VSM2[0]
SM2 OUTPUT VOLTAGE
Table 3-29. VSM2[4:0] Output Voltage Settings
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
3.0V–4.55V
00000
3.000
01000
3.400
10000
3.800
11000
4.200
00001
3.050
01001
3.450
10001
3.850
11001
4.250
00010
3.100
01010
3.500
10010
3.900
11010
4.300
00011
3.150
01011
3.550
10011
3.950
11011
4.350
00100
3.200
01100
3.600
10100
4.000
11100
4.400
00101
3.250
01101
3.650
10101
4.050
11101
4.450
00110
3.300
01110
3.700
10110
4.100
11110
4.500
00111
3.350
01111
3.750
10111
4.150
11111
4.550
3.55.2 PWM Operation
During PWM operation the converters use a fast response voltage mode controller scheme with input
voltage feed-forward, enabling the use of small ceramic input and output capacitors. At the beginning of
each clock cycle the high side channel MOSFET switch is turned on, and the oscillator starts the voltage
ramp. The inductor current will ramp-up until the ramp voltage reaches the error amplifier output voltage,
when the comparator trips and the high-side channel MOSFET switch is turned off. Internal adaptive
break-before-make circuits turn on the integrated low-side MOSFET switch after an internal, fixed
dead-time delay, and the inductor current ramps down, until the next cycle is started. When the next cycle
starts the ramp voltage is reset to its low value and the high-side channel MOSFET switch is turned on
again.
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Figure 3-16. PWM Control
3.55.3 PFM Mode Operation
The TPS658600 SM0, SM1 and SM2 buck converters can be set to operate only in PWM mode or to
switch automatically between PFM and PWM modes, via the I2C interface. While in the Pulsed Frequency
Mode the converters operate with reduced switching frequency and with a minimum quiescent current to
maintain high efficiency.
In PFM mode the converter will regulate the output voltage to 1% above the nominal output voltage. To
determine when to transition between the modes, the inductor current is monitored, and the PFM mode is
set when the inductor ripple current approaches zero. For duty cycles above 85% the PFM mode is
entered for load currents below the threshold IPFM(ENTER).
IPFM(ENTER) =
V(VIN_SMx)
34W
(4)
In PFM mode the output voltage is monitored by a voltage comparator, which regulates the output voltage
to the programmed value VO(SM1). If the output voltage is below VO(SM1) the PFM control circuit turns on the
power stage, applying a burst of pulses to increase the output voltage. When the output voltage exceeds
the target regulation voltage VO(SM1) the power stage is disabled, and the output voltage will drop until it is
below the regulation voltage target, when the power stage is enabled again.
The PFM operation is disabled and PWM operation set if one of the following events happens during PFM
operation:
1. The burst operation exceeds 7μs, typ.
2. The output voltage falls below 3% of the target regulation voltage in PFM mode (2% of the nominal
output voltage in PWM mode)
3.55.4 Setting the PWM/PFM Mode
In TPS658600 the PWM mode can be forced for each converter by setting the bit SMn_PWM to 1 in the
SMODE1 register. If bits SMn_GPIO is 1, the GPIO will control the PWM or PFM mode setting, and bits
SMn_PWM are ignored.
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Table 3-30. SM0,SM1, SM2 PWM/PFM Mode Selection
SMODE1 [Addr 0x47]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD477
SM2_GPIO
SM1_GPIO
SM0_GPIO
RSVD473
SM2_PWM
SM1_PWM
SM0_PWM
Function
SPARE
SM2 AUTO
PFM
CONTROL
SELECTION
SM1 AUTO
PFM
CONTROL
SELECTION
SM0 AUTO
PFM
CONTROL
SELECTION
SPARE
SM2 PWM
MODE ON
SM1 PWM
MODE ON
SM0 PWM
MODE ON
Table 3-31 details how the GPIO control is implemented. Note that the GPIO1 polarity indicated in
Table 3-31 is controlled by bit GPIOINV, register 0x5E.
Table 3-31. GPIO1 PWM/PFM Mode Control
SMx_GPIO
SMx_PWM
GPIO1 POLARITY
GPIO1
CONVERTER MODE
0
0
x
x
Auto PWM/PFM
0
1
x
x
PWM Only
1
x
Inverted
0
PWM Only
1
x
Inverted
1
Auto PWM/PFM
1
x
Not Inverted
0
Auto PWM/PFM
1
x
Not Inverted
1
PWM Only
3.55.5 Output Discharge Switches
When the SM0, SM1 and SM2 converters are disabled, an integrated switch automatically discharges the
converter output capacitor.
The converter output discharge switches are always enabled when NORMAL state is set and during the
SUPPLYSEQ state.
3.55.6 Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It
provides more headroom for both the voltage drop at a load step and the voltage increase at a load
throw-off. This improves load transient behavior.
At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1%
higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage
will drop until it reaches the COMP LOW threshold set to 2% below the nominal value and enters PWM
mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to
active regulation turning on the low-side channel switch.
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Figure 3-17. Voltage Positioning
3.55.7 Soft Start
SM0, SM1 and SM2 have an internal soft start circuit that limits the inrush current during start-up. An initial
delay (170µs typ) from the converter enabled command to the converter effectively being operational is
required to ensure that the internal circuits of the converter are properly biased. At the end of that initial
delay the soft start is initiated and the internal compensation capacitor is charged with a low value current
source. The soft start time is typically 250µs, with the output voltage ramping from 5% to 95% of the final
target value.
3.55.8 Dropout Operation at 100% Duty Cycle
The TPS658600 buck converters offer a low input to output voltage difference while still maintaining
operation when the duty cycle is set to 100%. In this mode of operation the high-side FET is constantly
turned on to enable operation with a low input voltage. The dropout operation will start if :
V(VIN_SMx) ≤ V(SMx) + ILx × ®DSON(PSMx) + RL)
where ILx is the output current plus ½ inductor ripple current and RL is the DC resistance of the inductor.
3.55.9 Output Voltage Monitoring
The output voltage of converters SM0, SM1 and SM2 is monitored by internal comparators, and an output
low voltage condition is detected when the output voltage is below 90% of the programmed value. The
power good comparator is disabled for all converters during output voltage transitions. The power
comparator on SM2 power good is also disabled when battery tracking mode is set.
3.55.10 Phase Control in PWM Mode
By default the SM0, SM1 and SM2 converters operate with phased clocking when they are in PWM mode,
with converter SM0 as the master. Converters SM0 and SM1, when enabled, will run 90 and 180 degrees
out of phase with SM0.
3.55.11 Integrated Snubber and Current Limit
The SM2 converter has an integrated electronic snubber that is used to improve transient response when
operating under conditions which cause the inductor current to flow in the negative direction (into the Ln
node) . This is especially true when SM2 is configured as the pre-regulator stage to the charger.
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3.56 LINEAR REGULATORS
The TPS658600 offers ten integrated linear dropout regulators (LDOs), designed to be stable over the
operating load range with use of external ceramic capacitors. The output voltage can be programmed via
I2C. All of the LDOs, with the exception of LDO5 and RTC_OUT LDO, have uncommitted input power
supply pins (VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9) which should be externally
connected to a number of system rails including SYS and the output of SM2.
The LDO5 and RTC_OUT regulators are internally connected to the SYS pin.
3.56.1 Output Voltage Monitoring
Internal power good comparators monitor the LDO outputs and detect when the output voltage is below
95% of the programmed value. This information is used by the TPS658600 to generate interrupts or to
trigger distinct operating modes, depending on specific I2C register settings. See interrupt and sequencing
controller section for additional details.
3.56.2 LDO2 DVM LDO - Output Voltage Registers
Registers 0x29, 0x2A, 0x2F and 0x30 set the output voltage for LDO2. The slew rate is internally fixed to
7mV/μSec (typ).
Table 3-32. DVM Supply Voltage Selection – LDO2
LDO2AV1 [Addr 0x29]
Bit Number
B7
Defaults in BOLD
B6
B5
B4
LDO2AV1[4]
Bit Name
RSVD297
RSVD296
RSVD295
Function
NOT USED
NOT USED
NOT USED
B3
B2
B1
B0
LDO2AV1[3]
LDO2AV1[2]
LDO2AV1[1]
LDO2AV1[0]
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-33)
SM1V2 [Addr 0x24]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD2A7
RSVD2A6
RSVD2A5
LDO2AV2[4]
LDO2AV2[3]
LDO2AV2[2]
LDO2AV2[1]
LDO2AV2[0]
Function
NOT USED
NOT USED
NOT USED
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-33)
LDO2BV1 [Addr 0x2F]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD2F7
RSVD2F6
RSVD2F5
LDO2BV1[4]
LDO2BV1[3]
LDO2BV1[2]
LDO2BV1[1]
LDO2BV1[0]
Function
NOT USED
NOT USED
NOT USED
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-33)
LDO2BV2 [Addr 0x30]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD307
RSVD306
RSVD305
LDO2BV2[4]
LDO2BV2[3]
LDO2BV2[2]
LDO2BV2[1]
LDO2BV2[0]
Function
NOT USED
NOT USED
NOT USED
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-33)
The available output voltages for LDO2 are shown below:
Table 3-33. LDO2AV1/2[4:0] and LDO2BV1/2[4:0] Settings
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
0.725V–1.50V
00000
0.725
01000
0.925
10000
1.125
11000
1.325
00001
0.750
01001
0.950
10001
1.150
11001
1.350
00010
0.775
01010
0.975
10010
1.175
11010
1.375
00011
0.800
01011
1.000
10011
1.200
11011
1.400
00100
0.825
01100
1.025
10100
1.225
11100
1.425
00101
0.850
01101
1.050
10101
1.250
11101
1.450
00110
0.875
01110
1.075
10110
1.275
11110
1.475
00111
0.900
01111
1.100
10111
1.300
11111
1.500
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3.56.3 LDO4 DVM LDO – Output Voltage Registers
Registers 0x32 and 0x33 set the output voltage for LDO4. The slew rate is internally fixed to 7mV/μSec
(typ).
Table 3-34. DVM Supply Voltage Selection – LDO4
LDO4V1 [Addr 0x32]
Bit Number
B7
B6
B5
B4
LDO4V1[4]
Bit Name
RSVD327
RSVD326
RSVD325
Function
NOT USED
NOT USED
NOT USED
B3
B2
B1
B0
LDO4V1[3]
LDO4V1[2]
LDO4V1[1]
LDO4V1[0]
LDO4 SUPPLY OUTPUT VOLTAGE (See Table 3-35)
LDO4V2 [Addr 0x33]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD337
RSVD336
RSVD335
LDO4V2[4]
LDO4V2[3]
LDO4V2[2]
LDO4V2[1]
LDO4V2[0]
Function
NOT USED
NOT USED
NOT USED
LDO4 SUPPLY OUTPUT VOLTAGE (See Table 3-35)
The available output voltages are shown below:
Table 3-35. LDO4V1[4:0] and LDO4V2[4:0] Output Voltage Settings
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
1.7V–2.475V
00000
1.700
01000
1.900
10000
2.100
11000
2.300
00001
1.725
01001
1.925
10001
2.125
11001
2.325
00010
1.750
01010
1.950
10010
2.150
11010
2.350
00011
1.775
01011
1.975
10011
2.175
11011
2.375
00100
1.800
01100
2.000
10100
2.200
11100
2.400
00101
1.825
01101
2.025
10101
2.225
11101
2.425
00110
1.850
01110
2.050
10110
2.250
11110
2.450
00111
1.875
01111
2.075
10111
2.275
11111
2.475
3.56.4 LDO Output Discharge Switches
All LDO's, with exception of RTC_OUT LDO, have internal discharge resistors that are connected to
ground via internal switches when the LDO is turned OFF, thus discharging the output capacitor.
The LDO output discharge switches are always enabled when NORMAL state is set and during the
SUPPLYSEQ state.
3.56.5 Non-DVM Supply Voltage Settings
Registers SUPPLYV1, SUPPLYV2, SUPPLYV3, SUPPLYV4 and SUPPLYV6 define the voltage settings
for the non-DVM supplies.
Register SUPPLYV4 has two bits that control the RTC_OUT LDO functionality. The RTC_OUT LDO will
be enabled when LDORTC_ON is 1. The power good threshold for the RTC_OUT LDO can be set as
follows: 2.4V (RTC_PGOOD is 1), 2.0V (RTC_PGOOD is 0).
Table 3-36. Non-DVM Supply Voltage Selection
SUPPLYV1 [Addr 0x41]
Bit Name
Function
VLDO0[2]
VLDO0[1]
VLDO0[0]
VLDO1[4]
LDO0 OUTPUT VOLTAGE (See Table 3-38)
VLDO1[3]
VLDO1[2]
VLDO1[1]
VLDO1[0]
LDO1 OUTPUT VOLTAGE (See Table 3-37)
SUPPLYV3 [Addr 0x43]
66
Bit Name
LDO7_SW
LDO6_SW
Function
SPARE
SPARE
VLDO7[2]
VLDO7[1]
VLDO7[0]
LDO7 OUTPUT VOLTAGE (See Table 3-38)
DETAILED DESCRIPTION
VLDO6[2]
VLDO6[1]
VLDO6[0]
LDO6 OUTPUT VOLTAGE (See Table 3-38)
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Table 3-36. Non-DVM Supply Voltage Selection (continued)
SUPPLYV4 [Addr 0x44]
Bit Name
LDORTC_ON
RTC_PGOOD
Function
RTC_LDO
ON/OFF
CONTROL
RTC_OUT
LOW
VOLTAGE
THRESHOLD
VRTC[2]
VRTC[1]
VRTC[0]
RTC OUTPUT VOLTAGE (See Table 3-38)
VLDO3[2]
VLDO3[1]
VLDO3[0]
LDO3 OUTPUT VOLTAGE (See Table 3-38)
SUPPLYV6 [Addr 0x46]
Bit Name
RSVD467
RSVD466
Function
NOT USED
NOT USED
VLDO9[2]
VLDO9[1]
VLDO9[0]
LDO9 OUTPUT VOLTAGE (See Table 3-38)
VLDO5[2]
VLDO5[1]
VLDO5[0]
LDO5 OUTPUT VOLTAGE (See Table 3-38)
The available output voltages for the non-DVM supplies are shown below:
Table 3-37. VLDO1[4:0] Settings
RANGE
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
[4:0]
VOUT (V)
0.725V–1.50V
00000
0.725
01000
0.925
10000
1.125
11000
1.325
00001
0.750
01001
0.950
10001
1.150
11001
1.350
00010
0.775
01010
0.975
10010
1.175
11010
1.375
00011
0.800
01011
1.000
10011
1.200
11011
1.400
00100
0.825
01100
1.025
10100
1.225
11100
1.425
00101
0.850
01101
1.050
10101
1.250
11101
1.450
00110
0.875
01110
1.075
10110
1.275
11110
1.475
00111
0.900
01111
1.100
10111
1.300
11111
1.500
Table 3-38. VLDO3/5/6/7/8/9[2:0] and VRTC[2:0] Settings
VLDOx[2:0]
VOUT (V)
VLDOx[2:0]
VOUT (V)
000
1.25
100
2.70
001
1.50
101
2.85
010
1.80
110
3.10
011
2.50
111
3.30
Table 3-39. VLDO0[2:0] and VRTC[2:0] Settings
VLDOx[2:0]
VOUT (V)
VLDOx[2:0]
VOUT (V)
000
1.20
100
2.70
001
1.50
101
2.85
010
1.80
110
3.10
011
2.50
111
3.30
Setting the RTC_OUT output voltage below the RTC_OUT power good threshold will result in a NORTC
pulse always being generated during the reboot cycle or when exiting sleep. Setting the RTC_OUT output
voltage below VUVLO_RTC disables the use of the internal real time clock counter and xtal oscillator.
3.57 BOOST CONVERTER
The TPS658600 has an integrated boost converter (SM3) that is optimized to drive white LED’s connected
in a series configuration. Up to six series white LED’s can be driven, with programmable current and duty
cycle adjustable via a dedicated I2C register.
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The SM3 boost Converter (SM3) has a 29v, 500mA low side integrated power stage switch, which drives
the external inductor. Another integrated 29V, 25mA switch (LED switch) is used to modulate the external
white LED’s brightness.
Figure 3-18. Boost Converter Block Diagram
The SM3 boost converter operates in a pulse frequency modulation (PFM) scheme with constant peak
current control. This control scheme maintains high efficiency over the entire load current range and
enables the use of small external components, as the switching frequency can reach up to 1 MHz
depending on the load conditions. The LED current ripple is defined by the external inductor size.
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The converter monitors the sense voltage at pin FB3, and turns on the integrated power stage switch
when V(FB3) is below the 250mV (typ) internal reference voltage. The integrated power switch turns off
when the inductor current reaches the internal peak current limit or if the switch is on for a period longer
than the maximum on-time of 6 μs (typ).
As the integrated power switch is turned off the external Schottky diode is forward biased, delivering the
stored inductor energy to the output. The main switch remains off until the FB3 pin voltage is below the
internal 250mV reference voltage, when it is turned on again.
This PFM peak current control sets the converter in discontinuous conduction mode (DCM), and the
switching frequency depends on the inductor, input/output voltage and LED current. Lower LED currents
reduce the switching frequency, with high efficiency over the entire LED current range. This regulation
scheme is inherently stable, allowing a wide range for the selection of the inductor and output capacitor.
3.57.1 SM3 RAM Registers
Table 3-40. SM3 Control
SM3_SET0 [Addr 0x57]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SM3_SET7
SM3_SET6
SM3_SET5
SM3_SET4
SM3_SET3
SM3_SET2
SM3_SET1
SM3_SET0
ADD 0.048%
Function
SM3 PWM SWITCH DUTY CYCLE
When 0
When 1
ADD 0 TO DUTY CYCLE
ADD 6.25%
ADD 3.125%
ADD 1.5625%
ADD 0.78125%
ADD 0.390%
ADD 0.195%
ADD 0.0976%
SM3_SET1 [Addr 0x58]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SM3SOFTOFF
SM3_ILIM
SM3_PRESC1
SM3_PRESC0
SM3_IGAIN
SM3_SET10
SM3_SET9
SM3_SET8
Function
SOFTSTART
ENABLE
SM3
CURRENT
LIMIT
SM3PWM
REPETITION
RATE[1]
SM3PWM
REPETITION
RATE[0]
ISM3G
OUTPUTBUFF
ER MODE
SM3 PWM DUTY CYCLE
When 0
ENABLED
300 mA
SEE SM3 PWM REPETITION
TABLE
Hi-Z
ADD 0 TO DUTY CYCLE
When 1
DISABLED
500 mA
SEE SM3 PWM REPETITION
TABLE
LO
ADD 50%
ADD 25%
ADD 12.5%
Table 3-41. SM3 PWM Repetition Settings
SM3PRESC[1]
SM3PRESC[0]
REPETITION RATE (Hz)
0
0
550
0
1
366
1
0
275
1
1
220
The internal LED switch, in series with the external LED’s, disconnects the LEDs from ground during
shutdown. In addition, the LED switch is driven by a PWM signal generated internally, enabling adjusting
the average LED current by setting the LED switch duty cycle. The duty cycle is adjusted with control bits
SM3_SET, on register SM3_SET0. With this control method the LED brightness depends on the LED
switch duty cycle only and is independent of the boost converter operating frequency. The duty cycle
control used in the SM3 converter LED switch is implemented by a single PWM pulse with a fixed
repetition rate. An example of distinct duty cycles is shown IN Figure 3-19
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Figure 3-19. SM3 Duty Cycle Example
The repetition period can be set using control bits SM3_PRESCn in the register SM3_SET1 to either
220/275/366/550 Hz (HI). Each repetition period has a total of 2048 steps, enabling a resolution of 0.05%
when programming the duty cycle.
3.57.2 Peak Current Control (Boost Converter)
The SM3 integrated power stage switch is turned on until the inductor current reaches the DC current limit
IMAX(L3) (500 mA or 300mA, typ), selectable via bit SM3_ILIM , register SM3_SET1. Due to internal delays,
typically around 100ns, the actual current exceeds the DC current limit threshold by a small amount. The
typical peak current limit can be calculated as follows:
IP(typ) = IMAX(L3) +
VSM3
´ 100 ns
L
(6)
The peak current will be directly proportional to the input voltage and inversely proportional to the inductor
value. The internal current limit may be set to either 300mA or 500mA via I2C.
Note that under PWM operation the slew rate of the converter output (SM3) is dependent of the IMAX(L3)
value selected.
3.57.3 Soft Start
All inductive step-up converters exhibit high in-rush current during start-up. If no special precautions are
taken voltage drops can be observed at the input supply rail during start-up, with unpredictable results in
the overall system operation.
The SM3 boost converter limits the inrush current during start-up by increasing the current limit in two
steps, starting from IMAX(L3) /4 for 256 power stage switch cycles (1cycle=power stage switch
OFF→ON→OFF) to IMAX(L3) /2 for the next 256 power stage switch cycles and then full current limit
IMAX(L3). The softstart function can be disabled via control bit SM3SOFTOFF, in register SM3_SET1.
3.57.4 Enabling the SM3 Converter
The converter is enabled when an I2C command sets the duty cycle to a value different than zero.
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3.57.5 Overvoltage Protection
The output voltage of the boost converter is sensed at pin SM3, and the integrated power stage switch is
turned OFF when V(SM3) exceeds the internal over-voltage threshold V(OVP3). The converter returns to
normal operation when V(SM3) < V(OVP3) – VHYS(OVP3).
3.57.6 Under Voltage Lockout Operation
The power stage mosfet switch and the LED switch are open (off) when the TPS658600 enters the sleep
mode or if the SM3 converter is set to OFF mode.
3.57.7 SM3 Output Current - High and Low Current Settings
A dedicated, open-drain pin (ISM3G) enables I2C selection of a low and high brightness setting for the
SM3 output current, by modifying the external FB3 resistor value. See application diagram for details. This
pin is configured as an open drain and it can be turned on/off with bit SM3_IGAIN on register SM3_SET1.
3.58 RGB AND PWM DRIVERS
The TPS658600 has integrated open drain and push-pull drivers with programmable duty cycle and
frequency, targeted at driving external RGB drivers, keyboard LED's, vibrator motor and other system
peripherals.
Figure 3-20. RGB and PWM Driver Blocks
3.58.1 PWM Pin Driver
The TPS658600 offers one high current (150mA max) open-drain PWM driver. The PWM driver is enabled
when PWM_EN is 1 in register PWM.
Table 3-42. PWM Control
PWM [Addr 0x5B]
Bit
Number
Default to 0
B7
B6
B5
B4
B3
Bit Name
PWM_EN
PWM_F[2]
PWM_F[1]
PWM_F[0]
PWM_D[3]
Function
PWM DRIVER ON/OFF
PWM DRIVER FREQUENCY
B2
B1
B0
PWM_D[2]
PWM_D[1]
PWM_D[0]
PWM DRIVER DUTY CYCLE
DETAILED DESCRIPTION
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The PWM frequency and duty cycle are defined by the PWM register settings as shown below.
Table 3-43. PWM Settings
PWM_F[2:0)
FREQUENCY(kHz)
PWM_D[3:0]
DUTY CYCLE (%)
PWM_D[3:0]
DUTY CYCLE (%)
000
23.4
0000
6.25
1000
56.25
001
11.7
0001
12.5
1001
62.5
010
6.7
0010
18.75
1010
68.75
011
4.5
0011
25
1011
75
100
3.0
0100
31.25
1100
81.25
101
2.3
0101
37.5
1101
87.5
110
1.5
0110
43.75
1110
93.75
111
0.75
0111
50
1111
100
3.58.2 DIG_PWM, DIG_PWM2 Drivers
The TPS658600 provides two push-pull outputs with programmable duty cycle at pins DIGPWM and
DIGPWM2. The DIG_PWM register controls the DIGPWM pin duty cycle, register DIG_PWM2 controls the
DIGPWM2 pin duty cycle. The DIG_PWM functions and register bit controls detailed below apply to the
DIGPWM2 pin and DIG_PWM2 register as well. Both registers default to 0x00 upon power-up.
Table 3-44. DIGPWM, DIGPWM2 Control
DIG_PWM [Addr 0x5A]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
DPWM_MODE
DPWM_SET[6]
DPWM_SET[5]
DPWM_SET[4]
DPWM_SET[3]
DPWM_SET[2]
DPWM_SET[1]
DPWM_SET[0]
DIG_PWM2 [Addr 0x5C]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
DPWM2_MODE
DPWM2_SET[6]
DPWM2_SET[5]
DPWM2_SET[4]
DPWM2_SET[3]
DPWM2_SET[2]
DPWM2_SET[1]
DPWM2_SET[0]
Mode 0 (DPWM_MODE is 0): The pulse width modulated output is a single PWM pulse of the selected
duty cycle, with a nominal 250Hz repetition rate. The DIG_PWM register bits [6:0] sets the pulse width
value as shown below:
TON (ms) =
DPWM_SET[6:0]
, if DPWM_SET[6:0] £ 126
32
(7)
TON(ms) = Always On, if DPWM_SET[6:0] = 127)
Mode 1 (DPWM_MODE is 1): The bit DPWMx_SET[6] of the DIG_PWMx register selects the pulse time
range, bits DIG_PWMx[5:3] set the ON times and bits DIG_PWMx[2:0] set the off times.
Table 3-45. Digital PWM Settings, DPWM_MODE=1
DPWMx_SET[ 6] = 0
72
DPWMx_SET[ 6] = 1
DIG_PWMx[5:3]
ON TIME (µs)
DIG_PWMx[2:0]
OFF TIME
(ms)
000
31
000
0.49
000
5
000
40
001
61
001
1.01
001
10
001
60
010
92
010
1.50
010
15
010
80
011
122
011
2.01
011
20
011
100
100
153
100
2.50
100
30
100
120
101
183
101
2.99
101
40
101
140
110
214
110
4.00
110
50
110
160
111
244
111
5.00
111
60
111
180
DIG_PWMx[5:3]
DETAILED DESCRIPTION
ON TIME
(ms)
DIG_PWMx[2:0]
OFF TIME (ms)
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3.58.3 LED_PWM Driver
The LED PWM open drain pin has the duty cycle set by a pulse width modulation circuit. The LED_SET
register bits (7:0) set the pulse width value in 256 steps. The pulse width modulated output is not a single
pulse of the selected duty cycle but a collection of semi-equally spaced pulses that sum to the required
duty cycle, with repetition rate of 125Hz (typ)
Table 3-46. LEDPWM Control
LED_PWM [Addr 0x59]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
LED_SET[7]
LED_SET[6]
LED_SET[5]
LED_SET[4]
LED_SET[3]
LED_SET[2]
LED_SET[1]
LED_SET[0]
TON (ms) =
LED_SET[7:0]
, if LED_SET[7:0] £ 254
32
(9)
TON(ms) = Always On, if LED_SET[7:0] = 255
3.58.4 RGB Drivers
The TPS658600 has two dedicated drivers for RGB external LED's. Three outputs are available for each
driver (pins REDn, GREENn, BLUEn), with I2C selection of operation mode and LED current.
3.58.5 RGB1 Driver
The RGB1 driver is enabled when RGB1_EN=HI, in RGB1_GREEN register. Each RGB1 pin (RED1,
GREEN1 or BLUE1) will sink the current selected by RGB1_ISET[1:0], RGB1_RED register.
The RGB1 driver can be set in a flashing mode, the flash operation parameters are configured in register
RGB1FLASH. During the flashing ON time the duty cycle for each driver can be set individually using
control bits PWMIR[4:0], PWMIG[4:0] and PWMIB[4:0] on registers RGB1_RED, RGB1_GREEN and
RGB1_BLUE. The modulated output is not a single pulse of the selected duty cycle but a collection of
semi-equally spaced pulses that sum to the required duty cycle, with repetition rate of 160Hz (typ). The
start of 1 of the modulated pulses on RGB1 can be phased by 200 μs from the others so that for duty
cycles below 50% the ON times of 2 of the LEDs will not overlap. When RGB1_PHASE is 0
(RGB1_GREEN[6]), the Red and Blue are drivers are in phase and Green is out of phase. For
RGB1_PHASE is 1 the Red and Green are in phase and Blue is out of phase.
Table 3-47. RGB1 Control
RGB1FLASH [Addr 0x50]
Default is 0
Bit Number
B7
B6
B5
B4
B3
Bit Name
RSVD507
FLASH1_ON[2]
FLASH1_ON[1]
FLASH1_ON[0]
FLASH1_PER[3]
Function
SPARE
RGB1 RED/BLUE/GREEN FLASHING ON-TIME
B2
B1
B0
FLASH1_PER[2]
FLASH1_PER[1]
FLASH1_PER[0]
RGB1 RED/BLUE/GREEN FLASHING PERIOD
RGB1RED [Addr 0x51]
Default is 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD517
RGB1_ISET[1]
RGB1_ISET[0]
PWM1R[4]
PWM1R[3]
PWM1R[2]
PWM1R[1]
PWM1R[0]
Function
NOT USED
RGB1 RED/BLUE/GREEN DRIVER
CURRENT SINK
RGB1 RED DRIVER INTENSITY CONTROL
RGB1GREEN [Addr 0x52]
Bit Number
Default is 0
B7
B6
B5
B4
B3
B2
B1
B0
PWM1G[4]
PWM1G[3]
PWM1G[2]
PWM1G[1]
PWM1G[0]
Bit Name
RGB1_EN
RGB1_PHASE
RSVD535
Function
RGB1 DRIVERS
ON/OFF
CONTROL
DRIVER ON TIME
PHASE CONTROL
NOT USED
B6
B5
B4
B3
B2
B1
B0
PWM1B[4]
PWM1B[3]
PWM1B[2]
PWM1B[1]
PWM1B[0]
RGB1 GREEN DRIVER INTENSITY CONTROL
RGB1BLUE [Addr 0x53]
Bit Number
Default is 0
B7
Bit Name
RSVD537
RSVD536
RSVD535
Function
NOT USED
NOT USED
NOT USED
RGB1 BLUE DRIVER INTENSITY CONTROL
DETAILED DESCRIPTION
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Table 3-48. RGB1 Sink Current Settings
RGB1_ISET[1:0]
RGB1 SINK CURRENT (mA)
00
0
01
3.7
10
7.4
11
11.1
Table 3-49. FLASH1_ON Settings
FLASH1_ON[2:0]
FLASH ON TIME (s)
000
0.10
001
0.15
010
0.20
011
0.25
100
0.30
101
0.40
110
0.50
111
0.60
Table 3-50. FLASH1_PER Settings
FLASH1_PER[3:0]
FLASH PERIOD (s)
FLASH1_PER[3:0]
FLASH PERIOD (s)
0000
1.0
1000
5.0
0001
1.5
1001
5.5
0010
2.0
1010
6.0
0011
2.5
1011
6.5
0100
3.0
1100
7.0
0101
3.5
1101
7.5
0110
4.0
1110
8.0
0111
4.5
1111
Always On
Equation 11 and Equation 12 indicates the duty cycle values for each driver, set with bit PWM1R[4:0],
PWM1G[4:0] and PWM1B[4:0]:
TON (ms) =
PWM1R/G/B[4:0]
, if PWM1R/G/B[4:0] £ 30
5.4
(11)
TON(ms) = Always On, if pwm1r/g/b[4:0] = 31
3.58.6 RGB2 Driver
The RGB2 driver is enabled when RGB2_EN is 1, in RGB2_GREEN register. Each RGB2 pin (RED2,
GREEN2 or BLUE2) will sink the current selected by RGB2_ISET[2:0], set in RGB2_RED register.
The RGB2 does not support a flashing mode, and will be turned on when RGB2_EN is 1. When turned
ON the duty cycle for each driver can be set individually using control bits PWMIR[4:0], PWMIG[4:0] and
PWMIB[4:0] on registers RGB2_RED, RGB2_GREEN and RGB2_BLUE. The modulated output is not a
single pulse of the selected duty cycle but a collection of semi-equally spaced pulses that sum to the
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required duty cycle, with repetition rate of 160Hz (typ). The start of one of the modulated pulses on RGB2
can be phased by 200 µs from the others, so that for duty cycles below 50% the ON times of 2 of the
LEDs will not overlap. When RGB2_PHASE is 0 (RGB2_GREEN[6]), the Red and Blue drivers are in
phase and Green is out of phase. When RGB2_PHASE is 1 the Red and Green are in phase and Blue is
out of phase.
Table 3-51. RGB2 Control
RGB2RED [Addr 0x54]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RGB2_ISET[2]
RGB2_ISET[1]
RGB2_ISET[0]
PWM2R[4]
PWM2R[3]
PWM2R[2]
PWM2R[1]
PWM2R[0]
Function
RGB2 RED/BLUE/GREEN DRIVER CURRENT SINK
RGB2 RED DRIVER INTENSITY CONTROL
RGB2GREEN [Addr 0x55]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RGB2_EN
RGB2_PHASE
RSVD565
PWM2G[4]
PWM2G[3]
PWM2G[2]
PWM2G[1]
PWM2G[1]
Function
RGB2 DRIVERS
ON/OFF CONTROL
RGB2 DRIVERS
ON TIME PHASE
CONTROL
SPARE
RGB2 GREEN DRIVER INTENSITY CONTROL
RGB2BLUE [Addr 0x56]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD577
RSVD576
RSVD575
PWM2B[4]
PWM2B[3]
PWM2B[2]
PWM2B[1]
PWM2B[1]
Function
NOT USED
NOT USED
NOT USED
RGB2 GREEN DRIVER INTENSITY CONTROL
Table 3-52. RGB2 Sink Current Settings
RGB2_ISET[2:0]
RGB2 SINK CURRENT (mA)
000
0
001
3.7
010
7.4
011
11.1
100
14.9
101
18.6
110
23.2
111
27.3
The on time for each driver, set with bits PWM2R[4:0], PWM2G[4:0] and PWM2B[4:0], is set by the
equations:
TON (ms) =
PWM2R/G/B[4:0]
, if PWM2R/G/B[4:0] £ 30
5.4
(13)
TON(ms) = Always On, if PWM2R/G/B[4:0] = 31
3.59 REAL TIME CLOCK
The TPS658600 has an integrated real time clock circuit that maintains an accurate timer/counter register
under all potential operating conditions (AC power input, USB power input, main battery power, backup
coincell / SuperCap power source, or any combination of the above). The internal oscillator for the RTC
can be driven by an external 32.768 kHz crystal. The TPS658600 has also been design with integrated,
I2C selectable, capacitors which can be used with the external 32.768 kHz crystal such that a wide range
of commercial crystals can be used without the need for external load capacitors.
DETAILED DESCRIPTION
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VRTC_OUT
POR
RESET RTC RAM
32K CLOCK
SELECTION
PRESCALER
XTAL2
I2C
Cd0
7pF
Cd1
12pF
40-BIT COUNTER
(RAW RTC DATA)
I2C
RTC
RAM
STANDARD
I2C ONLY
ALARM
DETECTION
LOGIC
XTAL1
Cg0
7pF
Cg1
12pF
ALARM2
ALARM1
V32K
SEQUENCER
INTERRUPT
CONTROLLER
OUT32K
EN
Figure 3-21. Simplified RTC Block
The following functions are provided:
• A 40-bit counter, driven by a low-power 32 kHz oscillator
• The 32 kHz oscillator can be switched using I2C, RTC_CTRL Register bit 6 (OSC_SRC_SEL),
between the TPS658600 internal (RC) oscillator source and the crystal driven oscillator source.
• Externally biased buffer to supply the crystal driven oscillator to an external device via the OUT32K
pin.
• Selectable pre-scaler divides the raw (32KHz) oscillator output, enabling clocking the RTC counter at
1.024 kHz or 32 kHz
• A 24-bit alarm register (ALARM1)
• A 16-bit alarm register (ALARM2)
The RTC registers are accessible only via the I2C bus. When an I2C read access is in progress, the RTC
counter update is postponed. At the end of the I2C read access, the accumulated missing counts are
added to the RTC counter.
NOTE
The RTC registers (0xC0-0xCA) ARE NOT reset when the TPS658600 is in the POWER
DOWN or SLEEP STATE as long as V(RTC_OUT) is greater than VUVLO_RTC . All the RTC
registers will be reset to their default settings, independent of the TPS658600 state, when
V(RTC_OUT) is less than VUVLO_RTC.
The host software must read all five RTC counter bytes when accessing the RTC counter data, as the
counter update is postponed starting at the first I2C byte read of a sequential I2C read of the five
RTC_COUNT bytes and negated on the fifth I2C byte read.
To assure proper operation of the RTC counter the following steps should always be followed:
1. The I2C address pointer must not be left pointing in the range 0xC6 to 0xCA
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2. The maximum time for the address pointer to be in this range is 1 ms
3. Always read RTC_ALARM2 in the following order to prevent the address pointer from stopping at
0xC6: RTC_ALARM2_LO, then RTC_ALARM2_HI
When the RTC_OUT voltage falls below the internal RTC circuit Power On Reset threshold, VUVLO_RTC,
the RTC_CTRL register is reset. The host can identify this situation by reading the bit, POR_RESET_N,
which will be 0.
The clock selection is controlled by OSC_SRC_SEL (RTC_CTRL [6]). The internal 32kHz oscillator is
connected to the RTC when the OSC_SRC_SEL bit is reset. Once the processor is running, the software
can set this bit to 1, thereby connecting the 32.768 kHz crystal oscillator clock to the RTC. After being set,
the OSC_SRC_SEL bit will remain 1 selecting the crystal oscillator clock, as long as the VRTC_OUT
voltage remains above the RTC_OUT Power On Reset threshold. POR_RESET_N=HI when
OSC_SRC_SEL is set HI, indicating to the host that the crystal clock is being delivered to the RTC.
The RTC_ENABLE (RTC_CTRL [5]) bit is cleared to 0 by the RTC_OUT Power On Reset, disabling the
RTC counter. To enable incrementing of the RTC_COUNT [39:0] from an initial value set by the host, the
RTC_ENABLE bit should be written to 1 only after the RTC_OUT voltage reaches the operating range.
The RTC_ENABLE bit must be cleared to 0 before any new value is written to the RTC_COUNT register.
Table 3-53. RTC Control (1)
RTC_CTRL [Addr 0xC0]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
POR_RESET_N
OSC_SRC_SEL
RTC_ENABLE
BUF_ENABLE
PRE_BYPASS
CL_SEL[1]
CL_SEL[0]
RSVDC00
Function
RESET RTC
COUNTER
32K CLOCK
SELECTION
RTC COUNTER
CLOCK AND
ALARM1/2
32KHZ BUFFER
ENABLE
RTC COUNTER
SCALING
INTERNAL XTAL1,
XTAL2
PIN
CAPACITANCE
RTC_ALARM2
DETECTION
EXITS SLEEP
When 0
RESET RTC
COUNTER
INTERNAL 32K
DISABLED
DISABLED
USE 32K/32
SEE CL_SEL SETTINGS TABLE
DISABLED
When 1
OSC_SRC_SEL BIT =
1
CRYSTAL 32K
ENABLED
ENABLED
USE 32K
SEE CL_SEL SETTINGS TABLE
ENABLED
(1)
B7 is READ ONLY, all other bits have Read/Write access
The selected 32KHz clock is applied to a prescaler that can divide it by 32, resulting in a timer tick
resolution of either 32,768 ticks per second (pre-scaler disabled, PRE_BYPASS is 1) or 1,024 ticks per
second (pre-scaler enabled, PRE_BYPASS is 0). The 32,768 Hz or 1024 Hz clock increments a 40 bit
counter that tracks the real time and which can be read at anytime via I2C. With the prescaler enabled, the
RTC count has a range of approximately 34 years. The RTC counter and alarm registers are shown
below, the 40 bit RTC Counter is cleared only on when RTC_OUT is below the UVLO threshold.
Table 3-54. RTC Counter
RTC_COUNT4 [Addr 0xC6]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RTC[39]
RTC[38]
RTC[37]
RTC[36]
RTC[35]
RTC[34]
RTC[33]
RTC[32]
RTC_COUNT3 [Addr 0xC7]
Bit Name
RTC[31]
Default to 0
RTC[30]
RTC[29]
RTC[28]
RTC[27]
RTC[26]
RTC[25]
RTC_COUNT2 [Addr 0xC8]
Bit Name
RTC[23]
RTC[22]
RTC[21]
RTC[20]
RTC[19]
RTC[18]
RTC[17]
RTC_COUNT1 [Addr 0xC9]
Bit Name
RTC[15]
RTC[7]
RTC[16]
Default to 0
RTC[14]
RTC[13]
RTC[12]
RTC[11]
RTC[10]
RTC[9]
RTC_COUNT0 [Addr 0xCA]
Bit Name
RTC[24]
Default to 0
RTC[8]
Default to 0
RTC[6]
RTC[5]
RTC[4]
RTC[3]
RTC[2]
RTC[1]
RTC[0]
DETAILED DESCRIPTION
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The alarm logic compares the RTC_ALARM1 register bits to the RTC_COUNT registers as follows:
With prescaler enabled: ALM1[23:0] is compared to RTC[23:0]
With prescaler disabled: ALM1[23:0] is compared to RTC[28:5]
An interrupt is sent to the host (if enabled via I2C, see interrupt controller section) when the alarm logic
detects that the RTC_COUNT value is equal to the pre-programmed ALARM1 register value.
The alarm logic compares the RTC_ALARM2 register bits to the RTC_COUNT registers as follows:
With prescaler enabled: ALM2[23:0] is compared to RTC[22:7]
With prescaler disabled: ALM2[15:0] is compared to RTC[27:12]
An interrupt is sent to the host (if enabled via I2C, see interrupt controller section) and the sleep mode
ends when the alarm logic detects that the RTC_COUNT value is equal to the pre-programmed ALARM2
register value.
Table 3-55. RTC Alarm
RTC_ALARM1_HI [ADDRESS=0xC1]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ALM1[23]
ALM1[22]
ALM1[21]
ALM1[20]
ALM1[19]
ALM1[18]
ALM1[17]
ALM1[16]
ALM1[13]
ALM1[12]
ALM1[11]
ALM1[10]
ALM1[9]
RTC_ALARM1_MID [Addr 0xC2]
Bit Name
ALM1[15]
Default to 0
ALM1[14]
RTC_ALARM1_LO [Addr 0xC3]
Bit Name
ALM1[7]
ALM1[6]
ALM1[5]
ALM1[4]
ALM1[3]
ALM1[2]
ALM1[1]
RTC_ALARM2_HI [Addr 0xC4]
Bit Name
ALM2[15]
ALM2[7]
ALM1[0]
Default to 0
ALM2[14]
ALM2[13]
ALM2[12]
ALM2[11]
ALM2[10]
ALM2[9]
RTC_ALARM2_LO [Addr 0xC5
Bit Name
ALM1[8]
Default to 0
ALM2[8]
Default to 0
ALM2[6]
ALM2[5]
ALM2[4]
ALM2[3]
ALM2[2]
ALM2[1]
ALM2[0]
3.60 SWITCHING BETWEEN INTERNAL AND CRYSTAL CLOCK
When switching between the internal clock to the crystal clock, an internal logic extends the LO time of the
clock sent to the counter to avoid undesired glitches. A typical clock switching timing diagram is shown
below:
SELECT CRYSTAL
CLOCK
INTERNAL 32K
CRYSTAL CLOCK
RTC CLOCK
3.61 CRYSTAL OSCILLATOR
The crystal oscillator has internal load capacitances, in order to allow a typical 32K crystal to operate as
described in the electrical characteristics tables. The TPS658600 has four integrated capacitors that can
be connected to the XTAL1, XTAL2 pins as defined by control bits CL_SEL[1:0] in register RTC_CTRL,
effectively applying a load capacitance to the external crystal.
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Table 3-56. CL_SEL[1:0] Setting
(Default in bold)
CL_SEL[1]
CL_SEL[0]
Total C_LOAD [pF]
(typ)
0
0
1.5
0
1
6.5
1
0
7.5
1
1
12.5
3.62 ADC FUNCTIONAL OVERVIEW
The TPS658600 ADC is capable of running in a variety of modes programmable via I2C. The ADC control
and data registers are accessible only by the standard I2C interface (SDA/SCLK). An internal 11:1 analog
multiplexer is used to allow a single SAR converter to sequentially monitor up to 11 analog inputs, as
shown inTable 3-57.
Table 3-57. ADC Channel Settings
CHANNEL
CONNECTION
CH1
ANLG1 pin
CH2
ANLG2 pin
CH3
ANLG3 pin
CH4
ISET pin
CH5
TS pin
FULL SCALE
READING
PARAMETER SAMPLED
VOLTAGE RANGE
SPECIAL FEATURES
Internal pull-up current
source programmable
via
I2C: 0/ 3/10/50 μA
2.6 V
User defined
0–2.6V
AVDD6-V(ANLGn)>
400mV
Voltage proportional to
charge current
0V (charger off) to
2.5V(fast charge)
—
2.6 V
Voltage proportional to pack
temperature
0V (short) to 2.2V (no
thermistor)
See Charger Section
2.6 V
2.6 V
2.6 V
CH6
RSVD
N/A
N/A
—
2.6 V
CH7
LDO_RTC pin
Internal LDO output voltage
0V to 3.3V
—
4.622 V
CH8
SYS pin
System Power bus voltage
0V to 5.5V
—
5.547 V
CH9
VIN_CHG pin
System Power bus voltage
0V to 5.5V
—
5.547 V
CH10
BAT pin
Battery pack positive
terminal voltage
0V to 4.6V
—
4.622 V
CH11
COMP pin
COMP pin voltage
0V – 2.6V
—
2.6 V
DETAILED DESCRIPTION
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A simplified block diagram for the ADC analog section is show in Figure 3-22.
Figure 3-22. Simplified ADC Block
3.62.1 ADC External Input Pins – Bias Current Settings
The external pins ANLG1, ANLG2 and ANLG3 may be biased using internal pull-up current sources, with
current source value set by register ADCANLG. The current sources are turned OFF when the ADC
reference is disabled.
Table 3-58. ADC Input Bias Selection
ADCANLG [Addr 0x60]
Default to 0
Bit Name
ANLG2FLT
ANLG3FLT
Function
SPARE
SPARE
IANLG3[1]
IANLG3[0]
ANLG3 BIAS CURRENT SOURCE
IANLG2[1]
IANLG2[0]
ANLG2 BIAS CURRENT SOURCE
IANLG1[1]
IANLG1[0]
ANLG1 BIAS CURRENT SOURCE
Table 3-59. ANLG3/2/1 Current Source Settings
IANLG[1]
IANLG[0]
Current (μA)
0
0
0
0
1
3
1
0
10
1
1
50
The COMP pin has no internal pull-up current source.
3.62.2 ADC Timing Engine Overview
The ADC timing engine can be configured to perform either one reading, a single-trigger multiple set of
readings, or to operate continuously until high or low limits are violated on any channel.
A conversion cycle includes the following steps:
1. Program the timing engine mode (single sample, multiple sample, etc.) and triggers
2. Enable the internal ADC reference and conversion start delay
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3. Select the channel to be used as the SAR input and start the conversion cycle
The timing engine has an internal ALU that stores the converted data in an internal accumulator,
executing mathematical operations with the stored data. A conversion cycle ends when the accumulator
data is transferred to the TPS658600 ADC RAM data registers.
When the conversion cycle is completed, an interrupt request corresponding to indicate end of conversion
operation is generated. The interrupt controller subsystem will set the ACK_ADC (bit B1, register 0xB6) to
indicate the source of the interrupt was the ADC subsystem. Additional information is available in the
ADC0_INT register (0x9A).
3.62.3 Configuring the ADC Conversion Cycle
3.62.3.1 Number of Samples and ADC Input Setup
Register ADC0_SET controls the following parameters for a conversion cycle: conversion start, continuous
or fixed-interval sampling mode, number of samples to be taken and channel selection.
Setting the ADC0_EN bit to 1 will start the conversion process. While a conversion cycle is being executed
(and conversions are being taken) the ADC0_INT register cannot be externally accessed.
The ADC engine has a BUSY signal generated by the ADC Digital Control Logic to indicate this condition.
If the ADC0_EN bit is cleared to 0 during a conversion, the conversion cycle will continue until the number
of samples specified with the RD_MODE bits has been taken so that the SUM (average) value from the
accumulator will be valid. The ADC0_EN bit must be set to 0 before a new conversion configuration is set
up.
Table 3-60. ADC0 Conversion Selection
ADC0_SET [Addr 0x61]
Bit
Number
Default in BOLD
B7
B6
B5
B4
B3
B2
B1
B0
RD0_MODE[1]
RD0_MODE[0]
CHSEL0[3]
CHSEL0[2]
CHSEL0[1]
CHSEL0[0]
Bit Name
ADC0_EN
REPEAT0
Function
ADC0 CONVERSION
START
ADC0 REPEAT
MODE ENABLE
When 0
DISABLED
DISABLED
When 1
ENABLED
ENABLED
READINGS IN A CONVERSION
ADC0 INPUT CHANNEL SELECTION
SEE ADC READING SETTINGS
SEE ADC CHANNEL SELECT SETTINGS
Table 3-61. ADC Readings Setting
(Default in bold)
NUMBER OF
READINGS
RD0_MODE[1]
RD0_MODE[0]
0
0
1
0
1
16
1
0
32
1
1
64
Table 3-62. ADC Channel Select Settings (Default in bold)
CHSELn[3:0]
CHANNEL
CHSELn[3:0]
CHANNEL
0000
CH1
1000
CH9
0001
CH2
1001
CH10
0010
CH3
1010
CH11
0011
CH4
1011
AGND
0100
CH5
1100
AGND
DETAILED DESCRIPTION
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Table 3-62. ADC Channel Select Settings (Default in bold) (continued)
CHSELn[3:0]
CHANNEL
CHSELn[3:0]
CHANNEL
0101
CH6
1101
AGND
0110
CH7
1110
AGND
0111
CH8
1111
AGND
Continuous sampling mode can be set by writing REPEAT to 1 and RD0_MODE[1:0]=00. With those
settings the conversions will be performed as single samples, without wait times, until the ADC_EN bit is
cleared by the host or a limit violation occurs. If fixed-interval sampling mode (REPEAT0 = 0) is chosen,
the conversion cycle will consist of a specific number of samples (1, 16, 32, or 64) as specified by the
RD0_MODE[1:0] bits. When a multiple sample conversion cycle is selected the time interval between
individual samples is defined by the WAIT bits (register ADC0_WAIT). To exit the continuous conversion
mode before a limit violation occurs, the host must first set the REPEAT bit to LO, and then set the
ADC0_EN bit to 0.
3.62.4 Timing and ADC Reference Setup
The ADC0_WAIT register controls the ADC0 timing engine reset, wait time value and the converter
internal reference voltage enable. The ADC reference and SAR are disabled when AUTO_REF=0 AND
REF_EN=0. The use of external references for the ADC is not supported.
Table 3-63. ADC0 Conversion Timing
ADC0_WAIT [Addr 0x62]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ADC_RESET
RSVD626
AUTO_REF
REF_EN
WAIT0[3]
WAIT0[2]
WAIT0[1]
WAIT0[0]
Function
RESET
CONVERSION
CYCLE
NOT USED
When 0
ALL ADC
ENGINES
ACTIVE
NOT USED
When 1
RESET ALL
ADC ENGINES
NOT USED
ADC Conversion Control
WAIT TIME BETWEEN INDIVIDUAL CONVERSIONS,
REPEAT MODE ENABLED (ms)
Function is based on ADC
Conversion Control
SEE WAIT0 SETTINGS TABLE
Table 3-64. ADC Conversion Control
(Default in bold)
AUTO_REF
REF_EN
DESCRIPTION
0
0
Reference and ADC disabled
0
1
Manual control of the Reference. WAIT=0 is not valid. 8ms must occur between REF_EN=1 and ADC0_EN=1
1
0
Automatic control of the Reference. Automatically enabled 8 ms before an ADC conversion is started.
1
1
Not a valid state
The relative timing between enabling the internal ADC reference / ANLGn pin bias currents and the start
of a conversion cycle is controlled by bits AUTO_REF and REF_EN. Those bits allow implementation of a
software only reference enable control or automatic reference enable control, as shown below:
Software enables ADC reference: Clear AUTO_REF bit to 0. Software must set REF_EN to 1 at least 8
ms before enabling an ADC engine and not clear REF_EN until all ADC engines are stopped.
Automatic ADC reference enable, internal or external trigger, wait time < 8ms : Set AUTO_REF bit to
1. The ADC logic will keep the ADC reference always on.
Automatic ADC reference enable, internal trigger, wait time > 8ms : Set AUTO_REF bit to 1. The ADC
logic enables the ADC reference 8 ms before the programmed wait time is reached
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Setting ADC_RESET to 1 will return ALL the ADC timing engine to the idle state, ready to be re-enabled
for a new conversion cycle. During the conversion cycle the ADC_RESET bit is internally set to LO prior to
the first ADC conversion being started. WAIT[3:0] sets the time interval between samples in the case
where a multiple-sample conversion cycle is being executed. WAIT[3:0] should be set LO in single sample
conversion cycles.
Table 3-65. ADC0 Conversion Wait Settings (Default in bold);
Valid for All Timing Engines
WAIT0[3:0]
WAIT TIME (ms)
WAIT0[3:0]
WAIT TIME (ms)
0000
0.000
1000
8.000
0001
0.062
1001
16.00
0010
0.125
1010
32.00
0011
0.250
1011
64.00
0100
0.500
1100
128.0
0101
1.000
1101
256.0
0110
2.000
1110
512.0
0111
4.000
1111
1024
3.62.5 External Trigger Setup
The ADC conversion cycle can be started via an internal or external trigger when using the ADC0 timing
engine. The trigger is selectable by setting bits ADC0_TRIG4, ADC0_TRIG2 in registers ADC0_DELAY.
Table 3-66. Trigger Settings
ADC0_DELAY [Addr 0x67]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ADC0_TRIG4
ADC0_TRIG2
ADC0HOLD
ADC0_EDGE
RSVD673
DELAY0[2]
DELAY0[1]
DELAY0[0]
Function
GPIO4 IS ADC0
EXT TRIGGER
GPIO2 IS ADC0
EXT TRIGGER
ADC HOLDOFF
ON/OFF CONTROL
NOT USED
NOT USED
ADC EXTERNAL TRIGGER DELAY (μs)
When 0
DISABLED
DISABLED
OFF
NOT USED
NOT USED
When 1
ENABLED
ENABLED
ON
NOT USED
NOT USED
000=00 001=50 010= 100 011=150
100=200 101=250 110=350 111=450
When more than one GPIO trigger source is selected the GPIO signals are OR'ed prior to trigger
detection. When both of those bits are cleared to 0 the internal trigger is selected.
ADC0_HOLDOFF (ADC0_DELAY[5]) enables the GPIOx trigger source to be used as a level-sensed
gating signal which will suspend conversion cycles when the trigger source is low. The default for this bit
is 0. When ADC0HOLD is 0, the conversion cycle will continue for the preset number of conversions
selected with the RD_MODE bits once the initial trigger occurs. If the ADC0HOLD bit is 1, any pending
conversion cycle can be suspended if the GPIO trigger goes low (and resumes once the trigger signal
goes high again and the trigger delay time has been met). ADC0_DELAY[2:0] are used to set the initial
wait interval from the trigger event until the first conversion in a cycle is started. This delay may be from 0
to 450μs.
When the GPIO's are selected as external triggers the ADC conversion start will be dependent on the
GPIO configuration. Table 3-67 shows the possible options:
Table 3-67. ADC0 GPIO Trigger Settings
ADC0_TRIG2 = 1, ADC0_TRIG4 = 0
ADC0_TRIG2 = 0, ADC0_TRIG4 = 1
GPIO2 PIN
ADC TRIGGER
SOURCE
WHEN HOLDOFF=HI
GPIO4 PIN
ADC TRIGGER
SOURCE
WHEN
HOLDOFF=HI
NON-INVERTED
GPIO2
POSITIVE EDGE
SUSPEND TRIGGER at
GPIO2=LO
NON-INVERTED
GPIO4
POSITIVE EDGE
SUSPEND
TRIGGER at
GPIO4=LO
DETAILED DESCRIPTION
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Table 3-67. ADC0 GPIO Trigger Settings (continued)
ADC0_TRIG2 = 1, ADC0_TRIG4 = 0
INVERTED
GPIO2
NEGATIVE
EDGE
SUSPEND TRIGGER at
GPIO2=HI
ADC0_TRIG2 = 0, ADC0_TRIG4 = 1
INVERTED
GPIO4 NEGATIVE
EDGE
SUSPEND
TRIGGER at
GPIO4=HI
ADC0_TRIG2=HI,ADC0_TRIG4=HI
GPIO2 PIN
GPIO4 PIN
ADC TRIGGER SOURCE
WHEN HOLDOFF=HI
NON-INVERTED
NON-INVERTED
GPIO2 OR GPIO4 POSITIVE
EDGE
SUSPEND TRIGGER at GPIO2
= LO AND GPIO4 = LO
NON-INVERTED
INVERTED
GPIO2 POSITIVE EDGE OR
GPIO4 NEGATIVE EDGE
SUSPEND TRIGGER at GPIO2
= LO AND GPIO4 = HI
INVERTED
NON-INVERTED
GPIO2 NEGATIVE EDGE OR
GPIO4 POSITIVE EDGE
SUSPEND TRIGGER at GPIO2
= HI AND GPIO4 = LO
INVERTED
INVERTED
GPIO2 OR GPIO4 NEGATIVE
EDGE
SUSPEND TRIGGER at GPIO2
= HI AND GPIO4 = HI
The procedure to start an externally-triggered conversion cycle has the following steps:
1. Verify that the current conversion cycle has ended (ADC0_BUSY is 0, I2C register STAT4)
2. Clear ADC0_EN to 0 (ADC0_SET[7]).
3. Set the appropriate bit in the corresponding ADC0_DELAY register (example – write 1 to
ADC0_DELAY bit B7 to use GPIO4 as trigger source for ADC0). Ensure that the selected GPIOs have
the appropriate input and polarity selection – see GPIOSET1 and GPIOSET2 registers.
4. Set ADC0_EN to 1
After step 4 the ADC will be armed, waiting for an external trigger detection to start a conversion cycle. In
triggered mode the current cycle will not expire if the converter is armed and an external trigger is not
detected.
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CONVERSION CYCLE
GPIO2
ON
INTERNAL ADC
CONVERSION STATUS
OFF
TWAIT(TRG)
TDLY(TRG)
st
1
SAMPLE
LAST
SAMPLE
ADC CONVERSION TRIGGERED BY GPIO2, POSITIVE EDGE TRIGGERED, ACTIVE LEVEL HI , HOLDOFF = LO
CONVERSION CYCLE
GPIO2
ON
OFF
INTERNAL ADC
CONVERSION STATUS
TWAIT(TRG)
TDLY(TRG)
TDLY(TRG)
1st
SAMPLE
LAST
SAMPLE
ADC CONVERSION TRIGGERED BY GPIO2, POSITIVE EDGE TRIGGERED, ACTIVE LEVEL HI , HOLDOFF = HI, 4 SAMPLE
CYCLE
Figure 3-23. ADC Operation Example
3.62.6 ADC ALU Unit and Result Registers
The ALU performs mathematical operations on the ADC output data. It can execute average (SUM)
calculations and minimum / maximum detection for a conversion cycle. The result of the SUM calculations
is stored in a 16 bit accumulator register (ADC0SUM2, ADC0_SUM1) and the MIN/MAX data is stored in
10-bit registers (ADC0_MAX2, ADC0_MAX1, ADC0_MIN2, ADC0_MIN1).
Equation 15 indicates how to translate the register data into a voltage reading for each channel:
ADC_OUTPUT_COUNTS = [ADC_INPUT_VOLTAGE / FULL_SCALE_READING] × 1023
Table 3-68. ADC0 Output Data
ADC0_SUM2
(1)
[Addr 0x94]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
AVG[15]
AVG[14]
AVG[13]
AVG[12]
AVG[11]
AVG[10]
AVG[9]
AVG[8]
AVG[6]
AVG[5]
AVG[4]
AVG[3]
AVG[2]
AVG[1]
AVG[0]
RSVD966
RSVD965
RSVD964
RSVD963
RSVD962
MAX[9]
MAX[8]
ADC0_SUM1 [Addr 0x95]
Bit Name
AVG[7]
ADC0_MAX2 [Addr 0x96]
Bit Name
RSVD967
ADC0_MAX1 [Addr 0x97]
(1)
All bits in ADC0_SUM2 are read only.
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Table 3-68. ADC0 Output Data (continued)
Bit Name
MAX[7]
MAX[6]
MAX[5]
MAX[4]
MAX[3]
MAX[2]
MAX[1]
MAX[0]
RSVD986
RSVD985
RSVD984
RSVD983
RSVD982
MIN[9]
MIN[8]
MIN[6]
MIN[5]
MIN[4]
MIN[3]
MIN[2]
MIN[1]
MIN[0]
ADC0_MIN2 [Addr 0x98]
Bit Name
RSVD987
ADC0_MIN1 [Addr 0x99]
Bit Name
MIN[7]
3.62.7 Limit Check Setup
The ADC0 timing engine has configurable low and high thresholds to interrupt the host when conversion
values, stored in registers ADC0_MAX and ADC0_MIN exceed a pre-selected range . A limit violation will
be detected and an interrupt sent to the host when the sampled value stored in registers ADC0_MAX2,
ADC0_MAX1 exceeds the maximum value set in registers ADC0_HILIM2, ADC0_HILIM1 or when the
minimum sampled value stored in registers ADC0_MIN2, ADC0_MIN1 is lower than the minimum value
programmed in registers and ADC0_HILIM2, ADC0_HILIM1.
Limit violations can not occur if Low Limit = 0x000 and High Limit = 0xFFF.
Table 3-69. ADC0 Limit Selection
ADC0_HILIM2 [Addr 0x63]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD637
RSVD636
RSVD635
RSVD634
HILIMA[11]
HILIMA[10]
HILIMA[9]
HILIMA[8]
HILIMA[6]
HILIMA[5]
HILIMA[4]
HILIMA[3]
HILIMA[2]
HILIMA[1]
HILIMA[0]
RSVD656
RSVD655
RSVD654
LOLIMA[11]
LOLIMA[10]
LOLIMA[9]
LOLIMA[8]
LOLIMA[6]
LOLIMA[5]
LOLIMA[4]
LOLIMA[3]
LOLIMA[2]
LOLIMA[1]
LOLIMA[0]
ADC0_HILIM1 [Addr 0x64]
Bit Name
HILIMA[7]
ADC0_LOLIM2 [Addr 0x65]
Bit Name
RSVD657
ADC0_LOLIM1 [Addr 0x66]
Bit Name
LOLIMA[7]
The limit detection ADC conversion cycle should be configured with internal trigger and sampling
sequences as follows:
1. To detect when an individual sample violates the max/min limits: Set RD_MODE[1:0] to 00 and
REPEAT to 1. With these settings the ALU will compare the 10-bit ADC data returned from the SAR
engine to the 10 bit values loaded in the ADC0_LIMIT values. The conversion sequence will repeat
until either a violation interrupt occurs or the ADC0_EN bit is written to 0.
2. To detect when the average value violates the max/min limits: Set RD_MODE[1:0]) to 01, 10 or 11 and
REPEAT to 1. At the end of the multiple sample conversion cycle the ALU will calculate the 12 bit
average of the sample values by shifting the AVG[15:0] register (shift right 2 if 16 samples, shift right 3
if 32 samples and shift right 4 if 64 samples) . The shifted 12-bit average value is then compared to the
value programmed in registers ADC0_LIMIT.
3.62.8 ADC Status Registers
The ADC conversion status for the timing engine is available in the ADC0_INT register. The ADC0_INT
register is read-only. Reading the ADC0_INT register clears the ADC0INT bit in the STAT4 register
(ADC0INT=0).
Table 3-70. ADC Conversion Status
ADC0_ INT [Addr 0x9A]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ADC0_ DONE
ADC0_
ERROR
HILIM0_FLT
LOLIM0_FLT
RSVD9A3
RSVD9A2
ADC0_GPIO4ST
ADC0_GPIO2ST
Function
CONVERSION
CYCLE STATUS
ADC_STATUS
HI LIMIT
FAULT
LO LIMIT FAULT
NOT USED
NOT USED
GPIO4 LEVEL
AT ADC0 EOC
GPIO2 LEVEL
AT ADC0 EOC
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Table 3-70. ADC Conversion Status (continued)
ADC0_ INT [Addr 0x9A]
When 0
BUSY
NO ERROR
NOT
DETECTED
NO DETECTED
NOT USED
NOT USED
LOW
LOW
When 1
DONE
ERROR
DETECTED
DETECTED
NOT USED
NOT USED
HIGH
HIGH
3.63 GPIO
The TPS658600 integrates 4 general purpose push-pull ports (GPIOs) which can be configured as
selectable inputs or outputs via register GPIOSET1 bits. When the GPIO is not configured the pull-down
current source (2.5uA typ) is connected to the GPIOn pin. When configured as an input the GPIO can be
set as inverting or non-inverting via bits GPIOnINV in the GPIOSET2 register.
When configured as an output, the GPIO output level is defined by bits GPIOnOUT in the GPIOSET2
register.
Table 3-71. GPIO Control (1)
GPIOSET1 [Addr 0x5D]
Default to 0
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
GPIO4_MODE
1
GPIO4_MODE
0
GPIO3_MODE
1
GPIO3_MODE
0
GPIO2_MODE
1
GPIO2_MODE
0
GPIO1_MODE
1
GPIO1_MODE
0
Function
GPIO4 CONFIGURATION
GPIO3 CONFIGURATION
GPIO2 CONFIGURATION
GPIO1 CONFIGURATION
GPIOSET2 [Addr 0x5E]
(1)
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
GPIO4INV
GPIO3INV
GPIO2INV
GPIO1INV
GPIO2_MODE
1
GPIO2_MODE
0
GPIO1_MODE
1
GPIO1_MODE
0
Function
GPIO4 INPUT
BUFFER
MODE
GPIO3 INPUT
BUFFER
MODE
GPIO2 INPUT
BUFFER
MODE
GPIO1 INPUT
BUFFER
MODE
GPIO4
VOLTAGE,
CONFIGURED
AS OUTPUT
GPIO3
VOLTAGE,
CONFIGURED
AS OUTPUT
GPIO2
VOLTAGE,
CONFIGURED
AS OUTPUT
GPIO1
VOLTAGE,
CONFIGURED
AS OUTPUT
When 0
NONINVERTING
NONINVERTING
NONINVERTING
NONINVERTING
LO
LO
LO
LO
When 1
INVERTING
INVERTING
INVERTING
INVERTING
HI
HI
HI
HI
All GPIO's default to the same configuration.
Table 3-72. GPIO4/3/2/1_MODE Settings
GPIOx_MODE[1]
GPIOx_MODE[0]
GPIO4 Config
GPIO3 Config
GPIO2 Config
GPIO1 Config
0
0
Not Configured
Not Configured
Not Configured
Not Configured
0
1
Output
Output
Output
Output
1
0
Input ADC Trigger
Input Not Used
Input ADC Trigger
Input PWM/PFM Control
1
1
Input LDO6/7/8 Enable
Input LDO2/3 Enable
Input LDO0/1 ENABLE
Input Not Used
3.64 STATUS REGISTERS
The system status is accessible via I2C registers listed below. The STATn registers are read only.
Table 3-73. Status Registers
ADC0_ INT [Addr 0x9A]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ADC0_ DONE
ADC0_ ERROR
HILIM0_FLT
LOLIM0_FLT
RSVD9A3
RSVD9A2
ADC0_GPIO4ST
ADC0_GPIO2ST
Function
CONVERSION
CYCLE STATUS
ADC_STATUS
HI LIMIT FAULT
LO LIMIT FAULT
NOT USED
NOT USED
GPIO4 LEVEL AT
ADC0 EOC
GPIO2 LEVEL AT
ADC0 EOC
When 0
BUSY
NO ERROR
NOT DETECTED
NOT DETECTED
NOT USED
NOT USED
LOW
LOW
When 1
DONE
ERROR
DETECTED
DETECTED
NOT USED
NOT USED
HIGH
HIGH
B7
B6
B5
B4
B3
B2
B1
B0
STAT1 [Addr 0xB9]
Bit Number
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Table 3-73. Status Registers (continued)
Bit Name
BATSYSON
ACSWON
Function
BAT TO SYS
SWITCH ON/OFF
STATUS
When 0
OFF
OFF
When 1
ON
ON
USBSWON
BATCHGSWON
RSVDB83
PACK_HOT
PACK_COLD
BATDET
BAT TO VIN_CHG
SWITCH ON/OFF
STATUS
SPARE
PACK TEMP
EXCEEDS HOT
THRESHOLD
PACK TEMP
BELOW COLD
THRESHOLD
BATTTERY PACK
TS THERMISTOR
DETECTION
OFF
OFF
NOT USED
NO
NO
NOT DETECTED
ON
ON
NOT USED
YES
YES
DETECTED
AC SWITCH ON/OFF
USB SWITCH
STATUS
ON/OFF STATUS
STAT2 [Addr 0xBA]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
TMRFLT
DPPM_ON(4)
TH_ON
ITERM
SLEEPTSHUT
STAT1
STAT2
COMPDET
Function
PRE-CHARGE OR
CHARGE TIMER
TIMEOUT
CHARGER DPPM
LOOP STATUS
CHARGER
THERMAL LOOP
STATUS
CHARGE
CURRENT BELOW
TERMINATION
THRESHOLD
NOT USED
CHARGE STATUS
When 0
NO
OFF
OFF
NO
NOT USED
When 1
YES
ON
ON
YES
NOT USED
00= PRE-CHARGE ON
01=CHARGE DONE
10=FAST CHARGE ON
11= CHARGE SUSPEND,
TIMER FAULT, CHARGER OFF
nHOTRST PULSE
GENERATED
REBOOT CYCLE
NO
YES
STAT3 [Addr 0xBB]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SLEEPREQ
LOWSYS
RESUME
RTC_ALARM
ACDET
USBDET
AC_OVP
USB_OVP
Function
SLEEP REQUEST
STATE SET
LOWSYS
DETECTION
STATUS
RESUME
DETECTION
STATUS
SPARE
AC INPUT OVP
DETECTION
USB INPUT OVP
DETECTION
When 0
NO
NOT DETECTED
NOT DETECTED
SPARE
NOT DETECTED
NOT DETECTED
NO OVP
NO OVP
When 1
YES
DETECTED
DETECTED
SPARE
DETECTED
DETECTED
OVP DETECTED
OVP DETECTED
AC INPUT POWER
USB INPUT
STATUS
POWER STATUS
STAT4 [Addr 0xBC]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVDBC7
RSVDBC6
RSVDBC5
ADC0BUSY
RSVDBC3
RSVDBC2
RSVDBC1
ADC0INT
Function
SPARE
SPARE
SPARE
ADC ENGINE 0
MODE
SPARE
SPARE
SPARE
ADC ENGINE 0
INTERRUPT
When 0
SPARE
SPARE
SPARE
IDLE
SPARE
SPARE
SPARE
NOT ACTIVE
When 1
SPARE
SPARE
SPARE
BUSY
SPARE
SPARE
SPARE
ACTIVE
3.65 INTERRUPT CONTROLLER
The interrupt controller monitors the system status bus and internal signals continuously, generating an
interrupt (INT = ‘0’) when a system status change is detected. Individual bits that generated the interrupt
will be set to 1 in the INT_ACK registers (read only registers), indicating which parameters generated the
interrupt.
All the parameters monitored by the interrupt controller can be masked by registers INT_MASK
(0=unmasked, 1=masked). Masked parameters do not generate an interrupt when their state changes.
When the host reads the INT_ACK registers, the interrupt is reset causing the INT pin to go to a logic 1
and the INT_ACK register bits are cleared.
The power good signals from the integrated supplies are level sensitive, and they will continue to cause an
interrupt until the power good condition returns or the signal is masked. For non-masked power good
parameters the INT_ACK bit will indicate the present state of the power good signals. The INTMASK
register bits are cleared to 0 upon power-up.
Table 3-74. INT_ACK registers
INT_ACK1 [Addr 0xB5]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
ACK_PLDO7
ACK_PLDO6
ACK_PLDO5
ACK_PLDO4
ACK_PLDO3
ACK_PLDO2
ACK_PLDO1
ACK_PLDO0
ACK_PSM2
ACK_PSM1
ACK_PSM0
ACK_PLDO9
ACK_PLDO8
ACK_ADC
ACK_ COMPDET (1)
INT_ACK2 [Addr 0xB6]
Bit Name
ACK_PSM3
INT_ACK3 [Addr 0xB7]
(1)
88
ACK_COMPDET= ACK INT BY HOTRST FLAG SET
DETAILED DESCRIPTION
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Table 3-74. INT_ACK registers (continued)
Bit Name
ACK_PP
ACK_CHGTEMP
ACK_CHGSTAT
ACK_BATDET
ACK_ACDET
ACK_USBDET
ACKACUSBOVP
ACK_RTCALM1
RSVDB86 (2)
IMASKLOWSYS
IMASKRESUME
IMASKRTCALM1
IMASKACDET
ACK_LOWSYS
ACK_RESUME
INT_ACK4 [Addr 0xB8]
Bit Name
(2)
RSVDB87
RSVDB86= ACK INT BY SLEEP REQUEST
Table 3-75. INTMASK Registers
INTMASK1 [Addr 0xB0]
Bit Name
Default to 1 (Masked)
IMASK_PLDO7
IMASK_PLDO6
IMASK_PLDO5
IMASK_PLDO4
IMASK_PLDO3
IMASK_PLDO2
IMASK_PLDO1
INTMASK2 [Addr 0xB1]
Bit Name
IMASK_PSM3
IMASK_PSM2
IMASK_PSM1
IMASK_PSM0
IMASK_PLDO9
IMASK_PLDO8
IMASKADC
INTMASK3 [Addr 0xB2]
Bit Name
IMASKSYSSW
IMASKACSW
IMASKUSBSW
IMASKBCHGSW
RSVDB83
IMASK_HOT
IMASK_COLD
IMASKBATDET
Default to 1 (Masked)
IMASK_TMRFLT
IMASK_DPPM
IMASK_THON
IMASK_TERM
IMASK_TSHUT
IMASKCHSTAT
IMASKRTCALM2
INTMASK5 [Addr 0xB4]
Bit Name
RSVDB10
Default to 1 (Masked)
INTMASK4 [Addr 0xB3]
Bit Name
IMASK_PLDO0
Default to 1 (Masked)
IMASK_COMP
Default to 1 (Masked)
RSVDB47
IMASKLOWSYS
IMASKRESUME
IMASKRTCALM1
IMASKACDET
IMASKUSBDET
IMASKAC_OVP
IMASKUSB_OVP
The interrupt controller can monitor either level or edge transitions to generate the interrupt request:
PARAMETER
STATUS BIT
SET INT_ACK BIT ON
MASK reg/bit
INT_ACK reg/bit
ACK clear at
LDO0 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO0
INT_ACK1 / ACK_LDO0
Read INT_ACK1
LDO1 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO1
INT_ACK1 / ACK_PLDO1
Read INT_ACK1
LDO2 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO2
INT_ACK1 / ACK_PLDO2
Read INT_ACK1
LDO3 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO3
INT_ACK1 / ACK_PLDO3
Read INT_ACK1
LDO4 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO4
INT_ACK1 / ACK_PLDO4
Read INT_ACK1
LDO5 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO5
INT_ACK1 / ACK_PLDO5
Read INT_ACK1
LDO6 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO6
INT_ACK1 / ACK_PLDO6
Read INT_ACK1
LDO7 power good fault
None
PGOOD FAULT DETECTED
INTMASK1 /
IMASK_PLDO7
INT_ACK1 / ACK_PLDO7
Read INT_ACK1
LDO8 power good fault
None
PGOOD FAULT DETECTED
INTMASK2 /
IMASK_PLDO8
INT_ACK2 / ACK_PLDO8
Read INT_ACK2
LDO9 power good fault
None
PGOOD FAULT DETECTED
INTMASK2 /
IMASK_PLDO9
INT_ACK2 / ACK_PLDO9
Read INT_ACK2
SM0 power good fault
None
PGOOD FAULT DETECTED
INTMASK2 / IMASK_PSM0
INT_ACK2 / ACK_PSM0
Read INT_ACK2
SM1 power good fault
None
PGOOD FAULT DETECTED
INTMASK2 / IMASK_PSM1
INT_ACK2 / ACK_PSM1
Read INT_ACK2
SM2 power good fault
None
PGOOD FAULT DETECTED
INTMASK2 / IMASK_PSM2
INT_ACK2 / ACK_PSM2
Read INT_ACK2
SM3 over-voltage detection
None
SM3 OVER-VOLTAGE
DETECTED
INTMASK2 / IMASK_PSM3
INT_ACK2 / ACK_PSM3
Read INT_ACK2
HOT RESET FLAG STATUS
STAT2 bit 0
HI→LO OR LO→HI
INTMASK4 / IMASK_COMP
INT_ACK2 /
ACK_COMPDET
Read INT_ACK2
BATSYS switch STATUS
STAT1 bit 7
HI→LO OR LO→HI
INTMASK3 / IMASKSYSSW INT_ACK3 / ACK_PP
Read INT_ACK3
ACSYS SWITCH STATUS
STAT1 bit 6
HI→LO OR LO→HI
INTMASK3 / IMASKACSW
INT_ACK3 /ACK_PP
Read INT_ACK3
USBSYS SWITCH STATUS
STAT1 bit 5
HI→LO OR LO→HI
INTMASK3 / IMASKUSBSW INT_ACK3 /ACK_PP
Read INT_ACK3
BATCHG SW STATUS
STAT1 bit 4
HI→LO OR LO→HI
INTMASK3 / IMASK_TERM
INT_ACK3 /ACK_PP
Read INT_ACK3
PACK HOT DETECTION
STAT1 bit 2
HI→LO OR LO→HI
INTMASK3 /
IMASK_TSHUT
INT_ACK3
/ACK_CHGTEMP
Read INT_ACK3
PACK COLD DETECTION
STAT1 bit 1
HI→LO OR LO→HI
INTMASK3 /
IMASKCHSTAT
INT_ACK3
/ACK_CHGTEMP
Read INT_ACK3
BATTERY INSERTION
STAT1 bit 0
HI→LO OR LO→HI
INTMASK3 /
IMASKBATDET
INT_ACK3 /ACK_BATDET
Read INT_ACK3
charger timer fault
STAT2 bit 7
HI→LO OR LO→HI
INTMASK4 /
IMASK_TMRFLT
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
DETAILED DESCRIPTION
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PARAMETER
STATUS BIT
SET INT_ACK BIT ON
MASK reg/bit
INT_ACK reg/bit
ACK clear at
DPPM loop STATUS
STAT2 bit 6
HI→LO OR LO→HI
INTMASK4 / IMASK_DPPM
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
thermal loop STATUS
STAT2 bit 5
HI→LO OR LO→HI
INTMASK4 / IMASK_THON
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
termination STATUS
STAT2 bit 4
HI→LO OR LO→HI
INTMASK4 / IMASK_TERM
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
charger STAT2
STAT2 bit 1
HI→LO OR LO→HI
INTMASK4 /
IMASKCHSTAT
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
charger STAT1
STAT2 bit 2
HI→LO OR LO→HI
INTMASK4 /
IMASKCHSTAT
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
SLEEP and tshut detected
STAT2 bit 3
HI→LO OR LO→HI
INTMASK4 /
IMASK_TSHUT
INT_ACK3
/ACK_CHGSTAT
Read INT_ACK3
SLEEP REQUEST
DETECTED
STAT3 bit7
HI→LO OR LO→HI
INTMASK2/RSVDB10
INT_ACK4 / RSVDB86
Read INT_ACK4
AC DETection
STAT3 bit 3
HI→LO OR LO→HI
INTMASK5 / IMASKACDET
INT_ACK3 / ACK_ACDET
Read INT_ACK3
USB DETection
STAT3 bit 2
HI→LO OR LO→HI
INTMASK5 /
IMAKSUSBDET
INT_ACK3 /
ACKACUSBOVP
Read INT_ACK3
AC OVP
STAT3 bit 1
HI→LO OR LO→HI
INTMASK5 /
IMAKSAC_OVP
INT_ACK3 /
ACKACUSBOVP
Read INT_ACK3
USB OVP
STAT3 bit 0
HI→LO OR LO→HI
INTMASK5 /
IMASKUSB_OVP
INT_ACK3 /
ACKACUSBOVP
Read INT_ACK3
RTC ALARM1
NONE
ALARM1 DETECTED
INTMASK5 /
IMAKSRTCALM1
INT_ACK3 /
ACK_RTCALM1
Read INT_ACK3
RTC ALARM2
NONE
ALARM2 DETECTED
INTMASK4 /
IMASKRTCALM2
INT_ACK4 /
ACK_RTCALM2
Read INT_ACK4
RESUME command
STAT3 bit 5
HI→LO OR LO→HI
INTMASK5 /
IMASKRESUME
INT_ACK4 / ACK_RESUME Read INT_ACK4
LOWSYS detection
STAT3 bit 6
HI→LO OR LO→HI
INTMASK5 /
IMASKLOWSYS
INT_ACK4 / ACK_LOWSYS Read INT_ACK4
DADC0INT
STAT4 bit 0
LO→HI ONLY
INTMASK2 / IMASKADC
INT_ACK4 / ACK_ADC
Read ADC0_INT
3.66 DEVICE ID RAM REGISTER
Each device has a unique 8-bit identifier stored in the read only register VERSIONID.
Table 3-76. Device ID Register
VERSIONID [Addr 0xCD]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
VCRC7
VCRC6
VCRC5
VCRC4
VCRC3
VCRC2
VCRC1
VCRC0
0
0
0
0
1
0
Device Number
TPS658600
90
VERSION IDENTIFICATION, FACTORY SET
0
0
DETAILED DESCRIPTION
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3.67 RAM MEMORY MAP
MEMORY AREA
ADDR
SUPPLY CONTROL AND
VOLTAGE SETTING
0x10
0x11
REGISTER
NAME
R/W
DESCRIPTION
SUPPLYENA
R/W
LDO2, SM0, SM1 ENABLE CONTROL
SUPPLYENB
R/W
LDO2, SM0, SM1 ENABLE CONTROL
0x12
SUPPLYENC
R/W
LDO0, LDO1. LDO3, LDO4, LDO6, LDO7, LDO8, SM2 ENABLE
CONTROL
0x13
SUPPLYEND
R/W
LDO0, LDO1. LDO3, LDO4, LDO6, LDO7, LDO8, SM2 ENABLE
CONTROL
0x14
SUPPLYENE
R/W
TPS658600 OPERATION MODE, LDO5, LDO9 ENABLE CONTROL
0x20
VCC1
R/W
SM0, SM1, LDO2, LDO4 VOLTAGE SELECTION / CHANGE
CONTROL
0x21
VCC2
R/W
SM0, SM1, LDO2, LDO4 VOLTAGE SELECTION / CHANGE
CONTROL
0x23
SM1V1
R/W
SM1 VOLTAGE SETTING #1
0x24
SM1V2
R/W
SM1 VOLTAGE SETTING #2
0x25
SM1SL
R/W
SM1 SLEW RATE
0x26
SM0V1
R/W
SM0 VOLTAGE SETTING #1
0x27
SM0V2
R/W
SM0 VOLTAGE SETTING #2
0x28
SM0SL
R/W
SM0 SLEW RATE
0x29
LDO2AV1
R/W
LDO2 VOLTAGE SETTING #1
0x2A
LDO2AV2
R/W
LDO2 VOLTAGE SETTING #2
0x2F
LDO2BV1
R/W
LDO2 VOLTAGE SETTING #1
0x30
LDO2BV2
R/W
LDO2 VOLTAGE SETTING #2
0x32
LDO4V1
R/W
LDO4 VOLTAGE SETTING # 1
0x33
LDO4V2
R/W
LDO4 VOLTAGE SETTING # 2
0x41
SUPPLYV1
R/W
LDO1, LDO0 OUPUT VOLTAGE
0x42
SUPPLYV2
R/W
SM2, LDO8 OUTPUT VOLTAGE
0x43
SUPPLYV3
R/W
LDO6, LDO7 OUTPUT VOLTAGE
0x44
SUPPLYV4
R/W
RTC_LDO, LDO3 OUTPUT VOLTAGE, RTC_LDO ON/OFF
0x45
SUPPLYV5
R/W
SPARE
0x46
SUPPLYV6
R/W
LDO5, LDO9 OUTPUT VOLTAGE
0x47
SMODE1
R/W
SM0, SM1, SM2, PWM/PFM MODE SETTING
0x48
SMODE2
R/W
SPARE
0x49
CHG1
R/W
CHARGER SETTINGS
0x4A
CHG2
R/W
CHARGER SETTINGS
0x4B
CHG3
R/W
CHARGER SETTING
POWER PATH SETUP
RAM
0x4C
PPATH2
R/W
OUT POWER PATH SETTINGS
TPS658600
SEQUENCING
0x4D
PGFLTMSK1
R/W
POWER GOOD FAULT MASK
0x4E
PGFLTMSK2
R/W
POWER GOOD FAULT MASK
0xCC
SPARE2
R/W
REBOOT CYCLE FLAG RESET
CONVERTER SETTINGS
CHARGER SETUP RAM
DETAILED DESCRIPTION
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MEMORY AREA
PERIPHERAL
CONTROL RAM
ADC0 ENGINE
SETUP RAM
ADC0 ENGINE
DATA RAM
INTERRUPT
CONTROL RAM
SYSTEM
STATUS RAM
92
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ADDR
hex
REGISTER NAME
ACC
DESCRIPTION
0X50
RGB1FLASH
R/W
RGB1R/G/B DRIVERS FLASH MODE SETTINGS
0X51
RGB1RED
R/W
RGB1 RED DRIVER INTENSITY CONTROL
0X52
RGB1GREEN
R/W
RGB1 GREEN DRIVER INTENSITY CONTROL
0X53
RGB1BLUE
R/W
RGB1 BLUE DRIVER INTENSITY CONTROL
0X54
RGB2RED
R/W
RGB2 RED DRIVER INTENSITY CONTROL
0X55
RGB2GREEN
R/W
RGB2 GREEN DRIVER INTENSITY CONTROL
0X56
RGB2BLUE
R/W
RGB2 BLUE DRIVER INTENSITY CONTROL
0X57
SM3_SET0
R/W
WHITE LED DUTY CYCLE SETTINGS
0X58
SM3_SET1
R/W
WHITE LED DUTY CYCLE SETTINGS
0X59
LED_PWM
R/W
LED_PWM DRIVER DUTY CYCLE SETTINGS
0X5A
DIG_PWM
R/W
DIG_PWM DRIVER DUTY CYCLE SETTINGS
0X5B
PWM
R/W
PWM DRIVER DUTY CYCLE SETTINGS
0X5C
DIG_PWM1
R/W
DIG_PWM1 DRIVER DUTY CYCLE SETTINGS
0X5D
GPIOSET1
R/W
GPIO CONFIGURATION
0X5E
GPIOSET2
R/W
GPIO CONFIGURATION
0x60
ADCANLG
R/W
adc input bias and filter control
0X61
ADC0_SET
R/W
ADC0 CONVERSION CYCLE SETUP
0X62
ADC0_WAIT
R/W
ADC0 CONVERSION CYCLE SETUP
0X63
ADC0_HILIMIT2
R/W
ADC0 HI LIMIT THRESHOLD
0X64
ADC0_HILIMIT1
R/W
ADC0 HI LIMIT THRESHOLD
0X65
ADC0_LOLIMIT2
R/W
ADC0 LO LIMIT THRESHOLD
0X66
ADC0_LOLIMIT1
R/W
ADC0 LO LIMIT THRESHOLD
0X67
ADC0_DELAY
R/W
ADC0 TRIGGER MODE
0x94
ADC0_SUM2
R
SUM OF ALL SAMPLES
0x95
ADC0_SUM1
R
SUM OF ALL SAMPLES
0x96
ADC0_MAX2
R
MAX SAMPLE VALUE
0x97
ADC0_MAX1
R
MAX SAMPLE VALUE
0x98
ADC0_MIN2
R
MIN SAMPLE VALUE
0x99
ADC0_MIN1
R
MIN SAMPLE VALUE
0x9A
ADC0_INT
R
ADC0 STATUS
0xB0
INT_MASK1
R/W
INT_MASK
0xB1
INT_MASK2
R/W
INT MASK
0xB2
INT_MASK3
R/W
INT MASK
0xB3
INT_MASK4
R/W
INT MANAGEMENT
0xB4
INT_MASK5
R/W
INT MANAGEMENT
0xB5
INT_ACK1
R/W
INT MANAGEMENT REGISTER
0xB6
INT_ACK2
R/W
INT MANAGEMENT REGISTER
0xB7
INT_ACK3
R/W
INT MANAGEMENT REGISTER
0xB8
INT_ACK4
R/W
INT MANAGEMENT REGISTER
0xB9
STAT1
R
power path switches, pack status
0xBA
STAT2
R
charger status
0xBB
STAT3
R
rtc, input power status
0xBC
STAT4
R
ADC STATUS
DETAILED DESCRIPTION
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MEMORY AREA
RTC
SLVSA37 – DECEMBER 2009
ADDR
hex
REGISTER NAME
ACC
DESCRIPTION
0xC0
RTC_CTRL
R/W
RTC CONTROL REGISTER
0XC1
RTC ALARM
RTC ALARM
0xC2
0xC3
0xC4
0xC5
0xC6
RTC COUNTER
R/W
RTC DATA
0xC7
0xC8
0xC9
0xCA
DEVICE ID
0XCD
VERSIONCRC
R
Device identification
DETAILED DESCRIPTION
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4 APPLICATION INFORMATION
4.1
4.1.1
DC/DC CONVERTER OUTPUT FILTER
Inductor Selection
The typical value for the converter inductor is 2.2μH output inductor. Larger or smaller inductor values can
be used to optimize the performance of the device for specific operation conditions. The selected inductor
has to be rated for its DC resistance and saturation current. The DC resistance of the inductance will
influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should
be selected for highest efficiency. See document SLVA157 for more information on inductor selection.
Equation 16 calculates the maximum inductor current under static load conditions. The saturation current
of the inductor should be rated higher than the maximum inductor current as calculated with Equation 16.
This is recommended because during heavy load transient the inductor current will rise above the
calculated value.
Vout
Vin
L ´ ¦
1DIL = Vout ´
ILmax = Ioutmax +
DIL
2
(16)
with:
f = Switching Frequency (2.25MHz typical)
L = Inductor Value
ΔIL= Peak to Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current will occur at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor
currents versus a comparable shielded inductor. A more conservative approach is to select the inductor
current rating just for the maximum switch current of the corresponding converter. It must be considered,
that the core material from inductor to inductor differs and will have an impact on the efficiency especially
at high switching frequencies.
Refer to Table 4-1 and the typical applications for possible inductors.
Table 4-1. Inductors
SUPPLY
SM0
SM1
SM2
SM3
4.1.2
INDUCTOR TYPE
INDUCTANCE
[μH]
SUPPLIER
TYP DIMENSIONS
[mm]
LPS4012-152
1.5
Coilcraft
4x4x1
VLS4012-1R5N1R5
1.5
TDK
4x4x1
4x4x1
LPS4012-152
1.5
Coilcraft
VLS4012-1R5N1R5
1.5
TDK
4x4x1
LPS4414-152MLx
1.5
Coilcraft
4x4x1.5
1008PS-152Kx
1.5
Coilcraft
4x4x2.5
DO2010-472
4.7
Coilcraft
2x2x1
VLS3012-47M1R0
4.7
TDK
3x3x1
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the two converters allow the use of small
ceramic capacitors with a typical value of 22μF, without having large output voltage under and overshoots
during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage
ripple and are therefore recommended. Refer to for recommended components.
94
APPLICATION INFORMATION
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SLVSA37 – DECEMBER 2009
If ceramic output capacitors are used the capacitor RMS ripple current rating will always meet the
application requirements. Just for completeness the RMS ripple current is calculated as:
Vout
1
Vin ´
L ´ f
2 ´ 3
1IRMSCout = Vout ´
(17)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage
ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused
by charging and discharging the output capacitor:
Vout
ö
1
Vin ´ æ
+ ESR ÷
ç
L ´ ¦
8
Cout
´
´
¦
è
ø
1DVout = Vout ´
(18)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is
dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay
and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
4.1.3
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high
input voltage spikes. The converters need a ceramic input capacitor of 10μF. The input capacitor can be
increased without any limit for better input voltage filtering.
Table 4-2. Capacitors
4.2
22 μF
0805
TDK C2012X5R0J226MT
Ceramic
22 μF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 μF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 μF
0805
TDK C2012X5R0J106M
Ceramic
XTAL OSCILLATOR PCB – GENERAL GUIDELINES
Table 4-3. External Crystal Specifications
EXTERNAL CRYSTAL REQUIREMENTS [TYP CRYSTAL – EPSON MC146]
PARAMETER
DESCRIPTION
FOSC
Nominal crystal resonant frequency
MIN
Frequency Tolerance
ΔF/FOSC
B
Parabolic Temp Co
ESR
Equivalent Series Resistance
CLOAD
Load Capacitance
CSHUNT
Shunt capacitance
PDRIVE
Drive power
TYP
MAX
UNIT
32.768
–20
kHz
20
ppm
0.04×10–6
1/°C2
65
kΩ
7
0.5
Aging
–3
pF
0.8
1.2
pF
0.5
1
μW
3
ppm/Yr
The jitter observed in the OUT32K pin is heavily dependent on the board layout close to the XTAL1 and
XTAL2 pins. The following layout/assembly procedures are recommended :
• Layout a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
APPLICATION INFORMATION
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•
•
•
•
96
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Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the
oscillator pins.
External capacitance is recommended for precision real-time clock applications.
APPLICATION INFORMATION
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4.3
SLVSA37 – DECEMBER 2009
APPLICATION CIRCUIT
4.3.1
Power Path , Charger, ADC, RTC and Ground Plane
0.22µF
1V25
XTAL1
TPS6586x
XTAL2
4.7µF
ADC_REF
AGND2
ANLG1
ANLG2
ANLG3
4.7µF
AGND
AVDD6
2V2
2.2µF
SYSTEM CORE
POWER BUS
2V2
AGND
VSYS
22µF
AGND
SYS
FLTDPPM
+
AC_DC ADAPTER
OUTPUT
-
1µF
GND
AC
1µF
+
USB POWER
-
USB
VIN_CHG
VSM2 or VSYS
RTS
VTSBIAS
GND
BAT
4.7µF
BATTERY
THERMISTOR
TS
RISET
ISET
AGNDn
DGNDn
AGND
ANALOG
GROUND
PLANE
DIGITAL
GROUND
PLANE
AGND
GND
GND
(1)
DGND
POWER GROUND PLANE
SUPPLY GROUND PLANE
GROUND STAR
OONECTION
SEE PCB LAYOUT
GUIDELINES
P1 P2 P3 P4
VIN_CHG should be connected to VSYS when SM2 is not configured as the charger pre-regulator stage
Figure 4-1. Power Path, Charger, ADC, RTC Connections
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Integrated Supplies
VSYS
TPS6586x
VIN_SM0
LSM0
L0
SM0
PGND0
VSM0
1.5µH
10µF
10µF
P0
VIN_SM1
LSM1
L1
SM1
PGND1
VSM1
1.5µH
10µF
10µF
P1
VIN_SM2
LSM2
L2
SM2
PGND2
VSM2
1.5µH
10µF
10µF
330
P2
Supercap
RTC_OUT
1µF
1µF
LDO5
VINLDO23
1µF
VINLDO23
LDO2
LDO3
2.2µF
2.2µF
VINLDO678
VINLDO678
LDO8
LDO6
LDO7
1µF
2.2µF
2.2µF
2.2µF
VINLDO4
VIN_LDO4
LDO4
1µF
2.2µF
VINLDO4
VIN_LDO01
LDO0
LDO1
1µF
2.2µF
2.2µF
VINLDO9
1µF
2.2µF
VLDO9
AGND
VLDO1
VLDO0
VLDO4
VLDO7
VLDO6
VLDO8
VLDO3
VLDO2
VLDO5
VRTC_OUT
(1)
(2)
VIN_SMn pins must be always connected to VSYS .
The supply input pins must be connected to VSYS or to the output of a supply which is powered from VSYS
Figure 4-2. Supply Rail Connections
98
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4.3.3
SLVSA37 – DECEMBER 2009
Display and Peripherals
VRAIL
2K
LED_PWM
TPS6586x
SM3SW
4.7uH
L3
VSYS
SM3
WHITE LEDS
FB3
RFB3
PGND3
ISM3G
PWM
100pF
100pF
33
RFB3A
P3
15
M
VoLDOn
DIGPWM
TO DIGITAL INPUT
DIGPWM2
RED1
RGB LED
GREEN1
BLUE1
RED2
RGB LED
GREEN2
BLUE2
(1)
(2)
(3)
PWM pin shown as driving an external vibrator motor, with vibrator supply connected to LDOn output
VRAIL can be the output of any of the TPS658600 integrated supplies or the SYS pin
1. DIGPWM, DIGPWM2 are push-pull outputs
Figure 4-3. Display and PWM Connections
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4.3.4
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Host Connections
2kW
2kW
2kW
2kW
VI2C
TPS6586x
VIO
SCLK
SDAT
VIO
PSCLK
PSDAT
nINT
100kW
GPIO1
GPIO2
GPIO3
GPIO4
HOST
V32K
32KOUT
CHG_STAT
nNORTC
nNOPOWER
HOST SEQUENCING AND
RESET CONTROL
LDO4EN
SM1EN
SM0EN
SYNCEN
SM0PG
SM1PG
LDO4PG
RESUME
nHOTRST
CNOPOWER
(1)
(2)
(3)
TNOPOWER
Those are generic connections only, see App Notes for host specific connectivity
VIO should be connected to the TPS658600 rail that powers the host I/O domain
VI2C should be connected to 2v2 or to the TPS658600 rail that powers the host I2C engine domain
Figure 4-4. Generic Host and Sequencing Circuit Connections
100
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4.3.5
SLVSA37 – DECEMBER 2009
Sequence Connections
TPS6586xx
V2V2
V2V2
SM1EN
LDO4EN
nCORECTRL
nCORECTRL
V32K
SYNCEN
VSM1
L1
SM1
PGND1
APPLICATION INFORMATION
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4.3.6
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Sequence Timing (TPS658600)
RTC_OU T
2.2V
Power Applied
2.2V
NORTC
RESU ME
2.2V
I N TERN A L
LDO2
1.2V
SM0EN + 2.5ms
SM0
1.8V
SM1
SM1EN + 15m s
3.3V
LDO6
SY N CEN + 2.5m s
2.85V
LDO8
SY N CEN + 2.5m s
LDO0
2.85V
SM1EN + 15m s
LDO1
1.2V
I N TERN A L + 15m s
Power
A p p l i ed
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
Time ( m s)
Figure 4-5. Sequence Timing
102
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
TPS658600ZQZR
PREVIEW
BGA MI
CROSTA
R JUNI
OR
ZQZ
120
2500
TBD
Call TI
Call TI
TPS658600ZQZT
PREVIEW
BGA MI
CROSTA
R JUNI
OR
ZQZ
120
250
TBD
Call TI
Call TI
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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