High Reliability Series Serial EEPROM Series WL-CSP EEPROMs family SPI BUS No.10001JAT06 BR25S128GUZ-W ●Description BR25S128GUZ-W is a 16K×8bit serial EEPROM of SPI BUS interface method. ●Features 1) High speed clock action up to 10MHz (Max.) 2) Wait function by HOLDB terminal 3) Part or whole of memory arrays settable as read only memory area by program 4) 1.7～5.5V single power source action most suitable for battery use 5) 64Byte page write mode useful for initial value write at factory shipment 6) For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1) 7) Auto erase and auto end function at data rewrite 8) Low current consumption At write action (5.0V) : 1.5mA (Typ.) At read action (5.0V) : 1.0mA (Typ.) At standby action (5.0V) : 0.1μA (Typ.) 9) Address auto increment function at read action 10) Write mistake prevention function Write prohibition at power on Write prohibition by command code (WRDI) Write prohibition by WPB pin Write prohibition block setting by status registers (BP1, BP0) Write mistake prevention function at low voltage 11) VCSP35L2 Package 12) Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0 13) Data kept for 40 years 14) Data rewrite up to 1,000,000 times www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Absolute maximum ratings (Ta=25°C) Parameter Symbol Impressed voltage Permissible dissipation Storage temperature range Operating temperature range Terminal voltage Vcc Pd ●Memory cell characteristics (Ta=25°C , Vcc=1.7V～5.5V) Limits Unit -0.3～+6.5 V VCSP35L2 220 ※1 -65～+125 ℃ Topr -40～+85 ℃ － -0.3～Vcc+0.3 ※2 ※1 Degradation is done at 4.5mW, for operation above 25℃. ※2 The Max value of Terminal Voltage is not over 6.5V. Number of data rewrite times ※1 ※1 Data hold years mW Tstg V Limits Parameter ※ 1 Unit Min. Typ. Max. 1,000,000 － － Time 40 － － Year Not 100% TESTED. ●Recommended action conditions Parameter Power source voltage Input voltage Symbol Vcc Limits 1.7～5.5 VIN 0～Vcc Unit V ●Input / output capacity (Ta=25°C, frequency=5MHz) Parameter Input capacity Output capacity ※ 1 ※1 ※1 Symbol Conditions Min. Max. CIN VIN=GND － 8 COUT VOUT=GND － 8 Unit pF Not 100% TESTED. ●Electrical characteristics (Unless otherwise specified, Ta=-40～+85°C, Vcc=1.7～5.5V) Limits Typ. － － － － － － － － Unit Parameter Symbol “H” Input Voltage1 “L” Input Voltage1 “L” Output Voltage1 “L” Output Voltage2 “H” Output Voltage1 “H” Output Voltage2 Input Leakage Current Output Leakage Current VIH1 VIL1 VOL1 VOL2 VOH1 VOH2 ILI ILO Min. 0.7xVcc -0.3 0 0 Vcc-0.2 Vcc-0.2 -1 -1 ICC1 － － 0.5 mA ICC2 － － 1 mA ICC3 － － 2 mA ICC4 － － 1 mA ICC5 － － 1 mA ICC6 － － 1.5 mA ICC7 － － 2 mA ICC8 － － 2 mA ICC9 － － 4 mA ICC10 － － 8 mA ISB － － 2 μA Operating Current Write Operating Current Read Standby Current Max. Vcc+0.3 0.3xVcc 0.4 0.2 Vcc Vcc 1 1 V V V V V V μA μA Conditions 1.7≦Vcc≦5.5V 1.7≦Vcc≦5.5V IOL=2.1mA, 2.5≦Vcc<5.5V IOL=1.0mA, 1.7≦Vcc<2.5V IOH=-0.4mA, 2.5V≦Vcc<5.5V IOH=-100μA, 1.7≦Vcc<2.5V VIN=0～Vcc VOUT=0～Vcc, CSB=Vcc Vcc=1.8V,fSCK=5MHz, tE/W=5ms Byte Write，Page Write Vcc=2.5V,fSCK=10MHz, tE/W=5ms Byte Write，Page Write Vcc=5.5V,fSCK=10MHz, tE/W=5ms Byte Write，Page Write Vcc=1.8V,fSCK=5MHz, SO=OPEN Read, Read Status Register Vcc=2.5V,fSCK=2MHz, SO=OPEN Read, Read Status Register Vcc=2.5V,fSCK=5MHz, SO=OPEN Read, Read Status Register Vcc=2.5V,fSCK=10MHz, SO=OPEN Read, Read Status Register Vcc=5.5V,fSCK=5MHz, SO=OPEN Read, Read Status Register Vcc=5.5V,fSCK=10MHz, SO=OPEN Read, Read Status Register Vcc=5.5V,fSCK=20MHz, SO=OPEN Read, Read Status Register Vcc=5.5V, CSB=Vcc, SCK=SI=Vcc or GND HOLDB=WPB=Vcc, SO=OPEN ○Radiation resistance design is not made www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Block diagram CSB VOLTAGE DETECTION INSTRUCTION DECODE CONTROL CLOCK GENERATION SCK WRITE INHIBITION SI HIGH VOLTAGE GENERATOR INSTRUCTION REGISTER HOLDB WPB SO ADDRESS REGISTER DATA REGISTER Fig.1 14bit ADDRESS DECODER 14bit 131,072 bit EEPROM 8bit R/W AMP 8bit Block diagram ●Operating timing characteristics (Ta=-40～+85°C, unless otherwise specified, load capacity CL=30pF) 1.7≦Vcc<2.5V 1.8≦Vcc<2.5V 2.5≦Vcc≦5.5V Parameter Symbol Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. SCK frequency fSCK 3 5 10 MHz SCK high time tSCKWH 125 80 40 ns SCK low time tSCKWL 125 80 40 ns CSB high time tCS 250 90 40 ns CSB setup time tCSS 100 60 30 ns CSB hold time tCSH 100 60 30 ns SCK setup time tSCKS 100 50 20 ns SCK hold time tSCKH 100 50 20 ns SI setup time tDIS 30 20 10 ns SI hold time tDIH 50 20 10 ns Data output delay time tPD 125 80 40 ns Output hold time tOH 0 0 0 ns Output disable time tOZ 200 80 40 ns HOLDB setting setup time tHFS 100 0 0 ns HOLDB setting hold time tHFH 100 20 10 ns HOLDB release setup time tHRS 100 0 0 ns HOLDB release hold time tHRH 100 20 10 ns Time from HOLDB to output High-Z tHOZ 100 80 40 ns Time from HOLDB to output change tHPD 100 80 40 ns ※1 SCK rise time 1 1 1 μs tRC ※1 SCK fall time tFC 1 1 1 μs ※1 OUTPUT rise time tRO 100 50 40 ns ※1 OUTPUT fall time 100 50 40 ns tFO Write time tE/W 5 5 5 ms ※ 1 NOT 100% TESTED www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ● 1 2 3 Pin assignment and description A1 B1 C1 D1 NC SI GND NC A2 B2 C2 D2 Terminal name CSB SO Input/Output Input Output WPB Input Input Input SCK HOLDB SO WPB A3 B3 C3 D3 NC Vcc CSB NC GND SI SCK A B C D HOLDB Input Vcc - Function Chip select input Serial data output Write protect input Write command is prohibited Write status register command is prohibited All input / output reference voltage, 0V Start bit, ope code, address, and serial data input Serial clock input Hold input Command communications may be suspended temporarily (HOLD status) Power source to be connected Fig.2 Pin assignment diagram ●Sync data input / output timing tCS tCSS tCS CSB tSCKS tSCKWL tRC tSCKWH tFC tCSH tSCKH CSB SCK SCK tDIS tDIH SI SI High-Z SO Fig.4 Fig.3 Input timing SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB CSB tPD tOH tRO,tFO tOZ High-Z SO Input / Output timing SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB. "H" "L" tHFS tHFH tHRS tHRH SCK tDIS SI n n+1 tHOZ SO Dn+1 Dn High-Z n-1 tHPD Dn Dn-1 HOLDB Fig.5 HOLD timing ●AC measurement conditions Parameter Load capacity Input rise time Input fall time Input voltage Input / Output judgment voltage www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Symbol CL - Min. - Limits Typ. Max. 30 50 50 0.2Vcc/0.8Vcc 0.3Vcc/0.7Vcc 4/16 Unit pF ns ns V V 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Characteristic data (The following characteristic data are Typ. Values.) 6 6 Ta=-40℃ Ta=25℃ Ta=85℃ 5 SPEC 4 VIL[V] VIH[V] 4 3 3 2 2 1 1 0.6 SPEC 0.4 SPEC 0.2 0 0 0 1 2 3 Vcc[V] 4 5 0 0 6 Ta=-40℃ Ta=25℃ Ta=85℃ 0.8 VOL1[V] 5 1 Ta=-40℃ Ta=25℃ Ta=85℃ 1 2 3 Vcc[V] 4 5 6 0 1.5 2.5 1 2.4 SPEC 2.3 SPEC 0.4 0.8 1.2 1 2 4 5 6 0 SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 5 6 Fig.11 Output leak current ILO(SO) ISB[μA] 6 Ta=-40℃ Ta=25℃ Ta=85℃ 3 4 SPEC 2 1 2 0 0 0 0 1 2 3 Vcc[V] 4 5 6 -1 0 Fig.12 Current consumption at WRITE operation ICC3 1 2 3 Vcc[V] 4 5 6 0 SPEC 100 tSCKWH [ns] SPEC 10 SPEC SPEC 1 1 2 3 Vcc[V] 4 5 60 SPEC 20 20 2 3 Vcc[V] 4 5 0 6 Fig.16 SCK high time tSCKWH SPEC 100 50 80 60 1 2 3 Vcc[V] 4 5 6 Fig.18 CSB high time tCS www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6 SPEC SPEC 20 0 0 0 5 60 40 SPEC 20 0 4 Ta=-40℃ Ta=25℃ Ta=85℃ 100 SPEC 40 SPEC 3 Vcc[V] SPEC Ta=-40℃ Ta=25℃ Ta=85℃ tCSH[ns] tCSS[ns] 100 2 Fig.17 SCK low time tSCKWL 80 150 1 120 SPEC SPEC SPEC 0 1 120 200 60 40 Fig.15 SCK frequency fSCK Ta=-40℃ Ta=25℃ Ta=85℃ 6 SPEC 80 40 0 250 5 Ta=-40℃ Ta=25℃ Ta=85℃ 100 SPEC 80 6 300 4 120 0 0 3 Vcc[V] SPEC 120 100 2 140 Ta=-40℃ Ta=25℃ Ta=85℃ tSCKWL [ns] Ta=-40℃ Ta=25℃ Ta=85℃ 1 Fig.13 Current Consumption at READ operation ICC10 Fig.14 Current Consumption at standby operation IS 140 1000 fSCK[MHz] 3 4 VOUT[V] 4 1 tCS[ns] 2 SPEC 8 ICC10[mA] 2 1 5 DATA=00h 3 ICC3[mA] 3 Vcc[V] 10 DATA=00h Ta=-40℃ Ta=25℃ Ta=85℃ Ta=-40℃ Ta=25℃ Ta=85℃ Fig.10 Input leak current ILI(CSB,SCK,SI,HOLDB,WPB) 4 6 -0.5 0 IOH[mA] Fig.9 "H" output voltage VOH1 (Vcc=2.5V) 5 0 -0.5 0 4 SPEC 0.5 0 2.2 3 IOL[mA] Fig.8 "L" output voltage VOL1 (Vcc=2.5V) 1 Ta=-40℃ Ta=25℃ Ta=85℃ 0.5 Ta=-40℃ Ta=25℃ Ta=85℃ 2 1.5 ILO[μA] 2.6 ILI[μA] VOH1[V] Fig.6 "H" input voltage VIH(CSB,SCK,SI,HOLDB,WPB) Fig.7 "L" input voltage VIL(CSB,SCK,SI,HOLDB,WPB) 1 0 1 2 3 Vcc[V] 4 5 Fig.19 CSB setup time tCSS 5/16 6 0 1 2 3 Vcc[V] 4 5 6 Fig.20 CSB hold time tCSH 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Characteristic data (The following characteristic data are Typ. Values.) 60 Ta=-40℃ Ta=25℃ Ta=85℃ 40 SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 40 tDIH[ns] 30 tDIS[ns] 140 SPEC 50 SPEC 20 30 20 SPEC 0 SPEC 20 0 0 1 2 3 Vcc[V] 4 5 1 2 3 Vcc[V] 6 Fig.21 SI setup time tDIS 4 5 6 0 0 SPEC 150 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 90 60 tHRH [ns] tHFH [ns] SPEC 60 40 SPEC 0 1 2 3 Vcc[V] 4 5 6 SPEC 10 1 2 3 Vcc[V] 4 5 6 0 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 80 SPEC 100 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 20 1 2 3 Vcc[V] 4 5 60 SPEC 60 40 40 20 20 4 5 6 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC SPEC 0 0 6 3 Vcc[V] 80 0 0 SPEC 100 tRO [ns] tHPD [ns] SPEC 40 2 Fig.26 HOLDB release hold time tHRH 80 60 1 120 120 SPEC Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 30 Fig.25 HOLDB setting hold time tHFH Fig.24 Output disable time tOZ 100 6 -10 0 120 5 50 SPEC 0 0 4 70 SPEC 20 30 SPEC 110 80 90 3 Vcc[V] Fig.23 Data output delay time ｔPD Ta=-40℃ Ta=25℃ Ta=85℃ 100 120 2 130 120 180 1 Fig.22 SI hold time tDIH 210 tOZ [ns] SPEC 60 0 -10 tHOZ [ns] 80 40 10 0 Fig.27 Time from HOLDB to output High-Z tHOZ 1 2 3 Vcc[V] 4 5 6 Fig.28 Time from HOLDB to output change tHPD 0 1 2 3 Vcc[V] 4 5 6 Fig.29 Output rise time tRO 8 120 SPEC 100 Ta=40℃ Ta=25℃ Ta=-40℃ Ta=25℃ Ta=85℃ 6 SPEC tE/W[ms] 80 tFO [ns] Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 100 SPEC 10 SPEC 120 tPD [ns] 50 SPEC 60 SPEC 40 4 2 20 0 0 1 2 3 Vcc[V] 4 5 Fig.30 Output fall time tFO www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6 0 0 1 2 3 Vcc[V] 4 5 6 Fig.31 Write cycle time tE/W 6/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Features ○Status registers This IC has status register. The status register expresses the following parameters of 8 bits. BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are valid even when power source is turned off. Rewrite characteristics and data hold time are same as characteristics of the EEPROM. WEN can be set by write enable command and write disable command. WEN becomes write disable status when power source is turned off. R/B is for write confirmation, therefore cannot be set externally. The value of status register can be read by read status register command. 1. Contexture of status register Product number bit 7 BR25S128GUZ-W bit Memory location WPEN EEPROM BP1 BP0 EEPROM WEN registers R/B registers bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 BP1 BP0 WEN R/B WPEN Function WPB pin enable / disable designation bit WPEN=0=invalid WPEN=1=valid EEPROM write disable block designation bit Write and write status register write enable / disable status confirmation bit WEN=0=prohibited WEN=1=permitted Write cycle status (READY / BUSY) status confirmation bit R/B=0=READY R/B=1=BUSY 2. Write disable block setting Write disable block BP1 BP0 BR25S128GUZ-W 0 0 None 0 1 3000h-3FFFh 1 0 2000h-3FFFh 1 1 0000h-3FFFh ○WPB pin By setting WPB=LOW, write command is prohibited. And the write command to be disabled at this moment is WRSR. However, when write cycle is in execution, no interruption can be made. Product number WRSR WRITE BR25S128GUZ-W Prohibition possible but WPEN bit “1” Prohibition impossible ○HOLDB pin By HOLDB pin, data transfer can be interrupted. When SCK=”0”, by making HOLDB from “1” into”0”, data transfer to EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Command mode Command Contents Ope code WREN WRDI READ WRITE RDSR WRSR Write enable command Write disable command Read command Write command Read status register command Write status register command 0000 0000 0000 0000 0000 0000 0110 0100 0011 0010 0101 0001 ●Timing chart 1. Write enable (WREN) / disable (WRDI) command WREN (WRITE ENABLE): Write enable WRDI (WRITE DISABLE): Write disable CSB CSB SCK 0 SI SO 1 0 2 0 3 0 4 0 0 5 1 6 7 1 SCK 0 1 2 3 4 5 7 6 0 SI 0 0 0 0 0 1 0 0 High-Z High-Z SO Fig.32 Write enable command Fig.33 Write disable command This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is set to write disable status by write disable command. As for these commands, set CSB LOW, and then input the respective ope codes. The respective commands are accepted at the 7-th clock rise. Even with input over 7 clocks, command becomes valid. When to carry out write command, it is necessary to set write enable status by the write enable command. If write command is input in the write disable status, the command is cancelled. And even in the write enable status, once write command is executed, it gets in the write disable status. After power on, this IC is in write disable status. 2. Read command (READ) ～ ～ ～ ～ CSB ～ ～ 0 1 2 3 4 5 6 7 8 9 10 11 23 ～ ～ SCK 24 30 31 ～ ～ 0 0 0 0 0 1 1 * * A13 A12 A1 A0 ～ ～ 0 ～ ～ SI ～ ～ High-Z D7 D6 ～ ～ ～ ～ SO D2 D1 D0 Fig.34 Read command By read command, data of EEPROM can be read. As for this command, set CSB LOW, then input address after read ope code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 23-th clock, and from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data of the most significant address, by continuing increment read, data of the most insignificant address is read. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/16 2010.01 - Rev.A Technical Note BR25128GUZ-W 3. Write command (WRITE) 0 2 0 3 0 4 0 5 6 0 7 1 8 0 * 11 A12 10 9 A13 * 23 A1 24 A0 D7 30 ～ ～ ～ ～ D6 D2 D1 31 D0 ～ ～ SO 0 1 ～ ～ ～ ～ SI 0 ～ ～ SCK ～ ～ ～ ～ ～ ～ CSB High-Z ＊=Don't Care Fig.35 Write command By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time of tE/W (Max 5ms). During tE/W, other than read status register command is not accepted. Set CSB HIGH between taking the last data (D0) and rising the next SCK clock. At the other timing, write command is not executed, and this write command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without setting CSB HIGH, 2byte or more data can be written for one tE/W. Up to 64 arbitrary bytes can be written. In page write, the insignificant 6 bit of the designated address is incremented internally at every time when data of 1 byte is input and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten. 4. Read status register command (RDSR) CSB SCK SI SO 0 0 1 0 2 3 0 0 4 0 5 0 6 0 7 8 1 9 10 bit7 bit6 bit5 WPEN * * 11 12 bit4 bit3 13 bit2 BP1 BP0 * 14 15 bit1 bit0 * * High-Z *=Don't care Fig.36 Write status register Write status register command can write data of status register. The data can be written by this command are 3 bits, that is, WPEN(bit7), BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As for this command, set CSB LOW, and input ope code of write status register, and input data. Then, by making CSB HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise, set CSB HIGH between taking the last data bit (bit0) and the next SCK clock rising. At the other timing, command is cancelled. Write disable block is determined by BP1 BP0, and the block can be selected from 1/4 , 1/2, and entire of memory array (Refer to the write disable block setting table.). To the write disabled block, write cannot be made, and only read can be made. CSB SCK SI SO 0 0 1 0 2 0 3 0 4 0 High-Z Fig.37 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6 5 1 0 7 8 9 10 11 12 13 14 15 1 bit7 bit6 bit5 bit4 WPEN 0 0 0 bit3 bit2 bit1 bit0 BP1 BP0 WEN R/B Read status register command 9/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●WPB cancel valid area WPB is normally fixed to “H” or “L” for use, but when WPB is controlled so as to cancel write status register command, pay attention to the following WPB valid timing. While write status register command is executed, by setting WPB = “L” in cancel valid area, command can be cancelled. The area from command ope code to CSB rise at internal automatic write start becomes the cancel valid area. However, once write is started, by any input write cycle cannot be cancelled. WPB input becomes Don’t Care, and cancellation becomes invalid. SCK 6 7 Ope Code 15 tE/W Data write time Data Valid (WRSR command is reset by WPB=L) Fig.38 16 Invalid WPB valid timing (At inputting WRSR command) ●HOLDB pin By HOLDB pin, command communication can be stopped temporarily (HOLD status). The command communications are carried out when the HOLDB pin is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the HOLDB pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release the HOLD status, set the HOLDB pin HIGH when SCK=LOW. After that, communication can be restarted from the point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, keep CSB LOW. When it is set CSB=HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Method to cancel each command ○READ, RDSR ・Method to cancel : cancel by CSB = “H”. Ope code 8 bits Address Data Ope code 8 bits 8 bits Cancel available in all areas of read mode Data 8 bits Cancel available in all areas of rdsr mode Fig.39 READ cancel valid timing Fig.40 RDSR cancel valid timing ○WRITE、PAGE WRITE a：Ope code or address input area Cancellation is available by CSB=”H”. b：Data input area (D7～D1 input area) Cancellation is available by CSB=”H”. c：Data input area (D0 area) In this area, cancellation is not available. When CSB is set HIGH, write starts. By continuing to input SCK clock without rising CSB, the command will be page write command. In page write mode, there is write enable area at every 8 clocks. d：tE/W area In the area c, by rising CSB, write starts. While writting, by any input, cancellation cannot be made. Ope code Address 8bits a Data tE/W 8bits b d c SCK SI D7 D6 D5 D4 D3 D2 D1 D0 c b Fig.41 WRITE cancel valid timing Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more. ○WRSR a：From ope code to 15-th clock rise Cancellation is available by CSB=”H”. b：From 15-th clock rise to 16-th clock rise (write enable area) In this area, cancellation is not available. When CSB is set HIGH, write starts. c：After 16-th clock rise. Cancellation is available by CSB=”H”. However, if write starts (CSB is rised) in the area b, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made. 14 SCK 15 D1 SI b c tE/W Data 8 bits 17 D0 a Ope code 16 8 bits a c b Fig.42 WRSR cancel valid timing Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more. ○WREN/WRDI a：From ope code to 7-th clock rise, cancellation is available by CSB = “H”. b：Cancellation is not available 7-th clock. 6 SCK 7 8 Ope code 8 bits a b Fig.43 WREN/WRDI cancel valid timing www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●I/O peripheral circuits In order to realize stable high speed operations, pay attention to the following input / output pin conditions. ○Input pin pull up, pull down resistance When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller VOL, IOL with considering VIL characteristics of this IC. 1. Pull up resistance RPU≧ Microcontroller IOLM VOLM VILE “L” output VOLM≦ EEPROM RPU “L” input VCC－VOLM IOLM VILE ･･･① ･･･② Example) When Vcc=5V, VILE=1.5V, VOLM=0.4V, IOLM=2mA, from the equation ①, 5－0.4 RPU≧ Fig.44 Pull up resistance ∴RPU≧ 2×10-3 2.3[kΩ] With the value of Rpu to satisfy the above equation, VOLM becomes 0.4V or lower, and with VILE (=1.5V), the equation ② is also satisfied. ・VILE :EEPROM VIL specifications ・VOLM :Microcontroller VOL specifications ・IOLM :Microcontroller IOL specifications And, in order to prevent malfunction or erroneous write at power ON/OFF, be sure to make CSB pull up. 2.Pull down resistance Microcontroller EEPROM VOHM “H” output RPD≧ VIHE IOHM Fig.45 RPD “H” input VOHM≧ VOHM IOHM ･･･③ VIHE ･･･④ Example) When VCC=5V, VOHM=VCC-0.5V, IOHM＝0.4mA, VIHE=VCC×0.7V, from the equation③, Pull down resistance RPD≧ ∴RPD≧ 5－0.5 -3 0.4×10 11.3[kΩ] Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting Vcc/GND level amplitude of signal, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC / *1 0.2Vcc is input, operation speed becomes slow. In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level. (★1 In this case, guaranteed value of operating timing is guaranteed.) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ○SO load capacity condition Load capacity of SO output pin affects upon delay characteristic of SO output (Data output delay time, time from HOLDB to High-Z, Output rise time, Output fall time.). In order to make output delay characteristic into better, make SO load capacity small. EEPROM SO CL Fig.46 SO load capacity of data output delay time tPD ○Other cautions Make the each wire length from the microcontroller to EEPROM input pin same length, in order to prevent setup / hold violation to EEPROM, owing to difference of wire length of each input. ●Equivalent circuit ○Output circuit SO OEint. Fig.47 SO output equivalent circuit ○Input circuit RESETint. CSB Fig.48 CSB input equivalent circuit SCK SI Fig.49 SCK input equivalent circuit Fig.50 SI input equivalent circuit WPB HOLDB Fig.51 HOLDB input equivalent circuit www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Fig.52 WPB input equivalent circuit 13/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Notes on power ON/OFF ○At standby Set CSB “H”, and be sure to set SCK, SI input “L” or “H”. Do not input intermediate electric potantial. ○At power ON/OFF When Vcc rise or fall, set CSB=”H” (=Vcc). When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, erroneous write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all inputs are canceled.) Vcc CSB Good example Bad example Fig.53 CSB timing at power ON/OFF (Good example) CSB terminal is pulled up to Vcc. At power OFF, take 10ms or more before supply. If power is turned on without observing this condition, the IC internal circuit may not be reset. (Bad example) CSB terminal is “L” at power ON/OFF. In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction or erroneous write owing to noises and the likes. Even when CSB input is High-Z, the status becomes like this case. ○Operating timing after power ON As shown in Fig.55, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read at SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status. Even if CSB is fallen at SCK=”H”, SI status is not read at that edge. CSB Command start here. SI is read. SCK 0 1 2 SI Fig.54 Operating timing ○At power on malfunction preventing function This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes. tR Vcc tOFF Recommended conditions of tR, tOFF, Vbot tR tOFF Vbot Vbot 0 10ms or below 10ms or higher 0.3V or below 100ms or below 10ms or higher 0.2V or below Fig.55 Rise waveform ○Low voltage malfunction preventing function LVCC (Vcc-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Noise countermeasures ○Vcc noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1μF) between IC Vcc and GND. At that time, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. ○SCK noise When the rise time of SCK (tRC) is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time of SCK (tRC) 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible. ○WPB noise During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur and forcible cancellation may result. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same manner, a Schmitt trigger circuit is built in CSB input, SI input and HOLDB input too. ●Cautions on use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is higher than that of GND terminal. (5) Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal short circuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/16 2010.01 - Rev.A Technical Note BR25128GUZ-W ●Selection of order type B R 2 Part No. 5 S 1 Operating Temperature / Power source voltage BUS Type 25:SPI 2 8 G U Capacity Package 128=128Kbit GUZ:VCSP35L2 Z - W E Double cell 2 Packaging and forming specification E2: Embossed tape and reel S: -40℃~ +85℃ / 1.7V~5.5V ●Package specifications VCSP35L2(BR25S128GUZ-W) 2.00±0.05 0.4MAX 0.10±0.05 2.63±0.05 <Tape and Reel information> 1PIN MARK A 3000pcs E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 0.565±0.05 12-φ0.25±0.05 0.05 A B Embossed carrier tape Quantity Direction of feed S 0.06 S Tape B C B A 0.50±0.05 1 2 3 P=0.5×3 D 1pin P=0.5×2 Reel (Unit : mm) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/16 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.01 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. 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ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A