High Reliability Series Serial EEPROM Series
WL-CSP EEPROM family
I2C BUS
No.10001EAT07
BU9889GUL-W
●Description
2
BU9889GUL-W is a serial EEPROM of I C BUS interface method.
●Features
2
1) Completely conforming to the world standard I C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) 1k words×8 bits architecture 8kbit serial EEPROM.
3) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
4) 1.7～5.5V single power source action most suitable for battery use.
5) FAST MODE 400kHz at 1.7～5.5V
6) Page write mode useful for initial value write at factory shipment.
7) Auto erase and auto end function at data rewrite.
8) Low current consumption
At write operation (5V)
: 0.5mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1µA (Typ.)
9) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
10) WLCSP6pin compact package
11) Data rewrite up to 100,000 times
12) Data kept for 40 years
13) Noise filter built in SCL / SDA terminal
14) Shipment data all address FFh
●Absolute maximum ratings (Ta=25℃)
Parameter
symbol
Limits
Unit
Impressed voltage
VCC
-0.3+6.5
V
Permissible dissipation
Pd
220*1
mW
Storage temperature range
Tstg
-65+125
℃
Action temperature range
Topr
-40+85
℃
-
-0.3～Vcc+1.0
V
Terminal voltage
*1 When using at Ta=25℃ or higher, 2.2mW to be reduced per 1℃
●Memory cell characteristics (Ta=25℃, Vcc=1.7～5.5V)
Limits
Parameter
Min.
Typ.
Number of data rewrite times *1
Data hold years *1
Max.
Unit
100,000
-
-
Times
40
-
-
Years
*1 Not 100% TESTED
●Recommended operating conditions
Parameter
Symbol
Limits
Power source voltage
Vcc
1.7～5.5
Input voltage
VIN
0～Vcc
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1/17
Unit
V
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Electrical characteristics
Parameter
Symbol
Limits
Min
Typ.
Max.
Unit
Condition
"H" Input Voltage1
VIH1
0.7Vcc
-
Vcc+1.0
V
"L" Input Voltage1
VIL1
-0.3
-
0.3Vcc
V
"L" Output Voltage1
VOL1
-
-
0.4
V
IOL=3.0mA , 2.5V≦Vcc≦5.5V (SDA)
"L" Output Voltage2
VOL2
-
-
0.2
V
IOL=0.7mA , 1.7V≦Vcc≦2.5V (SDA)
Input Leakage Current
ILI
-1
-
1
μA
VIN=0～Vcc
Output Leakage Current
ILO
-1
-
1
μA
VOUT=0～Vcc (SDA)
ICC1
-
-
2.0
mA
ICC2
-
-
0.5
mA
ISB
-
-
2.0
μA
Vcc=5.5V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write
Vcc=5.5V , fSCL =400kHz
Random read, Current read, Sequential read
Vcc=5.5V , SDA・SCL=Vcc
A2=GND, WP=GND
Current consumption at action
Standby Current
○Radiation resistance design is not made.
●Action timing characteristics
Parameter
SCL Frequency
Symbol
fSCL
Limits
Min.
Typ.
Max.
-
-
400
Unit
kHz
Data clock "High" time
tHIGH
0.6
-
-
μs
Data clock "Low" time
tLOW
1.2
-
-
μs
tR
-
-
0.3
μs
tF
-
-
0.3
μs
tHD:STA
0.6
-
-
μs
Start condition setup time
tSU:STA
0.6
-
-
μs
Input data hold time
tHD:DAT
0
-
-
ns
Input data setup time
SDA, SCL rise time
SDA, SCL fall time
*1
*1
Start condition hold time
tSU:DAT
100
-
-
ns
Output data delay time
tPD
0.1
-
0.9
μs
Output data hold time
tDH
0.1
-
-
μs
Stop condition data setup time
tSU:STO
0.6
-
-
μs
Bus release time before transfer start
tBUF
1.2
-
-
μs
Internal write cycle time
tWR
-
-
5
ms
tI
-
-
0.1
μs
tHD:WP
0
-
-
ns
WP setup time
tSU:WP
0.1
-
-
μs
WP valid time
tHIGH:WP
1.0
-
-
μs
Noise removal valid period (SDA,SCL terminal)
WP hold time
*1 : Not 100% TESTED
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© 2010 ROHM Co., Ltd. All rights reserved.
2/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Sync data input/output timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
DATA(1)
tHD:DAT
SDA
(入力)
(Input)
D1
SDA
tPD
tBUF
DATA(n)
D0
ACK
ACK
tDH
SDA
(出力)
(Output)
ｔWR
ストップコンディション
Stop
condition
WP
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tSU：WP
Fig.1-(a) Sync data input / output timing
ｔHD：WP
Fig.1-(d) WP timing at write execution
SCL
tSU:STA
tHD:STA
tSU:STO
tWR
SCL
SDA
DATA(n)
DATA(1)
START BIT
STOP BIT
SDA
Fig.1-(b) Start - stop bit timing
D1
D0
ACK
ACK
tHIGH:WP
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first DATA(1),
to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under
access is not guaranteed, therefore write it once again.
SCL
SDA
D0
ACK
WRITE DATA(n)
Fig.1-(e) WP timing at write cancel
tWR
STOP
CONDITION
START
CONDITION
Fig.1-(c) Write cycle timing
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© 2010 ROHM Co., Ltd. All rights reserved.
3/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Block diagram
Vcc
8Kｂｉｔ ＥＥＰＲＯＭ ARRAY
GND
8bit
10bit
ADDRESS
DECODER
SLAVE、WORD
10bit
DATA
ADDRESS REGISTER
START
WP
REGISTER
STOP
SCL
CONTROL LOGIC
A2
ACK
SDA
Vcc LEVEL DETECT
HIGH VOLTAGE GEN.
Fig.2 Block diagram
●Pin assignment and description
○ ○ ○
○ ○ ○
B
A
B1
B2
B3
SDA
GND
A2
A1
A2
A3
SCL
WP
VCC
1
2
Terminal
name
Input/
Output
A2
Input
GND
-
SDA
Input /
Output
SCL
Input
Serial clock input
WP
Input
Write protect terminal
Vcc
-
3
BU9889GUL-W (BOTTOM VIEW)
Function
Slave address setting
Reference voltage of all input / output, 0V.
Slave and word address,
Serial data input serial data output
Connect the power source.
●Characteristic data (The following values are Typ. ones.)
6
4
3
SPEC
2
1
0
1
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
SPEC
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
0
1
2
3
4
5
0.6
0.4
SPEC
0.2
0
6
0
SUPPLY VOLTAGE : Vcc(V)
Fig.3 'H'
input
voltage VIHIH
Fig.3 'H'
input
voltage V
(A2,SCL,SDA,WP)
(A2,SCL,SDA,WP)
0.4
SPEC
0.2
0
OUTPUT LEAK CURRENT : ILO(uA)
INPUT LEAK CURRENT : ILI(uA)
0.8
SPEC
1
0.8
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
0
0
1
2
3
4
5
L OUTPUT CURRENT : IOL(mA)
6
Fig.6
'L' output
Fig.6 'L'
output voltage
voltage VVOLOL-I-IOL
OL(Vcc=2.5V)
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© 2010 ROHM Co., Ltd. All rights reserved.
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc(V)
Fig.7
Input leak
Fig.7 Input
leakcurrent
currentLII ILI
(A2,SCL,WP)
(A2,SCL,WP)
4/17
6
2
3
4
5
6
7
L OUTPUT CURRENT : IOL(mA)
8
Fig.5'L' 'L'
output
voltage
Fig.5
output
voltage
VOLV-OL- IOL
(Vcc=1.7V)
I (V
1 7V)
1.2
1.2
Ta=-40℃
Ta=25℃
Ta=85℃
1
Fig.4 'L'
input
voltage VILIL
Fig.4 'L'
input
voltage V
(A2,SCL,SDA,WP)
(A2,SCL,SDA,WP)
1
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0
0
L OUTPUT VOLTAGE : VOL(V)
L OUTPUT VOLTAGE : VOL(V)
Ta=-40℃
Ta=25℃
Ta=85℃
5
L INPUT VOLTAGE : VIL(V)
H INPUT VOLTAGE : VIH(V)
6
SPEC
1
0.8
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
ILO (SDA)
Fig.8
Output leak
Fig.8 Output
leakcurrent
current
I (SDA)
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Characteristic data (The following values are Typ. ones.)
2.5
0.6
1.5
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0.5
0.4
Ta=-40℃
Ta=25℃
Ta=85℃
0.3
0.2
0.1
0
1
2
3
4
5
Fig.9 Current consumption at WRITE operation ICC1
(fscl=400kHz)
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
0
SPEC
100
Ta=-40℃
Ta=25℃
Ta=85℃
10
1
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
4
3
Ta=-40℃
Ta=25℃
Ta=85℃
2
1
Fig.12 SCL frequency fSCL
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
3
Ta=-40℃
Ta=25℃
Ta=85℃
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
3.9
2.9
Ta=-40℃
Ta=25℃
Ta=85℃
1.9
SPEC
0.9
0
6
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.16 Start Condition Setup Time tSU :
STA
STA
SPEC
0
-50
Ta=-40℃
Ta=25℃
Ta=85℃
-200
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
300
200
SPEC
100
0
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-200
6
0
Fig.18 Input Data Hold Time
ｔHD : DAT(LOW）
OUTPUT DATA DELAY TIME : tPD(us)
Ta=-40℃
Ta=25℃
Ta=85℃
3
SPEC
2
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
1
SPEC
-50
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-150
-200
0
1
6
Fig.21 'L' Data output delay time tPD0
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2
3
4
5
6
Fig.17 Input Data Hold Time
tHD : DAT（HIGH）
300
200
SPEC
100
0
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-200
0
6
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.20 Input Data setup time
tSU : DAT(LOW)
Fig.19 Input Data Setup Time
ｔSU: DAT(HIGH)
4
6
0
4
5
BUS OPEN TIME
BEFORE TRANSMISSION : tBUF(us)
0
2
3
4
5
SUPPLY VOLTAGE : Vcc（V）
Fig.14 Data clock Low Period tLOW
INPUT DATA SET UP TIME : tSU : DAT(ns)
INPUT DATA SET UP TIME : tSU: DAT(ns)
50
-150
1
SUPPLY VOLTAGE : Vcc(V)
Fig.15 Start Condition Hold Time tHD :
-100
1
50
4.9
-0.1
0
1
Ta=-40℃
Ta=25℃
Ta=85℃
2
0
INPUT DATA HOLD TIME : tHD: STA(ns)
START CONDITION
SET UP TIME : tSU:STA(uA)
4
0
3
6
5.9
SPEC
2
SPEC
4
Fig.13 Data clock High Period tHIGH
5
6
0
0
6
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
5
SPEC
0
0.1
0
1
Fig.11 Stanby operation ISB
ＤＡＴＡ CLK L TIME : tLOW(us)
DATA CLK H TIME : tHIGH(uA)
SCL FREQUENCY : fｓｃｌ（ｋHZ）
0.5
5
1000
Ta=-40℃
Ta=25℃
Ta=85℃
1
Fig.10 Current consumption at READ operation ICC2
(fscl=400kHz)
10000
START CONDITION HOLD TIME : tHD : STA(us)
1.5
0
0
6
SUPPLY VOLTAGE : Vcc(V)
INPUT DATA HOLD TIME : tHD :DAT(ns)
2
0
0
OUTPUT DATA DELAY TIME : tPD(us)
SPEC
STANBY CURRENT : ISB(uA)
CURRENT CONSUMPTION
AT READING : Icc2(mA)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2
1
2.5
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
3
SPEC
2
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Fig.22 'H' Data output delay time ｔPD1
5/17
6
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
2
SPEC
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.23 BUS open time before transmission ｔ
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Characteristic data (The following values are Typ. ones.)
4
3
2
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0.8
NOISE REDUCTION
EFECTIVE TIME : tl(SCL L)(us)
5
1
Ta=-40℃
Ta=25℃
Ta=85℃
0.6
0.4
0.2
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
0
6
Fig.24 Internal writing cycle time ｔWR
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
0.2
SPEC
0.1
0
0.3
0.2
SPEC
0.1
0
0.5
0.4
0.3
Ta=-40℃
Ta=25℃
Ta=85℃
0.2
SPEC
0.1
6
Fig.27 Noise resuction efecctive time ｔｌ（SDA
H）
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
SPEC
0.1
0
-0.1
Ta=-40℃
Ta=25℃
Ta=85℃
-0.2
-0.3
-0.4
-0.5
-0.6
0
2
4
SUPPLY VOLATGE : Vcc(V)
1
Fig.26 Noise reduction efective time tl（SCL
L）
0.2
WP SET UP TIME : tSU : WP(us)
NOISE REDUCTION
EFFECTIVE TIME : tl(SAD L)(us)
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.3
Fig.25 Noise reduction efection time tl（SCL
）
0.6
0.4
0.4
6
0.6
0.5
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0
0
0
NOISE REDUCTION
EFECTIVE TIME : tl(SDA H)(us)
0.6
1
SPEC
NOISE REDUCTION
EFECTIVE TIME : tl(SCL H) (us)
INTERNAL WRITING
CYCLE TIME : tWR(ms)
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.28 Noise reduction efective time tl（SDA L）
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.29 WP setup time tSU : WP
WP EFFECTIVE TIME : tHIGH : WP(us)
1.2
SPEC
1
0.8
0.6
0.4
Ta=-40℃
Ta=25℃
Ta=85℃
0.2
0
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc(V)
6
Fig.30 WP efective time tHIGH : WP
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6/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●I2C BUS communication
○I2C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
2
I C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
DATA
8
1-7
9
ACK
DATA
Fig.31 Data transfer timing
8
9
ACK
P
STOP
condition
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of
read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Following a START condition, the master output the slave address to be accessed.
・The most significant four bits of the slave address are the “device type indentifier,” for this device it is fixed as “1010”.
・The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2
input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin.
Using this address scheme, up to two devices may be connected to the bus.
・The next two bits (P1, P0) are used by the master to select four 256 word page of memory.
P1, P0 set to “0” “0” ･･･ 1page (000～0FF)
P1, P0 set to “0” “1” ･･･ 1page (100～1FF)
P1, P0 set to “1” “0” ･･･ 1page (200～2FF)
P1, P0 set to “1” “1” ･･･ 1page (300～3FF)
・The last bit of the stream (R/W … READ/WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R/W set to “0” ･･･ WRITE (including word address input of Random Read)
R/W set to “1” ･･･ READ
1 0 1
0
A2
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P1
P0
7/17
―
R/W
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
WA
7
1 0 1 0 A2 P1 P0
S
T
O
P
DATA
WA
0
D7
D0
A
C
K
R A
/ C
W K
A
C
K
Fig.32 Byte write cycle
S
T
A
R
T
SDA
L IN E
W
R
I
T
E
SLAVE
ADDRESS
P1 P0
WA
7
1 0 1 0 A 2A 1A 0
注)
W ORD
A D D R E S S (n )
D A TA (n )
WA
0
R A
/ C *1
W K
D7
D A TA (n +1 5 )
D0
A
C
K
S
T
O
P
*2
D0
A
C
K
A
C
K
Fig.33 Page write cycle
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 16 bytes
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment of "Notes on page write cycle" in P9/17.)
・As for page write command, after page select bit(PS) of slave address is designated arbitrarily, by continuing data input of
2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.
○Notes on write cycle continuous input
At STOP (s top bit )
write starts.
S
T
A
R
T
SDA
LINE
SL AVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS（ｎ）
WA
7
1 0 1 0 A2 P1 P0
R A
/ C
W K
DATA(n)
WA
0
D7
A
C
K
DATA(n+15)
D0
D0
A
C
K
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S
T
A
R
T
1 0 1 0
A
C
K
Next command
tW R(maximum： 5ms)
Command is not accepted for this
Fig.34 Page write cycle
© 2010 ROHM Co., Ltd. All rights reserved.
S
T
O
P
period.
8/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
○Notes on page write cycle
Maximum page number is 16 bytes for this IC.
Any bytes below these can be written.
The page write cycle write time is 5ms at maximum for 16byte bulk write.
It does not stand 5ms at maximum × 16byte = 80ms(Max.).
○Internal address increment
Page write mode
WA7 ----0
----0
----0
-----
WA4
0
0
0
WA3
0
0
0
WA2
0
0
0
0
0
0
-------------
WA0
0
1
0
Increment
---------
---------
0Eh
WA1
0
0
1
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
Significant bit is fixed.
No digit up
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･, which please note.
* 0Eh･･･16 in hexadecimal, therefore, 00001110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite
of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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© 2010 ROHM Co., Ltd. All rights reserved.
9/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
SD A
LINE
S LA VE
A DDRE SS
W
R
I
T
E
W O RD
ADD RES S(n)
WA
7
1 0 1 0 A2 P1P0
S
T
A
R
T
WA
0
R A
/ C
W K
SLA VE
A DDRE SS
R
E
A
D
DA TA (n)
D7
1 0 1 0 A 2 P1P0
A
C
K
S
T
O
P
It is necessary to input 'H'
to the last ACK.
D0
A
C
K
R A
/ C
W K
Fig.35 Random read cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
S LAV E
AD DRES S
1 0 1 0 A 2P 1P 0
S
T
O
P
DA TA (n)
D7
It is necessary to input 'H'
to the last ACK.
D0
A
C
K
R A
/ C
W K
Fig.36 Current read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 P1P0
DATA(n)
D7
R A
/ C
W K
S
T
O
P
DATA(n+x)
D0
D7
A
C
K
A
C
K
D0
A
C
K
Fig.37 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
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© 2010 ROHM Co., Ltd. All rights reserved.
10/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.38(a), Fig.38(b), Fig.38(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level)
may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL
1
2
13
Normal command
14
SDA
Normal command
Fig.38-(a) The case of 14 Dummy clock + START + START+ command input
SCL
Start
Dummy clock×9
Start
1
2
8
Normal command
9
SDA
Normal command
Fig.385-(b) The case of START+9 Dummy clock + START + command input
Start×9
SCL
1
2
3
7
8
9
Normal command
SDA
Normal command
Fig.38-(c) START × 9 + command input
* Start command from START input.
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data so forth.
During internal write,
First write command
S
T
A
R
T
Write command
ACK = HIGH is sent back.
S
T
O
P
S
T Slave
A address
R
T
A
C
K
H
tWR
S
T Slave
A
R address
T
A
C
K
H
…
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
tWR
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
Fig.39 Case to continuously write by acknowledge polling
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11/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.47.) After
execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
SCL
・Rise of SDA
SDA
D0
D1
ACK
SDA
SDA
S
T Slave
A
R address
T
ACK
D0
Enlarged view
Enlarged view
A
A
C Word C D7 D6 D5 D4 D3 D2 D1 D0
K address K
L
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
WP cancel valid area
tWR
Write forced end
WP
Data is not written.
Data not guaranteed
Fig.40 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig.41.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.41 Case of cancel by start, stop condition during slave address input
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© 2010 ROHM Co., Ltd. All rights reserved.
12/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA
(2)The bus electric potential ○
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2Vcc.
Microcontroller
Vcc - ILRPU - 0.2Vcc ≧ VIH
RPU ≦
∴
BR9889GUL-W
RPU
0.8VCC－VIH
IL
SDA terminal
A
Ex.) When Vcc = 3V, IL=10μA, VIH = 0.7Vcc, from (2)
RPU ≦
IL
0.8×3－0.7×3
-6
10×10
IL
≦ 300 ［kΩ］
Bus line
Capacity
CBUS
○Minimum value of RPU
Fig.42 I/O circuit diagram
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC－VOL
≦ IOL
RPU
∴ RPU ≧
VCC－VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise
margin 0.1Vcc.
VOLMAX ≦ VIL-0.1 Vcc
Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from(1),
3－0.4
RPU
≧
3×10
-3
≧ 867 ［Ω］
VOL=0.4［V］
VIL=0.3×3
=0.9［V］
Therefore, the condition (2) is satisfied.
And
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A2, WP process
○Process of device address terminals (A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND.
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it
to pull down or GND.
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© 2010 ROHM Co., Ltd. All rights reserved.
13/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Cautions on microcontroller connection
○Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
ACK
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H' output of microcontroller
and 'L' output of EEPROM.
Fig.43 I/O circuit diagram
Fig.44 Input/output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
(2)The bus electric potential ○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
RPU
RS
(VCC－VOL)×RS
RPU+RS
A
VOL
∴ RS ≦
IOL
Bus line
capacity CBUS
VIL
VIL－VOL－0.1VCC
1.1VCC－VIL
×
RPU
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ,
from(2),
EEPROM
Microcontroller
+ VOL+0.1VCC≦VIL
RS ≦
0.3×3－0.4－0.1×3
×
1.1×3－0.3×3
20×10
3
≦ 1.67［kΩ］
Fig.45 I/O circuit diagram
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
VCC
≦
RS
RPU
I
'L' output
RS
∴ RS ≧
Over currentⅠ
VCC
I
Example）When VCC=3V, I=10mA
'H' output
RS
Microcontroller
EEPROM
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3
-3
10×10
≧ 300［Ω］
Fig.46 I/O circuit diagram
© 2010 ROHM Co., Ltd. All rights reserved.
≧
14/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●I2C BUS input / output circuit
○Input (A2, SCL, WP)
Fig.47 Input pin circuit diagram
○Input/Output (SDA)
Fig.48 Input /output pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR,tOFF,Vbot
tR
tOFF
tOFF
Vbot
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
0
Fig.49 Rise waveform diagram
Vbot
10ms or below
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
A ft er V cc bec omes st able
Af t er Vcc becom es stab le
tDH
tSU:DAT
Fig.50 When SCL='H' and SDA='L'
tSU:DAT
Fig.51
When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
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15/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended
to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Cautions on use
(1)Described numeric values and data are design representative values, and the values are not guaranteed.
(2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3)Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5)Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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© 2010 ROHM Co., Ltd. All rights reserved.
16/17
2010.01 - Rev.A
Technical Note
BU9889GUL-W
●Ordering part number
B
U
Part No.
9
8
8
9
Part No.
G
U
L
Package
GUL : VCSP50L1
- W
W-CELL
E
2
Packaging and forming specification
E2: Embossed tape and reel
1.00±0.05
VCSP50L1(BU9889GUL-W)
Tape
Embossed carrier tape (heat sealing method)
Quantity
3000pcs
Direction
of feed
0.55MAX
1.60±0.05
<Tape and Reel information>
0.10±0.05
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
S
6-φ0.25±0.05
0.05 A B
0.25
0.06 S
(φ0.15)INDEX POST
A
0.5
B B
A
1
0.30
2
3
1pin
P=0.5×2
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
17/17
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.01 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
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More detail product informations and catalogs are available, please contact us.
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R1010A