Memory ICs 256k (32k × 8) Bit SRAM BR62256F-70LL The BR62256F-70LL is a 32768 word × 8 bit asynchronous high-speed CMOS static RAM. It runs on a 5V single power supply, and in addition to its low power consumption and high-speed, its low standby current enables its use in battery backup applications. Applications •General-purpose •1)Features SRAM with a 32768 word × 8 bit configuration. 5) Input / output TTL compatible. 6) Common input / output pin with three output statuses. 7) No clock is necessary (asynchronous static circuit). 8) Input and output data are in the same phase. 9) Low power consumption. 2) High speed read access time of 70ns maximum (Ta = 0 to 70°C). 3) Battery backup is possible. Standby current: 50µA max. (Ta = 0 to 70°C) Data holding current: 3µA max. (Ta = 0 to 70°C) 4) 5V single power supply voltage with ± 10% fluctuation tolerance. •Block diagram A0 A1 A2 A3 A4 A5 A6 A14 ADDRESS ROW BUFFER DECODER 262144BIT (512 × 512) MEMORY CELL ARRAY I / O0 INPUT DATA CONTROL I / O7 COLUMN SWITCH COLUMN DECODER OUTPUT DATA CONTROL ADDRESS BUFFER A7 A 12 A 13 CS OE CONTROL BUFFER WE 1 Memory ICs BR62256F-70LL •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Applied voltage Limits V Pd 850∗2 mW Tstg – 55 ~ + 125 °C Power dissipation Storage temperature Unit – 0.5∗1 ~ + 7.0 VCC Operating temperature Topr 0 ~ + 70 °C I / O voltage VI / O – 0.5 ~ VCC + 0.5 V Input voltage VIN – 0.5 ~ VCC + 0.5 V ∗1 At pulse width of 50ns: – 3.0V (min.) ∗2 Reduced by 8.5mW for each increase in Ta of 1°C over 25°C. •Recommended operating conditions Symbol Min. Typ. Max. Unit Power supply voltage Parameter VCC 4.5 5.0 5.5 V Input high level voltage VIH 2.2 — VCC + 0.5 V Input low level voltage VIL – 0.3 — 0.8 V Ambient temperature Ta — 70 °C 0 •Pin assignments VCC WE A13 A8 A9 A11 OE A10 CS 28 27 26 25 24 23 22 21 20 I / 07 I / 06 I / 05 I / 04 I / 03 19 1 2 3 4 5 6 7 8 9 10 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 18 17 16 11 12 13 I / 00 I / 01 I / 02 Fig.1 •Pin descriptions 2 Pin name I/O VCC — 5V ± 10% power supply Reference voltage for all input / output, 0V VSS — A0 ~ A14 I I / 00 ~ I / 07 I/O Function 32k memory address input 8-bit data I / O CS I Chip segment control input OE I Output enable control input WE I Write enable control input 15 14 VSS Memory ICs BR62256F-70LL •Electrical characteristics (unless otherwise noted, Ta = 0 to + 70°C, V CC Parameter Symbol Min. Typ. Max. Unit Conditions Mesurement Circuit — 0.8 V — — 2.2 — VCC + 0.5 V — — 0.4 V VIL – 0.3 Input high level voltage VIH Output low level voltage VOL Input low level voltage Output high level voltage Input leakage current Output leakage current Average operating current Standby current = 5V ± 10%) — — IOL = 2.1mA Fig.2 VOH 2.4 — — V IOH = – 1.0mA Fig.3 VOH1 VCC × 0.8 — — V IOH = – 0.1mA Fig.3 — +1 µA VIN = 0 ~ VCC Fig.4 Fig.5 ILI –1 –1 — +1 µA VI / O = 0 ~ VCC CS = VIH or CE = VIH or WE = VIL ICCA1 — — 45 mA CS = VIL,I / O: OPEN, Min.cycle time Fig.6 ICCA2 — — 10 mA CS ⬉ 0.2V, f = 1MHz, I / O: OPEN VIL ⬉ 0.2V, VIH ⭌ VCC – 0.2V Fig.6 ISB — — 3 mA CS = VIH ISB1 — — 50 µA CS ⭌ VCC – 0.2V ILO — Fig.7 3 Memory ICs BR62256F-70LL •Measurement circuits VCC VCC VIH VIH WE CS OE VCC 2.1mA WE CS I / O 0 ~ I / O7 OE VSS V V0L VCC 1.0mA I / O 0 ~ I / O7 VSS V0H V VIL VIL Data sets all output to HIGH (Data FF) Data sets all output to LOW (Data 00) Fig.3 Fig.2 VCC VCC ILI VCC A0 ~ A14 WE, CS, OE A VIN = 0 ~ VCC IL0 VCC A I / O 0 ~ I / O7 VSS VI / 0 = 0 ~ VCC VSS CS = VIH or WE = VIL or OE = VIH Fig.4 Fig.5 VCC A VCC ICCA1, ICCA2 ISB1 A CS = VCC – 0.2V VCC I / O 0 ~ I / O7 q CS SW VSS A0 ~ A14 I / O 0 ~ I / O7 VIH or VIL (Min. cycle) CS A0 ~ A14 VSS w VIL VCC OPEN VIH or VIL (1MHz cycle) Sw q: Average operating current ICCA1 Sw w: Average operating current ICCA2 Fig.6 4 Fig.7 OPEN VCC or VSS Memory ICs BR62256F-70LL •Operating modes Control pin Mode Power consumption I/O OE CS X H X Wait state High impedance Standby state H L H Output disable High impedance Operating state L L H Read Data output Operating state X L L Write Data input Operating state WE X: Either VIL or VIH •Input / output capacity (Ta = 25°C, f = 1MHz) Parameter Symbol Min. Typ. Max. Unit CI/O — — 10 pF V I / O = 0V C IN — — 10 pF V IN = 0V Input / output capacity Input capacity Conditions Note: These parameters are not measurements for all conditions, but are sample values. •Part specification Part number Acces time (ns) BR62256F-70LL 70 max. AC test conditions (Ta = 0 to + 70°C, V •Input pulse level: 0.8 to 2.4V CC = 5V ± 10%) Input rise / fall time: 5ns I / O timing level: 1.5V Output load: 1 TTL gate and CL = 100pF •Read cycle Parameter Symbol Min. Max. Unit tRC 70 — ns Address access time tAA — 70 ns Chip enable access time (CS) tACS — 70 ns Read cycle time Output enable access time tOE — 35 ns Output hold time tOH 10 — ns CS output set time tLZ 10 — ns Output enable and output set time tOLZ 5 — ns Chip deselect output floating tCHZ — 30 ns Chip disable output floating tOHZ — 30 ns 5 Memory ICs BR62256F-70LL •Read cycle timing chart 1 (CS = OE = V , CE2 = WE = V ) IL IH tRC Address tAA tOH DOUT Previous Valid Data Valid Data Fig.8 •Read cycle timing chart 2 (WE = V ) IH tRC Address tAA CS tACS tCHZ tLZ OE tOHZ tOE tOLZ Valid Data DOUT High Impedance Fig.9 6 Memory ICs BR62256F-70LL •Write cycle Symbol Min. Max. Unit Write cycle time Parameter tWC 70 — ns Chip select time tCW 60 — ns Address valid time tAW 60 — ns Address setup time tAS 0 — ns Write pulse width tWP 55 — ns WE output delay time tWR 0 — ns CS output delay time tWR1 0 — ns WE output floating time tWHZ — 30 ns Input data set time tDW 30 — ns Input data hold time tDH 0 — ns WE output set time tOW 10 — ns •Write cycle timing chart 1 (WE control) tWC Address tAW tWR OE CS tCW tAS tWP WE tDW DIN tDH Valid Data tWHZ tOW DOUT High Impedance Fig.10 7 Memory ICs BR62256F-70LL •Write cycle timing chart 2 (CS control) tWC Address tAW tWR1 OE tAS tCW CS tWP WE tDW DIN Valid Data tLZ tWHZ DOUT Fig.11 ∗ While the I / O pin is in the output state, input signals should not be applied that are in reverse phase to the output. ∗ The contents noted in this document may fall under the jurisdiction of services pertaining to overseas exchange rates and overseas control regulations (services pertaining to design, construction, specifications), and may require special handling. 8 tDH Memory ICs BR62256F-70LL •Data retention characteristics at low power supply voltage (Ta = 0 to + 70°C) Parameter Symbol Min. Typ. Max. Unit Data retention power supply voltage VDR 2.0 — 5.5 V CS ⭌ VCC – 0.2V Data retention current ICCDR∗1 — 1.0 20 µA VCC = 3.0V, CS ⭌ VCC – 0.2V CS data retention time tCDR 0 — — ns — tR 5 — — ms — Operating recovery time Conditions ∗1 3µA (max.) when Ta = 0 to 40°C •Data retention waveform at low power supply voltage Data Retention Mode 4.5V VCC 4.5V VDR tR tCDR CS ⭌ VCC – 0.2V 2.2V CS 2.2V Fig.12 •External dimensions (Units: mm) 1 14 8.4 ± 0.2 15 1.27 0.40 ± 0.10 0.15 ± 0.1 2.55 ± 0.10 0.20 11.8 ± 0.3 18.0 ± 0.2 28 0.5Min. 0.1 SOP-N28 9