P4C1256L P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM FEATURES VCC Current (Commercial/Industrial) — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70 (Commercial or Industrial) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —28-Pin 600 mil DIP —28-Pin 330 mil SOP DESCRIPTION The P4C1256L is a 262,144-bit low power CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is Access times of 55 ns and 70 ns are available. CMOS HIGH or WE is LOW. is utilized to reduce power consumption to a low level. Package options for the P4C1256L include 28-pin 600 The P4C1256L device provides asynchronous opera- mil DIP and 28-pin 330 mil SOP packages. tion with matching access and cycle times. Memory PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM •• • ROW SELECT A (8) A 262,144-BIT MEMORY ARRAY I/O1 ••• ••• ••• COLUMN I/O • •• ••• ••• INPUT DATA CONTROL I/O2 COLUMN SELECT WE ••• ••• CE A (7) A VCC A0 1 28 A1 2 27 WE A2 3 26 A14 A3 4 25 A13 A4 5 24 A12 A5 6 23 A11 A6 7 22 OE A7 8 21 A10 A8 9 20 CE A9 10 19 I/08 I/01 11 18 I/07 I/02 12 17 I/06 I/03 13 16 I/05 GND 14 15 I/04 DIP (P6), SOP (S11-2) TOP VIEW OE Means Quality, Service and Speed 1Q97 125 P4C1256L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 4.5V ≤ VCC ≤ 5.5V Industrial (-40°C to 85°C) 4.5 ≤ VCC ≤ 5.5V MAXIMUM RATINGS Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol Parameter Min Max Unit VCC Supply Voltage with Respect to GND -0.5 7.0 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current >200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter Min Test Conditions VOH Output High Voltage (I/O0 - I/O7) IOH = –1mA, VCC = 4.5V VOL Output Low Voltage (I/O0 - I/O7) IOL = 2.1mA VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current GND ≤ VIN ≤ VCC ILO Output Leakage Current GND ≤ VOUT ≤ VCC CE ≥ VIH ISB VCC Current TTL Standby Current (TTL Input Levels) ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) Max Unit V 2.4 0.4 V 2.2 VCC + 0.3 V -0.5 0.8 V Ind'l. Com'l. -5 -2 +5 +2 µA Ind'l. Com'l. -5 -2 +5 +2 µA VCC = 5.5V, IOUT = 0 mA CE = VIH 3 mA VCC = 5.5V, IOUT = 0 mA CE ≥ VCC -0.2V 100 µA 126 P4C1256L CAPACITANCES (VCC = 5.0V, TA = 25˚C, F = 1.0 MHz) Symbol CIN COUT Test Conditions Max Unit Input Capacitance VIN = 0V 7 pF Output Capacitance VOUT = 0V 9 pF Parameter POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Industrial * ** -55 -70 -55 70 85 70 85 15 25 -70 15 25 Unit mA mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. **As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -70 -55 Max Min Min Max Unit tRC Read Cycle Time tAA Address Access Time 55 70 ns tAC Chip Enable Access Time Output Hold from Address Change 55 70 ns tOH 55 70 ns 5 5 ns 5 5 ns tLZ Chip Enable to Output in Low Z tHZ Chip Disable to Output in High Z 20 25 ns tOE Output Enable Low to Data Valid 30 35 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 5 5 25 20 0 ns 0 55 127 ns ns 70 ns P4C1256L OE CONTROLLED)(1) READ CYCLE NO. 1 (OE t RC (5) ADDRESS t AA OE t OE t OLZ t OH (4) CE t AC t AC t OHZ (4) t HZ (4) (4) DATA OUT NOTES: 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. 1. WE is HIGH for READ cycle. 2. CE is LOW and OE is LOW for READ cycle. 3. ADDRESS must be valid prior to, or coincident with CE transition LOW. READ CYCLE NO. 2 (ADDRESS CONTROLLED) t RC (5) ADDRESS t AA t OH DATA OUT DATA VALID PREVIOUS DATA VALID CE CONTROLLED) READ CYCLE NO. 3 (CE tRC CE1 tLZ (8) tHZ tAC DATA OUT DATA VALID HIGH IMPEDANCE ICC VCC SUPPLY CURRENT tPD tPU ISB 128 P4C1256L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) -55 -70 Symbol Parameter tWC Write Cycle Time 55 70 ns tCW Chip Enable Time to End of Write 50 60 ns tAW Address Valid to End of Write 50 60 ns tAS Address Set-up Time 0 0 ns tWP Write Pulse Width 40 50 ns tAH Address Hold Time 0 0 ns tDW Data Valid to End of Write 25 30 ns tDH Data Hold Time 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write Min Max Min Max 25 30 5 5 (9) ADDRESS tCW CE tAW tWP tAH WE tAS t DW DATA IN tDH DATA VALID (4,7) (4) tOW tWZ (7) DATA OUT DATA UNDEFINED HIGH IMPEDANCE Notes: 6. CE and WE must be LOW for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. 129 ns ns WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE tWC Unit P4C1256L CE CONTROLLED)(6) TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE tWC (9) ADDRESS tAS tCW CE tAH tAW tWP WE tDW tDH DATA VALID DATA IN (6) DATA OUT HIGH IMPEDANCE TRUTH TABLE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times GND to 3.0V 3ns Input Timing Reference Level 1.5V 1.5V Output Timing Reference Level Output Load See Figures 1 and 2 Mode CE OE WE I/O Power Standby Standby H X X X X X High Z Standby High Z Standby DOUT Disabled L H H High Z Active Read L L H DOUT Active Write L X L High Z Active +5V R TH = 638.7 Ω 1800 Ω D OUT DOUT 990 Ω 30pF* (5pF* for t HZ , t LZ , t OHZ , t OLZ t, WZ and t OW ) Figure 1. Output Load VTH = 1.77 V 30pF* (5pF* for t HZ , t LZ , t OHZ, t OLZ , t WZ and t OW ) Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the high speed of the P4C1256L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. 130 To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with DOUT to match 639Ω (Thevenin Resistance). P4C1256L DATA RETENTION Symbol Parameter Test Conditions Min Max Unit 2.0 5.5 V VDR VCC for Data Retention CE ≥ VCC -0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V ICCDR (1) Data Retention Current VDR = 2.0V 30 µA VDR = 3.0V 50 µA tCDR Chip Deselect to Data Retention Time tR Operating Recovery Time See Retention Waveform 0 ns 5 ms 1. CE ≥ VDR -0.2V LOW VCC DATA RETENTION WAVEFORM Data Retention Mode VCC VDR 4.5V tCDR CE 4.5V tR CE ≥ VDR -0.2V 2.2V 131 2.2V P4C1256L TEMPERATURE RANGE SUFFIX PACKAGE SUFFIX Package Suffix Temperature Description Range Suffix Description P Plastic DIP, 600 mil wide standard S SOP, 330 mil wide standard C I Commercial Temperature Range, 0˚C to +70˚C Industrial Temperature Range, -40˚C to +85˚C ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4C 1256L ss p t Temperature Range: C,I Package Code: P, S Speed (Access/Cycle Time): 55,70 Device Number: 1256L Static RAM Prefix SELECTION GUIDE The P4C1256L is available in the following temperature, speed and package options. Temperature Range Package Speed (ns) -55 -70 Commercial Temperature Plastic DIP 600 Plastic SOP 330 -55PC -55SC -70PC -70SC Industrial Temperature Plastic DIP 600 -55PI -55SI -70PI Plastic SOP 330 132 -70SI